DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 15-16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 9,825,631).
In regards to claim 1, Cho discloses of an impedance calibration circuit, comprising: a calibration controller (220) configured to receive an impedance calibration command and generate a calibration enable signal (ZQEN) based on the impedance calibration command; and a calibration circuit (500) connected to an external resistor (RZQ) provided in a board through an impedance pad (401), the calibration circuit being configured to, in response to the calibration enable signal (ZQEN): generate a first reference voltage code based on a voltage level of a selected reference voltage (VTG) becoming the same as a first voltage of a first node (N22) coupled to the impedance pad (401), the first voltage being based on an initial pull-up control code (from 540); generate a pull-up control code (PUCD) for driving the first node (N22) based on the first reference voltage code (see Fig 13); generate a second reference voltage code based on the voltage level of the selected reference voltage (VTG) becoming the same as a second voltage of a second node (N21), the second voltage being based on the pull-up control code (PUCD); and generate a pull-down control code (PDCD) for driving the second node (N21) based on the second reference voltage code (see Fig 13).
In regards to claim 2, Cho discloses of the impedance calibration circuit of claim 1, wherein the calibration circuit includes: a pull-up driver (520) coupled between a power supply voltage (VDDQ) and the first node (N22), the pull-up driver (520) configured to drive the first node (N22) with the first voltage based on the initial pull-up control code; a first comparator circuit (531) configured to generate a first comparison signal by comparing the first voltage with the selected reference voltage (VTG); a reference voltage generator (510) configured to generate a plurality of reference voltages (VTG1, VTG2); a replica pull-up driver (545) coupled between the power supply voltage (VDDQ) and the second node (N21), the replica pull-up driver (545) configured to drive the second node (N21) with the second voltage based on the pull-up control code; a pull-down driver (560) coupled between the second node (N21) and a ground voltage (VSS); a second comparator circuit (581) configured to generate a second comparison signal (CS22) by comparing the second voltage with the selected reference voltage (VTG); and a control/code generation circuit configured to: select the selected reference voltage from among the plurality of reference voltages (VTG1, VTG2); generate the first reference voltage code based on the first comparison signal (CS21); generate the pull-up control code (PUCD) based on the first reference voltage code; generate the second reference voltage code based on the second comparison signal (CS22); generate the pull-down control code (PDCD) based on the second reference voltage code; and provide the pull-down control code (PDCD) to the pull-down driver (560, see Fig 13).
In regards to claim 3, Cho discloses of the impedance calibration circuit of claim 2, wherein the control/code generation circuit and the first comparator circuit (531) constitute a first loop, the control/code generation circuit and the first comparator circuit (531) being configured to generate the first reference voltage code and generate the pull-up control code (PUCD) based on the first reference voltage code, and wherein the control/code generation circuit and the second comparator circuit (581) constitute a second loop, the control/code generation circuit and the second comparator circuit (581) being configured to generate the second reference voltage code and generate the pull-down control code (PDCD) based on the second reference voltage code (see Fig 13).
In regards to claim 15, Cho discloses of a semiconductor memory device comprising: an external resistor (RZQ) provided in a board; and a plurality of memory dies mounted on the board and commonly connected to the external resistor (RZQ, see Figs 1-3, 22), wherein each of the plurality of memory dies includes an impedance calibration circuit connected to the external resistor (RZQ) through an impedance pad (401), wherein the impedance calibration circuit, in response to an impedance calibration command (ZQEN), is configured to perform an impedance calibration operation by: generating a first reference voltage code based on a voltage level of a selected reference voltage (VTG) becoming the same as a first voltage of a first node (N22) coupled to the impedance pad (401), the first voltage being based on an initial pull-up control code; generating a pull-up control code (PUCD) for driving the first node (N22) based on the first reference voltage code; generating a second reference voltage code based on the voltage level of the selected reference voltage (VTG) becoming the same as a second voltage of a second node (N21), the second voltage being based on the pull-up control code (PUCD); and generating a pull-down control code (PDCD) for driving the second node based on the second reference voltage code (see Fig 13).
In regards to claim 16, Cho discloses of the semiconductor memory device of claim 15, wherein the impedance calibration circuit includes: a calibration controller (220) configured to receive an impedance calibration command and generate a calibration enable signal (ZQEN) based on the impedance calibration command ; and a calibration circuit connected to the external resistor (RZQ) through the impedance pad (401), the calibration circuit configured to perform the impedance calibration operation in response to the calibration enable signal (ZQEN), wherein the calibration circuit includes: a pull-up driver (520) coupled between a power supply voltage (VDDQ) and the first node (N22), the pull-up driver (520) configured to drive the first node (N22) with the first voltage based on the initial pull-up control code; a first comparator circuit (531) configured to generate a first comparison signal (CS21) by comparing the first voltage with the selected reference voltage (VTG); a reference voltage generator (510) configured to generate a plurality of reference voltages (VTG1, VTG2); a replica pull-up driver (545) coupled between the power supply voltage (VDDQ) and the second node (N21), the replica pull-up driver (545) configured to drive the second node (N21) with the second voltage based on the pull-up control code (PUCD); a pull-down driver (560) coupled between the second node (N21) and a ground voltage (VSS); a second comparator circuit (581) configured to generate a second comparison signal (CS22) by comparing the second voltage with the selected reference voltage (VTG); and a control/code generation circuit configured to: select the selected reference voltage (VTG) from among the plurality of reference voltages (VTG1, VTG2); generate the first reference voltage code based on the first comparison signal (CS21); generate the pull-up control code (PUCD) based on the first reference voltage code; generate the second reference voltage code based on the second comparison signal (CS22); generate the pull-down control code (PDCD) based on the second reference voltage code; and provide the pull-down control code (PDCD) to the pull-down driver (560, see Fig 13).
In regards to claim 20, Cho discloses of an impedance calibration circuit, comprising: a calibration controller (220) configured to receive an impedance calibration command and generate a calibration enable signal (ZQEN) based on the impedance calibration command; and a calibration circuit connected to an external resistor (RZQ) provided in a board through an impedance pad (401), the calibration circuit, in response to the calibration enable signal, configured to: generate a first reference voltage code based on a voltage level of a selected reference voltage (VTG) becoming the same as a first voltage of a first node (N12) coupled to the impedance pad (401), the first voltage being based on an initial pull-down control code; generate a pull-down control code (PDCD) for driving the first node (N12) based on the first reference voltage code (see Fig 8); generate a second reference voltage code based on the voltage level of the selected reference voltage (VTG) becoming the same as a second voltage of a second node (N11), the second voltage being based on the pull-down control code (PDCD); and generate a pull-up control code (PUCD) for driving the second node (N11) based on the second reference voltage code, and wherein the calibration circuit includes: a pull-down driver (460) coupled between the first node (N12) and a ground voltage (VSS), the pull-down driver (460) configured to drive the first node (N12) with the first voltage based on the initial pull-down control code; a first comparator circuit (481) configured to generate a comparison signal (CS12) by comparing the first voltage with the selected reference voltage (VTG); a reference voltage generator (410) configured to generate a plurality of reference voltages (VTG1, VTG2); and a control/code generation circuit configured to: select the selected reference voltage from among the plurality of reference voltages (VTG1, VTG2); generate the first reference voltage code based on the first comparison signal (CS12); generate the pull-down control code (PDCD) based on the first reference voltage code; and provide the pull-down control code (PDCD) to the pull-down driver (460, see Fig 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 9,825,631) in view of Kavala et al. (US 2022/0148630).
In regards to claims 17 and 18, Cho discloses of the semiconductor memory device as found within the explanation of claim 15 above, however, Cho does not explicitly disclose of wherein each of the plurality of memory dies is a nonvolatile memory device, wherein the nonvolatile memory device includes: a memory cell array includes a plurality of nonvolatile/volatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit-lines; and a data input/output (I/O) circuit connected to the page buffer circuit, the data I/O circuit including an output driver, and wherein the impedance calibration circuit is configured to apply the pull-up control code and the pull-down control code to the output driver.
Kavala discloses of a semiconductor memory device comprising: an external resistor (RZQ) provided in a board; and a plurality of memory dies mounted on the board and commonly connected to the external resistor (RZQ, see Figs 12-15), wherein each of the plurality of memory dies includes an impedance calibration circuit connected to the external resistor (RZQ) through an impedance pad (201), wherein the impedance calibration circuit, in response to an impedance calibration command (ZQEN), is configured to perform an impedance calibration operation by: generating a first reference voltage code based on a voltage level of a selected reference voltage (VREF) becoming the same as a first voltage of a first node (at 201) coupled to the impedance pad (201), the first voltage being based on an initial pull-up control code; generating a pull-up control code (PUZQCD) for driving the first node (at 201) based on the first reference voltage code; generating a second reference voltage code based on the voltage level of the selected reference voltage (VREF) becoming the same as a second voltage of a second node (N11), the second voltage being based on the pull-up control code (PUZQCD); and generating a pull-down control code (PDZQCD) for driving the second node (N11) based on the second reference voltage code (see Fig 2); wherein each of the plurality of memory dies is a nonvolatile memory device (see Paragraph 0129), and/or wherein the memory dies are volatile (0041), wherein the nonvolatile/volatile memory device includes: a memory cell array (510) includes a plurality of nonvolatile/volatile memory cells (see Fig 12); a page buffer circuit/ I/O gating circuit (530) connected to the memory cell array (510) through a plurality of bit-lines (BL); and a data input/output (I/O) circuit (540) connected to the page buffer circuit/ I/O gating circuit (530), the data I/O circuit including an output driver, and wherein the impedance calibration circuit (570, see Paragraphs 0133, 0146) is configured to apply the pull-up control code (PUZQCD) and the pull-down control code (PDZQCD) to the output driver (see Figs 2, 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have the memory dies being nonvolatile or volatile and including a page buffer circuit or I/O gating circuit and data output circuit connected to the impedance calibration circuit as taught by Kavala for improving function of the semiconductor memory device by preventing the detrimental effects of impedance/calibration mismatching in a memory device.
Claim 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 9,825,631) in view of Seo et al. (US 2022/0165321).
In regards to claim 19, Cho discloses of the semiconductor memory device of claim 15 as found within the explanation above.
However, Cho does not explicitly disclose of wherein, one of the plurality of memory dies is designated as a master die and a rest of the plurality of memory dies except the master die is designated as a plurality of slave dies, the master die is mounted on the board; the plurality of slave dies are stacked on the master die; and the master die is connected to respective ones of the plurality of slave dies through respective ones of a plurality of wires.
Seo discloses of a semiconductor memory device comprising: an external resistor (RZQ) provided in a board; and a plurality of memory dies mounted on the board and commonly connected to the external resistor (RZQ, see Figs 1-2, 7-8), wherein each of the plurality of memory dies includes an impedance calibration circuit connected to the external resistor (RZQ) through an impedance pad (401), wherein the impedance calibration circuit, in response to an impedance calibration command (ZQEN1), is configured to perform an impedance calibration operation by: generating a first reference voltage code based on a voltage level of a selected reference voltage (VREF) becoming the same as a first voltage of a first node (N12) coupled to the impedance pad (401), the first voltage being based on an initial pull-down control code; generating a pull-down control code (PDCD) for driving the first node (N12) based on the first reference voltage code; generating a second reference voltage code based on the voltage level of the selected reference voltage (VTG1) becoming the same as a second voltage of a second node (N11), the second voltage being based on the pull-up control code (PDCD); and generating a pull-up control code (PUCD) for driving the second node (N11) based on the second reference voltage code (see Fig 8) and wherein, one of the plurality of memory dies is designated as a master die (530) and a rest of the plurality of memory dies except the master die (530) is designated as a plurality of slave dies (540, 550, see Fig 18), the master die (530) is mounted on the board; the plurality of slave dies (540, 550) are stacked on the master die (530); and the master die (530) is connected to respective ones of the plurality of slave dies (540, 550) through respective ones of a plurality of wires 561-562, see Fig 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have the memory dies comprising a master memory die and a plurality of slave memory dies as taught by Seo for providing proper impedance calibration amongst all of the dies within the semiconductor memory device.
Allowable Subject Matter
Claims 4-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 4, the prior art does not disclose of the impedance calibration circuit of claim 2, further comprising: an oscillator configured to generate a clock signal in response to the calibration enable signal, and wherein the control/code generation circuit includes: a selection signal generator configured to generate selection signals and inverted selection signals based on the clock signal; a reference voltage selector configured to output the selected reference voltage by selecting at least a portion of the plurality of reference voltages based on the selection signals and the inverted selection signals during each of a plurality of cycles; a first reference voltage code generator configured to generate the first reference voltage code when the voltage level of the selected reference voltage becomes the same as the first voltage based on the first comparison signal; a pull-up code generator configured to generate the pull-up control code based on the clock signal and the first reference voltage code; a second reference voltage code generator configured to generate the second reference voltage code when the voltage level of the selected reference voltage becomes the same as the second voltage based on the second comparison signal; and a pull-down code generator configured to generate the pull-down control code based on the clock signal and the second reference voltage code, nor would it have been obvious to one of ordinary skill in the art to do so. Claims 5-14 are also objected to as being dependent on claim 4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chung (US 2024/0290378)
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844