DETAILED ACTION
This application is responsive to the following: The application filed on November 4, 2024 and information disclosure statement filed on October 9, 2025.
Claims 1-19 are pending. Claim 1 is Independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 9, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujiwara et al (US 20020041529).
Regarding Independent Claim 1, Fujiwara teaches a memory (Fig. 2: 50), comprising:
a plurality of data input/output pins (Fig. 2: 3a), configured to receive or output working serial data (para 93 “Signals (input<0> to input<5>) may transmit serial data”) when the memory is in a working mode, one of the data input/output pins being a target data input/output pin (Fig. 2: input<5:0>), and the target data input/output pin being configured to receive test serial data when the memory is in a test mode (Fig. 2: TestMode); and
a data input/output selector (Fig. 2: 12), a first input terminal (Fig. 2: CoreCntrl<5:0>) of the data input/output selector receiving the test serial data received by the target data input/output pin (Fig. 2: input<5:0>), and
the data input/output selector (Fig. 2: 12) being configured to: in the test mode (Fig. 2: TestMode), separately transmit, to transmission paths (Fig. 2: CNtrol<5:0>) corresponding to one corresponding data input/output pin in the memory, each bit of data in the test serial data (Fig. 2: Core Cntrol<5:0>) received by the target data input/output pin.
Regarding Claim 2, Fujiwara teaches the limitations of claim 1. Fujiwara further teaches wherein a second input terminal (Fig. 2: 3a) of the data input/output selector (Fig. 2: 12) receives a plurality of pieces of working serial data (para 93 “Signals (input<0> to input<5>) may transmit serial data”) received by the plurality of data input/output pins; and
the data input/output selector (Fig. 2: 12) is further configured to: in the working mode, separately transmit, to the transmission paths corresponding to the one corresponding data input/output pin, working serial data received by the one corresponding data input/output pin (para 157 “Selector 12 may also receive signal group input<5:0>; and signal TestMode. When signal TestMode is low, selector 12 may output signal group CoreCntrol<5:0>; to memory 14 as signal group Cntrol<5:0>;. When signal TestMode is high, selector 12 may output signal group input<5:0>; to memory 14 as signal group Cntrol<5:0>;.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al (US 20020041529) in view of Kornachuk et al (US 6044481 A).
Regarding Claim 3, Fujiwara teaches the limitations of claim 2. Fujiwara fails to teach that the selector comprises a plurality of selectors.
Kornachuk teaches a plurality of selectors (Fig. 2D: 210) each of the first selectors corresponds to one data input/output pin (Fig. D0 to Dn-1, Q0 to Qn-1, DQ0 to DQn-1).
Its obvious that if you have multiple pins providing different signals that there must be some way of muxing the signals such that each signal is separately selectable.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kornahuck to the teachings of Fujiwara to produce a memory device with a plurality of selector circuits to select between test and working data. Where each selector corresponds to a separate input/output pin.
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et al (US 20020041529) in view of Yoon (US 20080082900 A1).
Regarding Claim 13, Fujiwara teaches a serial-to-parallel circuit (Fig. 2: 9), a first input terminal (Fig. 2: Dec_Trg) of the serial-to-parallel circuit (Fig. 2: 9) receiving the test serial data (Fig. 2: Dec_Trg) when the memory is in the test mode (Fig. 2: TestMode),
the serial-to-parallel circuit being configured to convert the test serial data (Fig. 2: Dec_Trg) into test parallel data (Fig. 2: CoreCntrol <5:0> )when the memory is in the test mode (Fig. 2: TestMode); and
However, Fujiwara fails to teach the serial-to-parallel circuit being configured to convert each piece of working serial data into corresponding working parallel data when the memory is in the working mode.
Yoon teaches teach the serial-to-parallel circuit (Fig. 2: 130) being configured to convert each piece of working serial data (Fig. 2: DQ<7:0>) Into corresponding working parallel data when the memory is in the working mode.
Turning serial data into parallel data for the purpose of sending it to a memory block is useful as the data can be written to the memory more quickly than processing the data serially.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Yoon to the teachings of Fujiwara to produce a memory devices with separate serial-to-parallel circuits for the test data and for working serial data input to the device.
Allowable Subject Matter
Claims 4-12 and 14-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 is allowable for teaching that the selector circuits comprise two selector circuits that output to two separate transmission paths for input/output pin. Both Kornachuk and Fujiwara only teach a single selector circuit outputting to single transmission path for each data input/output pin. Therefore, this claim would be allowable if written in independent form.
Claim 5 is allowable for teaching a selector circuit that has a reverse data pin and work mode enable pin in addition to a test pin and the limitations of claim 1. Other references don’t teach the selectors with this many different functions and enable pins. Therefore, this claim would be allowable if written in independent form.
Claims 6-12 would be allowable for being dependent on claim 5.
Claim 14 would be allowable for teachings that the serial-to-parallel circuit comprises a plurality of circuits. Both Yoon and Fujiwara are silent with respect to how many circuits the serial-to-parallel circuits they teach comprise. Therefore, this claim would be allowable if written in independent form.
Claims 15-16 would be allowable for being dependent on claim 14.
Claim 17 is allowable for teaching data mask pins and a check code data selector in addition to the limitations of claim 1. None of the references applied taught these features. Other refences teach one limitation but not the other, such as Bains (US 20100064100 A1), which teaches a data mask pins. Therefore, this claim would be allowable if written in independent form.
Claim 18-19 would be allowable for being dependent on claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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