FINAL OFFICE ACTION
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2019/0303230 to Liberty et al. (hereinafter Liberty) in view of U.S. Patent No. 8,839,032 to Walton et al. (hereinafter Walton).
Liberty discloses:
1. A device comprising:
a processor core (para. [0024] and Fig. 2, execution units 210); and
a management core (para. [0025] and Fig. 2, control logic 220) configured to:
detect an error of the processor core (para. [0025] and Fig. 4, block 405); and
process the error independently from the processor core (para. [0035] and Fig. 4, block 415).
Liberty does not disclose expressly:
store the error in a non-volatile storage separate from the management core.
Walton teaches storing the error in a non-volatile storage separate from the management core (col. 5, lns. 3-24).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Liberty by storing the error in a non-volatile storage separate from the management core, as taught by Walton. A person of ordinary skill in the art would have been motivated to do so in order to allow for improvements to the error manager, improving user satisfaction, as discussed by Walton (col. 12, lns. 32-40).
Claims 2, 10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Liberty and Walton in view of U.S. Patent Pub. No. 2008/0126852 to Brandyberry et al. (hereinafter Brandyberry).
Liberty does not disclose express:
2. The device of claim 1, wherein the management core is further configured to store an error log of the error in a non-volatile storage.
Brandyberry teaches wherein the management core is further configured to store an error log of the error in a non-volatile storage (para. [0053]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Liberty by storing an error log, as taught by Brandyberry. A person of ordinary skill in the art would have been motivated to do so in order to have the information regarding the error available “for use in error diagnosis even after a reboot,” as discussed by Brandyberry (para. [0053]).
Modified Liberty discloses:
10. A system comprising:
a memory (Liberty - Fig. 1, memory devices 112, 140);
a baseboard controller comprising a non-volatile storage (Brandyberry - para. [0053] and Fig. 1, BMC 102); and
a processor separate from the baseboard controller and coupled to the memory (Liberty - Fig. 1, computing system 100) and comprising:
a processor core (Liberty - Fig. 1, processor cores 105);
a register for storing an error state of the processor core (Liberty - Fig. 2, registers 230); and
a management core (Liberty - Fig. 2, control logic 220) configured to:
detect an error of the processor core (Liberty - para. [0025] and Fig. 4, block 405);
control read access to the error state in the register (Liberty - para. [0026]);
store the error state in the non-volatile storage (Brandyberry - para. [0053]); and
process the error independently from the processor core (Liberty - para. [0035] and Fig. 4, block 415).
15. A method comprising:
detecting, by a management core of a processor, an error of a processor core of the processor (Liberty - para. [0025] and Fig. 4, block 405);
storing, in a non-volatile storage of a baseboard controller separate from the processor, an error log of the error (Brandyberry - para. [0053]);
controlling, by the management core, read access to an error state in a register based on an error policy (Liberty - para. [0026]); and
processing the error independently from the processor core while the processor core continues operations (Liberty - para. [0035] and Fig. 4, block 415).
Claims 3, 5, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Liberty in view of Walton and Brandyberry, and further in view of U.S. Patent Pub. No. 2016/0179641 to Maeda et al. (hereinafter Maeda).
Liberty and Brandyberry discose:
3. The device of claim 2, wherein the management core is configured to interface with an external management controller to store the error log in the non-volatile storage (paras. [0046], [0052]).
Liberty and Brandberry do not disclose expressly providing the error log to the external management controller in response to a ready signal from the external management controller.
Maeda teaches providing the error log to the external management controller in response to a ready signal from the external management controller (paras. [0097], [0098]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Liberty and Brandyberry by providing the error log, as taught by Maeda. A person of ordinary skill in the art would have been motivated to do so in order to avoid decreasing I/O performance, as discussed by Maeda (para. [0092]).
Modified Liberty discloses:
5. The device of claim 3, wherein the external management controller is configured to send the ready signal by querying the management core for errors (Maeda – para. [0098]).
9. The device of claim 3, wherein the management core is further configured to clear the error log in response to providing the error log to the external management controller (Maeda – para. [0062], [0063]).
Allowable Subject Matter
Claims 4, 6-8, 11-14, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Philip Guyton whose telephone number is (571)272-3807. The examiner can normally be reached M-F 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHILIP GUYTON/Primary Examiner, Art Unit 2113