DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 18 January 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
The claims use the phrase “special cache coherency operation”. This phrase is not used outside of the Applicant’s patent applications. It is unclear what cache coherency operations are to be considered special and what cache coherency operations are not to be considered special. The specification provides examples of special cache coherency operations but does not give any indication as to the bounds of the scope of the phrase. Applicant could replace this phrase with a list of operations disclosed in the specification, which would render the claims definite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 24, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mannava et al. (US 10,970,225).
In regards to claims 1, 24, and 25, Mannava teaches a computer system for cache management comprising:
a memory which stores instructions (“In this first example, it is assumed that the master device is executing software, and at some point executes an instruction to perform a CMO within its local cache.”, Col. 16, lines 60-62);
one or more processors coupled to the memory (“The apparatus includes a plurality of master devices 10, 20, 30 that are coupled via an interconnect 40 to a slave device 55. The slave device in this example is coupled to main memory 60.”, Col. 11, lines 35-38) wherein the one or more processors, when executing the instructions which are stored, are configured to:
access a plurality of processor cores, wherein each processor of the plurality of processor cores includes a shared local cache (“In the example shown it is assumed that the master devices 10, 20 are fully coherent master devices whose caches 15, 25 are kept coherent with caches in a lower level of the cache hierarchy, such as a system cache 50 provided within the interconnect 40.”, Col. 11, lines 48-52), and wherein the plurality of processor cores implements special cache coherency operations (“One or more of the requester elements may be able to issue cache maintenance operation (CMO) requests that specify a memory address range, and are used to cause a block of data associated with the specified memory address range to be pushed through at least one level of the cache hierarchy to a determined visibility point in order to make that block of data visible to one or more other requester elements in the plurality of requester elements.”, Col. 4, lines 13-20);
couple an evict buffer to the plurality of processor cores, wherein the evict buffer is shared among the plurality of processor cores, and wherein the evict buffer enables delayed writes (“One or more of the requester elements may be able to issue cache maintenance operation (CMO) requests that specify a memory address range, and are used to cause a block of data associated with the specified memory address range to be pushed through at least one level of the cache hierarchy to a determined visibility point in order to make that block of data visible to one or more other requester elements in the plurality of requester elements.”, Col. 12, line 64 - Col. 13, line 2);
monitor evict buffer writes, wherein the monitoring evict buffer writes identifies a special cache coherency operation (“As a still further example, when the given requester element detects a need to write the item of data to a point of persistence, the given requester element may be arranged to issue the combined write and cache maintenance operation request, so that performance of the cache maintenance operation will cause the item of data to be pushed to the point of persistence. In particular, when it is determined necessary to write an item of data to a point of persistence, it is not typically possible for the write request itself to specify that the data needs to be written to the point of persistence, and instead a separate cache maintenance operation needs to be performed to achieve that effect. However, when using the techniques described herein, there is no need to defer issuance of the cache maintenance operation request until a completion signal has been received for the write, and instead a combined write and cache maintenance operation request can be issued directly from the given requester element.”, Col. 10, lines 11-30; “This can in some instances allow a level of cache to form a point of persistence, or for a write buffer within a memory controller to form a point of persistence.”, Col. 8, lines 46-49); and
mark an evict buffer entry, wherein the marking corresponds to the special cache coherency operation that was identified (“As a still further example, when the given requester element detects a need to write the item of data to a point of persistence, the given requester element may be arranged to issue the combined write and cache maintenance operation request, so that performance of the cache maintenance operation will cause the item of data to be pushed to the point of persistence. In particular, when it is determined necessary to write an item of data to a point of persistence, it is not typically possible for the write request itself to specify that the data needs to be written to the point of persistence, and instead a separate cache maintenance operation needs to be performed to achieve that effect. However, when using the techniques described herein, there is no need to defer issuance of the cache maintenance operation request until a completion signal has been received for the write, and instead a combined write and cache maintenance operation request can be issued directly from the given requester element.”, Col. 10, lines 11-30; “This can in some instances allow a level of cache to form a point of persistence, or for a write buffer within a memory controller to form a point of persistence.”, Col. 8, lines 46-49), and wherein the marking enables management of cache evict duplication (“If the ‘no’ path is followed from step 650, it may be determined whether the CMO specifies a memory address for which a pending write is present in a write buffer of the requester element. In that condition, it will be necessary to flush the pending write from the buffer in order to send the write request downstream, and again the process can proceed to step 665 where the combined condition is determined to be present.”, Col. 22, lines 14-21).
In regards to claim 2, Mannava further teaches that the special cache coherency operation that was identified comprises a global snoop operation (“For example, the cache coherency circuitry 45 may employ a snoop-based cache coherency mechanism, whereby in response to a request from one of the coherent master devices 10, 20, it can issue snoop requests to one or more other fully coherent master devices 10, 20 in order to determine whether those other coherent master devices have cached copies of the data that the requesting coherent master device is seeking to access.”, Col. 11, lines 60-67).
In regards to claim 3, Mannava further teaches that the global snoop operation is initiated from an agent (“For example, the cache coherency circuitry 45 may employ a snoop-based cache coherency mechanism, whereby in response to a request from one of the coherent master devices 10, 20, it can issue snoop requests to one or more other fully coherent master devices 10, 20 in order to determine whether those other coherent master devices have cached copies of the data that the requesting coherent master device is seeking to access.”, Col. 11, lines 60-67) within a globally coherent system (“It should be noted that not all of the master devices needs to be fully coherent master devices, and by way of example an input/output (I/O) coherent master device 30 is shown.”, Col. 12, lines 11-13, the phrasing of this sentence implies that there are also embodiments envisaged where all master devices are fully coherent).
In regards to claim 4, Mannava further teaches that the special cache coherency operation that was identified comprises a cache maintenance operation (CMO) (“As a still further example, when the given requester element detects a need to write the item of data to a point of persistence, the given requester element may be arranged to issue the combined write and cache maintenance operation request, so that performance of the cache maintenance operation will cause the item of data to be pushed to the point of persistence.”, Col. 10, lines 11-18).
In regards to claim 5, Mannava further teaches that the CMO comprises a cache block operation (CBO) CLEAN instruction (“Such write operations may be allowed to be the subject of combined write and CMO requests for a variety of CMOs, such as a CleanShared(Persist) CMO (where cleaning of all cached copies (i.e. into the non dirty state) and writing back to memory (or PoP) of dirty data is required), and in some instances a CleanInvalid CMO (where all cached copies are invalidated, and writing back to memory of dirty data is required).”, Col. 22, lines 55-62).
In regards to claim 6, Mannava further teaches that the special cache coherency operation that was identified causes dirty data to be written (“Such write operations may be allowed to be the subject of combined write and CMO requests for a variety of CMOs, such as a CleanShared(Persist) CMO (where cleaning of all cached copies (i.e. into the non dirty state) and writing back to memory (or PoP) of dirty data is required), and in some instances a CleanInvalid CMO (where all cached copies are invalidated, and writing back to memory of dirty data is required).”, Col. 22, lines 55-62) into the evict buffer (“It may be that the slave device includes some local buffering in which write data can be stored prior to being written out to main memory, and in that instance those write buffers within the slave device 55 may be viewed as a visibility point to which the write data needs to be pushed.”, Col. 12, line 64 - Col. 13, line 2).
In regards to claim 7, Mannava further teaches receiving an additional evict buffer write by the evict buffer (“If the ‘no’ path is followed from step 650, it may be determined whether the CMO specifies a memory address for which a pending write is present in a write buffer of the requester element. In that condition, it will be necessary to flush the pending write from the buffer in order to send the write request downstream, and again the process can proceed to step 665 where the combined condition is determined to be present.”, Col. 22, lines 14-21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Mannava et al. (US 10,970,225) in view of Yuki et al. (JP 2015-210577) as supported by its translation.
In regards to claim 8, Mannava further teaches performing a compare between the additional evict buffer write and the evict buffer entry that was marked to detect duplication (“If the ‘no’ path is followed from step 650, it may be determined whether the CMO specifies a memory address for which a pending write is present in a write buffer of the requester element. In that condition, it will be necessary to flush the pending write from the buffer in order to send the write request downstream, and again the process can proceed to step 665 where the combined condition is determined to be present.”, Col. 22, lines 14-17). Mannava fails to teach that the compare is a fast compare. Yuki teaches that the compare is a fast compare (“The determination unit 114 stores the first partial address information represented by a predetermined number of bits on the lower side of the source address included in the subsequent load instruction LD input following the store instruction ST, and the store information storage unit 112 stores the first partial address information. The first partial address information to be compared is compared. The first partial address information included in the load instruction LD may be a part of the source address, and may be represented by a predetermined number of bits on the upper side of the source address. When a part of the first partial address information included in the subsequent load instruction LD overlaps with the first partial address information included in the preceding store instruction ST, the determination unit 114 is based on the hit information HIT and the way information WAYID. Determine continuation or abort of load instruction.”, page 3, paragraph 5) in order “to suppress a decrease in access efficiency” (page 4, paragraph 5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Mannava with Yuki such that the compare is a fast compare in order “to suppress a decrease in access efficiency” (id.).
In regards to claim 9, Mannava further teaches that the comparing is based on an address of the evict buffer entry (“If the ‘no’ path is followed from step 650, it may be determined whether the CMO specifies a memory address for which a pending write is present in a write buffer of the requester element. In that condition, it will be necessary to flush the pending write from the buffer in order to send the write request downstream, and again the process can proceed to step 665 where the combined condition is determined to be present.”, Col. 22, lines 14-17). Yuki further teaches that the comparing is based on a partial address (“The first partial address information to be compared is compared. The first partial address information included in the load instruction LD may be a part of the source address, and may be represented by a predetermined number of bits on the upper side of the source address. When a part of the first partial address information included in the subsequent load instruction LD overlaps with the first partial address information included in the preceding store instruction ST, the determination unit 114 is based on the hit information HIT and the way information WAYID.”, page 3, paragraph 5).
In regards to claim 10, Yuki further teaches that the partial address comprises a cache set index (“An address for identifying a data group (for example, 256 bytes) stored in the main storage device 300 is represented by an upper bit group excluding the lower 8 bits among the addresses included in the store instruction ST or the load instruction LD. For example, the lower 6 bits of the upper bit group are used for identifying 64 storage areas storing addresses in the tag area TAG, and the bits other than the lower 6 bits of the upper bit group are used in the tag area TAG. Stored in one of the storage areas. In the hit information HIT, the upper bit group of the address included in the store instruction ST or the load instruction LD matches the upper bit group of the address of the main storage device 300 in which the data stored in the cache memory unit 110 is stored.”, page 3, paragraph 3).
Claims 17-23 are rejected under 35 U.S.C. 103 as being unpatentable over Mannava et al. (US 10,970,225) in view of Carpenter et al. (US 2009/0031085).
In regards to claim 17, Mannava teaches claim 1. Mannava fails to teach that the shared local cache is coupled to a grouping of two or more processor cores of the plurality of processor cores. Carpenter teaches that the shared local cache is coupled to a grouping of two or more processor cores of the plurality of processor cores (“A ‘processing element’ is one logical attachment point to the bus, often having 200 to 500 wires, and typically consists of one shared Level2 cache 108 to which one or more processors are attached.”, paragraph 0004; See also figure 1) which “reduces maximum latency” (paragraph 0035). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Mannava with Carpenter such that the shared local cache is coupled to a grouping of two or more processor cores of the plurality of processor cores which “reduces maximum latency” (id.).
In regards to claim 18, Carpenter further teaches that the shared local cache is shared among the two or more processor cores (“A ‘processing element’ is one logical attachment point to the bus, often having 200 to 500 wires, and typically consists of one shared Level2 cache 108 to which one or more processors are attached.”, paragraph 0004).
In regards to claim 19, Carpenter further teaches that the grouping of two or more processor cores and the shared local cache operates using local coherency (“If the request is a system request (`yes` output of step 310), the bus controller resolves the coherency locally (step 312). Resolving the coherency locally may include snooping all of the devices on the node, determining if any of the snoopers have a modified copy of the data, generating a castout, and ensuring the castout reaches its destination.”, paragraph 0041; “If the data is not remotely owned and the request does not contain a remote destination (`no` output of step 324), the process skips to step 312.”, paragraph 0043).
In regards to claim 20, Carpenter further teaches that the local coherency is distinct from a global coherency (“If the data is remotely owned or the request contains a remote destination (`yes` output of step 324), the multi-node bridge forwards the request to the system side (step 326). Forwarding the request to the system side comprises broadcasting the request in a global manner to all nodes.”, paragraph 0044).
In regards to claim 21, Mannava further teaches performing a cache maintenance operation in the grouping of two or more processor cores and the shared local cache (“In this first example, it is assumed that the master device is executing software, and at some point executes an instruction to perform a CMO within its local cache.”, Col. 16, lines 60-62).
In regards to claim 22, Carpenter further teaches that the cache maintenance operation generates cache coherency transactions between the global coherency and the local coherency (“If the data is remotely owned or the request contains a remote destination (`yes` output of step 324), the multi-node bridge forwards the request to the system side (step 326). Forwarding the request to the system side comprises broadcasting the request in a global manner to all nodes. This system request may be processed by each node in a manner similar to the process of the given local node in this example, such that each of the nodes receives the request as a system request in step 304.”, paragraph 0044).
In regards to claim 23, Carpenter further teaches performing a global snoop operation on the shared local cache (“If the request is a system request (`yes` output of step 310), the bus controller resolves the coherency locally (step 312). Resolving the coherency locally may include snooping all of the devices on the node, determining if any of the snoopers have a modified copy of the data, generating a castout, and ensuring the castout reaches its destination.”, paragraph 0041).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gal (US 5,367,660) teaches checking an external buffer for writes to the same line. Holst (US 5,940,334) teaches handling aliases in a write eviction buffer. Krick (US 2002/0169935) teaches an eviction queue and a write queue. Col (US 7,065,632) teaches identifying store hits in a store buffer. Damodaran (US 2012/0198163) teaches comparing DMA addresses with a victim buffer. Moyer (US 2014/0143471) teaches gathering requests in a store buffer. Grandou (US 9,081,685) teaches using an eviction buffer for cache maintenance operations. Bhoria (US 2020/0371912) teaches resolving same addresses in a write-miss buffer. Walker (US 2022/0027270) teaches storing a duplicate copy in a write buffer. Bigelow et al. ("An Evaluation of Snoop-Based Cache Coherence Protocols") teaches checking a write-back buffer for an address match.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 20 October 2025