Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
1. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 6 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claims claimed “gate closed input” and “gate control signal”. It is uncleared and not understood which the description does not appear to offer any clarification. An appropriated correction is required.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-6, 8-12, 14-15, 17-19 and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by George et al. (US Patent No. 11,886,365)
As per claims 1 and 14, George discloses an apparatus, comprising:
a buffer in direct memory access (DMA) (fig.3, DMA engine 330) communication with a network interface to receive data packets comprising data payload portions containing data in a stream of time-synchronous media (col.21, line 57-col.22, line 3, managing performed by the DMA control circuit includes controlling the timing of data transfers over the various DMA channels, and may take various forms.)
a buffer (fig.3, RX Channel Data Buffers 214) to temporarily store a plurality of time-synchronous media records extracted from the data payload portions (col.13, lines 11-12, transfer ID and length fields may be extracted and temporarily stored), wherein respective ones of the plurality of time-synchronous media records is associated with a respective media channel (fig.3, RX Channel buffer manager 370, col.7, lines12-24, control circuit 234 is configured to control the timing of DMA transfers)
a data router circuit (fig.3, channel buffer manager 370) to read one of the plurality of time-synchronous media records from the buffer route that time-synchronous media record to a media interface (fig.3, memory write interface 306), and
a buffer monitor circuit (fig.3, DMA control circuit 130) to monitor a ratio of stored records and read records and to trigger a processor interrupt in the event of a buffer underflow or buffer overflow (col.5, lines 19-23, arbitration circuits that are configured to select the most critical requests for immediate servicing).
As per claims 8 and 18, George discloses a method, comprising:
receiving a first time-synchronous media record containing data in a stream of time-synchronous media (col.21, line 57-col.22, line 3, managing performed by the DMA control circuit includes controlling the timing of data transfers over the various DMA channels, and may take various forms.)
, storing the first time-synchronous media record in a buffer with a media channel identifier and associated with a timestamp col.13, lines 11-12, transfer ID and length fields may be extracted and temporarily stored),
monitoring the buffer with a buffer monitor circuit to trigger a processor interrupt in the event of a buffer underflow or buffer overflow (col.5, lines 19-23, arbitration circuits that are configured to select the most critical requests for immediate servicing),
determining the timestamp to be within an acceptable timestamp window and routing the first time-synchronous media record from the buffer to a media interface using a data router circuit, wherein the routing is based at least in part on the media channel identifier (col.2, lines 22-46, configured to capture and provide timestamp information regarding the progress of a transfer of a block of data over a particular channel, e.g., a value indicative of a time).
As per claim 2, George discloses the apparatus of claim 1, comprising:
a timestamp matching circuit (fig.3, timestamp generation 334), comprising:
a timestamp window (fig.1, timestamp information 134) representing a minimum timestamp value and a maximum timestamp value, a timestamp register to record a time value corresponding to a most recent frame synchronization signal (col.2, lines 22-46, configured to capture and provide timestamp information regarding the progress of a transfer of a block of data over a particular channel, e.g., a value indicative of a time), and
a matching circuit (fig.1, processing circuit 110) to assert a match signal when the time value corresponding to the most recent frame synchronization signal is within the timestamp window (col.4, lines 52-67, timestamp information 134 that is indicative of the timing of a particular transfer within the system).
As per claims 3 and 9, George discloses the apparatus of claim 2, the timestamp matching circuit comprising:
a first counter to increment on each operation of the matching circuit, and a latched counter to increment on each assertion of the match signal. (col.4, lines 52-67, timestamp information 134 that is indicative of the timing of a particular transfer within the system).
As per claims 4 and 10, George disclsoes the timestamp matching circuit comprising: a reset circuit to reset the first counter and the latched counter, and to set a trigger to enable the first counter on a next assertion of the match signal (col.8, lines 24-31, when the level of buffer 214 reaches the transfer threshold, control circuit 234 triggers, and begins performing DMAs to corresponding receive sample buffer 204 based on the descriptors that have been set up.)
As per claims 5 and 11, George discloses the data router circuit further comprising:
a first DMA input associated with a first media channel to receive a first time-synchronous media record from the buffer, a second DMA input associated with a second media channel to receive a second time-synchronous media record from the buffer (col.21, lines 57-67, managing 820 include determining that two or more DMA channels are in a prioritized class based on a comparison of current data levels to threshold levels of channel data buffers.)
an unpacker circuit (fig.8, managing 820) for receiving a third time-synchronous media record from the buffer, the unpacker circuit comprising: a first unpacker output to output a first subset of the third time-synchronous record, and a second unpacker output to output a second subset of the third time-synchronous record, a first input selector to select either the first DMA input or the first unpacker output, and a second input selector to select either the second DMA input or the second unpacker output (col.21, lines 57-67, managing 820 include determining that two or more DMA channels are in a prioritized class based on a comparison of current data levels to threshold levels of channel data buffers.)
As per claims 6 and 12, George discloses the apparatus of claim 5, the data router circuit comprising:
a gate closed input, a first gate selector to select either the output of the first input selector or the gate closed input based on a first gate control signal (col.21, lines 57-67, managing 820 include determining that two or more DMA channels are in a prioritized class based on a comparison of current data levels to threshold levels of channel data buffers.), and
a second gate selector to select either the output of the second input selector or the gate closed input based on a second gate control signal. (col.21, lines 57-67, managing 820 include determining that two or more DMA channels are in a prioritized class based on a comparison of current data levels to threshold levels of channel data buffers.)
As per claim 15, the apparatus of claim 14, comprising:
a channel selector to route a data record from the media interface to one of a plurality of media channel registers, each media channel register in DMA communication with the buffer (col.21, lines 57-67, managing 820 include determining that two or more DMA channels are in a prioritized class based on a comparison of current data levels to threshold levels of channel data buffers.)
As per claim 17, George discloses the apparatus of claim 15, comprising: a packer circuit in communication with the channel selector to combine at least a portion of each of two data records received from the media interface and to store the combination in one of the plurality of media channel registers (col.21, lines 57-67, managing 820 include determining that two or more DMA channels are in a prioritized class based on a comparison of current data levels to threshold levels of channel data buffers.)
As per claim 19, George discloses the method of claim 18, comprising:
selecting a channel to route a time-synchronous media record from the media interface to one of a plurality of media channel registers, each media channel register in DMA communication with the buffer(col.21, lines 57-67, managing 820 include determining that two or more DMA channels are in a prioritized class based on a comparison of current data levels to threshold levels of channel data buffers.)
As per claim 21, George discloses the method of claim 19, comprising: packing at least a portion of each of two data records received from the media device and storing the combination in one of the plurality of media channel registers (col.21, lines 57-67, managing 820 include determining that two or more DMA channels are in a prioritized class based on a comparison of current data levels to threshold levels of channel data buffers.)
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 7, 13, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over George et al. (US Patent No. 11,886,365) in view of Koramutla et al. (WO 2024/076413)
As per claims 7 and 13, George discloses all the limitations as the above but does not explicitly discloses the data router circuit (fig.3, traffic shaping 314) comprising: a first padding mask circuit to controllably mask zero or more bits of the output of the first gate selector, a second padding mask circuit to controllably mask zero or more bits of the output of the second gate selector, and a routing selector to route to an output register one of: an output of the first padding mask circuit, an output of the second padding mask, and a null value. However, Koramutla discloses this. (paragraph 55, figure 3, traffic shaping 314 components in a computing system that could be included in a vehicle and configured to manage different types of data streams in, the traffic shaping by either padding or dropping packets is common general knowledge in packet-based networks)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Koramutla with the teaching of George so as to prevent network congestion so as to make system more efficient, thus enhance the system performance.
As per claim 16, Koramutla discloses the apparatus of claim 15, comprising: a plurality of padding mask circuits each padding mask circuit to controllably mask zero or more bits of a particular data record from the media interface before storing the padded data record in associated with one of the plurality of media channel registers (paragraph 55, figure 3, traffic shaping 314 components in a computing system that could be included in a vehicle and configured to manage different types of data streams in, the traffic shaping by either padding or dropping packets is common general knowledge in packet-based networks).
As per claim 20, Koramutla discloses the method of claim 19, comprising: controllably masking zero more bits of the data record. Koramutla discloses this. (paragraph 55, figure 3, traffic shaping 314 components in a computing system that could be included in a vehicle and configured to manage different types of data streams in, the traffic shaping by either padding or dropping packets is common general knowledge in packet-based networks)
6. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Rentschler [Pub. No. US 20220013149] discloses The hardware circuitry is configured to provide a word select signal to the word select line and a serial clock signal to the serial clock line.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184