Prosecution Insights
Last updated: April 19, 2026
Application No. 18/937,415

Data Storage Device That Detects and Releases Bottlenecks in Hardware

Non-Final OA §102
Filed
Nov 05, 2024
Examiner
ROSSITER, SEAN D
Art Unit
2133
Tech Center
2100 — Computer Architecture & Software
Assignee
Sandisk Technologies Inc.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
591 granted / 665 resolved
+33.9% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
7 currently pending
Career history
672
Total Applications
across all art units

Statute-Specific Performance

§101
2.9%
-37.1% vs TC avg
§103
41.3%
+1.3% vs TC avg
§102
34.3%
-5.7% vs TC avg
§112
16.8%
-23.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 665 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/5/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 & 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shiga et al. PG Pub US 2005/018809 A1 [hereinafter Shiga]. 1. A data storage device, comprising: a first hardware module; a second hardware module coupled to the first hardware module; a third hardware module coupled to the first hardware module (there is provided a system including: a first device; a second device; a plurality of paths which connect the first device and the second device; and a third device which is connected to the first device [0015]); and a controller coupled to the first hardware module, the second hardware module, and the third hardware module (storage management device 2 [0057]), wherein the controller is configured to: receive a command (The host sends commands and data to the storage device [0006]), wherein contents of the command are scheduled to be transferred to the second hardware module from the first hardware module (wherein the first device transfers data to the second device [0015]); detect that the second hardware module has a bottleneck occurring (detects congestion of the plurality of paths and notifies the first device of the congestion, and the first device changes the predetermined ratio among paths on the basis of the notification to transfer the data to the second device using the plurality of paths [0015]); adjust an operating parameter of the second hardware module in response to the bottleneck (the first device changes the predetermined ratio among paths on the basis of the notification to transfer the data to the second device using the plurality of paths [0015]); and transfer the command from the first hardware module to the second hardware module (the first device transfers the data to the second device [0017]). 4. The data storage device of claim 1, wherein the second hardware module is either: a data path central processing unit (CPU) (CPU 204 in Storage management device 2); a low level flash sequence (LLFS) CPU; or a flash unit of a memory device of the data storage device. Allowable Subject Matter Claims 2, 3, & 5-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Although the prior art discloses each of the claimed limitations, individually, the Examiner cannot determine a reasonable motivation to combine them in the manner claimed, either in the prior art or existing case law. Notes The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Rubi PG Pub US 2024/0053890 A1 discloses a controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists either in an input queue corresponding to a hardware module of a plurality of hardware modules or in the hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue or in the hardware module. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN D ROSSITER whose telephone number is (571)270-3788. The examiner can normally be reached M-F 8AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEAN D ROSSITER/Primary Examiner, Art Unit 2133
Read full office action

Prosecution Timeline

Nov 05, 2024
Application Filed
Jan 28, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.8%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 665 resolved cases by this examiner. Grant probability derived from career allow rate.

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