Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 8/4/2026 in response to the Office action dated 5/22/2026. Claims 1, 8, and 15 have been amended. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-11, and 15-17 are rejected under 35 U.S.C 103 as being unpatentable over Bhardwaj (US 20220019370 A1) in view of Bennett et al. (US 20210334201 A1), hereinafter Bennett, and further in view of Nagahara (US 20220308789 A1) and Rajasekaran et al. (US 20140201442 A1), hereinafter Rajasekaran.
Regarding claim 1, Bhardwaj teaches a system comprising: a memory device (Paragraph 21; Fig. 1, non-volatile memory device 130 of memory sub-system 110); and
a processing device, operatively coupled with the memory device (Paragraph 32; Fig. 1, memory sub-system controller 115 which controls operations of memory sub-system 110 includes processor 117), to perform operations comprising:
receiving data from a host system (Paragraph 51; Figs 1 and 3, step 305, receiving write data from host system 120);
in response to receiving the data, initiating a write operation to write the data to a set of cache blocks of the memory device, the set of cache blocks comprising a first cache block and a second cache block (Paragraphs 51, 56; Figs. 2 and 3, steps 305, 320, in response to receiving write data, performing a write operation to store the data at non-zoned memory region 208 comprising blocks [including a first and second cache block]);
determining whether the first cache block is fully written (Paragraphs 59-60; Fig. 3, step 325, determining that the amount of data stored in non-zoned memory has reached a threshold condition, such as the amount of data being enough to close a block),
a second cache block (Paragraph 60, data stored in non-zoned memory can occupy two full blocks of memory (including a second block)); and
in response to determining that the first cache block is fully written and that the amount of data written to the second cache block is greater than or equal to the threshold amount of data, causing the data written to the set of cache blocks to be written to the target block (Paragraphs 59-60, 63; Figs. 2 and 3, steps 325, 330, upon determining that the amount of data reaches an aforementioned threshold condition, such as the amount of data filling two full blocks of non-zoned memory (first block being fully written and second block being fully written [equal to a threshold amount of data]), migrating data from the non-zoned memory blocks 208 [including cache blocks] to zoned memory blocks 206 [including a target block]).
Bhardwaj does not explicitly teach determining whether an amount of data written to the cache is greater than or equal to a threshold amount of data defined by a threshold number of wordlines of a target block of the memory device, wherein the data written to the set of cache blocks is migrated to the target block one cache block at a time without using double buffering, and wherein, after the data written to the first cache block is migrated to the target block, the first cache block is erased and the second cache block continues to receive additional data from the host system.
However, Bennett teaches determining whether an amount of data written to the cache is greater than or equal to a threshold amount of data, wherein the threshold amount of data is defined by a threshold number of wordlines of a target block of the memory device (Paragraphs 45, 60-62; Figs. 1 and 4A, determining whether unwritten data stored in volatile memory 112 meets a minimum write size requirement [threshold amount of data] in order to be written to a storage unit 110, wherein the minimum write size corresponds to one (or any other selected number of) wordline(s) in each erase [target] block 404 of the storage unit 110).
The Examiner notes that Bhardwaj teaches the threshold amount of data corresponding to cache blocks while Bennett teaches the threshold amount of data being defined by a number of wordlines of a target block.
Bhardwaj and Bennett are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Bhardwaj to further include the threshold amount of data being defined by a threshold number of wordlines of a target block according to the teachings of Bennett. The motivation for doing so would have been to improve overall write performance and programming efficiency (Bennett, Paragraphs 62, 68).
Bhardwaj in view of Bennett does not explicitly teach wherein the data written to the set of cache blocks is migrated to the target block one cache block at a time without using double buffering, and wherein, after the data written to the first cache block is migrated to the target block, the first cache block is erased and the second cache block continues to receive additional data from the host system.
However, Nagahara teaches wherein, after the data written to the first cache block is migrated to the target block, the first cache block is erased (Paragraph 121; Fig. 12, after migrating data from a block 148, physically erasing data from block 148).
Bhardwaj, Bennett, and Nagahara are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Bhardwaj in view of Bennett to further include the erasing after migration according to the teachings of Nagahara. The motivation for doing so would have been to increase the amount of free memory space (Nagahara, Paragraph 41).
Bhardwaj in view of Bennett, further in view of Nagahara does not explicitly teach wherein the data written to the set of cache blocks is migrated to the target block one cache block at a time without using double buffering, and wherein, after the data written to the first cache block is migrated to the target block, the second cache block continues to receive additional data from the host system.
However, Rajasekaran teaches wherein the data written to the set of cache blocks is migrated to the target block one cache block at a time without using double buffering (Paragraphs 10-11, 13, 24; Figs. 1 and 3, steps 340-350, flushing [migrating] data from a first cache region [block] of a secondary storage cache 104 (single cache/buffer) to primary storage 102 (including [target] blocks), wherein the flushing occurs one region [block] at a time, and data is continuously written to another cache region at the same time), and
wherein, after the data written to the first cache block is migrated to the target block, the second cache block continues to receive additional data from the host system (Paragraphs 10, 13, 22, 24; Figs. 1 and 3, steps 340-350, while a first cache region [block] is being flushed [migrated] to primary storage 102 (including [target] blocks), controller 106 [host] continues to write data to a second cache region [block]).
Bhardwaj, Bennett, Nagahara, and Rajasekaran are analogous art because they are in the same field of endeavor, that being storage buffer management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Bhardwaj in view of Bennett, further in view of Nagahara to further include the migration/erasing of a first cache block and continuous write of a second cache block according to the teachings of Rajasekaran. The motivation for doing so would have been to improve write performance by allowing uninterrupted writes to a cache during flushing/migration (Rajasekaran, Paragraphs 2, 22).
Regarding claim 2, Bhardwaj in view of Bennett, further in view of Rajasekaran teaches the system of claim 1 and migrating the data written to the set of cache blocks to the target block (Bhardwaj, Paragraph 63; Figs. 2 and 3, step 330, migrating data from the non-zoned memory blocks 208 [including cache blocks] to zoned memory blocks 206 [including a target block]).
Bhardwaj in view of Bennett, further in view of Rajasekaran does not explicitly teach wherein the operations further comprise, after migrating the data, updating a logical-to-physical (L2P) mapping table; and initiating an erase operation to erase the first cache block.
However, Nagahara teaches wherein the operations further comprise, after migrating the data, updating a logical-to-physical (L2P) mapping table (Paragraph 121; Figs. 1 and 12, after moving data from one block 148 to another, updating L2P table 31); and
initiating an erase operation to erase the first cache block (Paragraph 121; Fig. 12, after migrating data from a block 148, physically erasing data from block 148).
Bhardwaj, Bennett, Rajasekaran, and Nagahara are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Bhardwaj in view of Bennett, further in view of Rajasekaran to further include the updating and erasing after migration according to the teachings of Nagahara. The motivation for doing so would have been to increase the amount of free memory space (Nagahara, Paragraph 41).
Regarding claim 3, Bhardwaj in view of Bennett, further in view of Nagahara and Rajasekaran teaches the system of claim 1, wherein the first cache block comprises cells having a first type (Bhardwaj, Paragraphs 47, 56; Fig. 2, purposed blocks 212 of non-zoned memory region 208 [including the first cache block] are configured as single-level cells (SLC) [first type]), and
wherein the target block comprises cells having a second type different from the first type (Bhardwaj, Paragraph 47; Fig. 2, zoned namespace 206 blocks [including the target block] are configured as quad-level cells (QLC) [second type]).
Regarding claim 4, Bhardwaj in view of Bennett, further in view of Nagahara and Rajasekaran teaches the system of claim 3, wherein the cells having the first type are single-level cells (SLC) cells (Bhardwaj, Paragraphs 47, 56; Fig. 2, purposed blocks 212 of non-zoned memory region 208 [including the first cache block] are configured as single-level cells (SLC)), and
the cells having the second type are quad-level cells (QLC) cells (Bhardwaj, Paragraph 47; Fig. 2, zoned namespace 206 blocks [including the target block] are configured as quad-level cells (QLC)).
Regarding claims 8-11, these are method versions of the claimed system discussed above (claims 1-4, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, these claims are also obvious over Bhardwaj in view of Bennett, further in view of Nagahara and Rajasekaran.
Regarding claims 15-17, these are non-transitory computer-readable storage medium versions of the claimed system discussed above (claims 1-3, respectively), wherein Bhardwaj in view of Bennett, further in view of Nagahara and Rajasekaran also teaches a non-transitory computer-readable storage medium comprising instructions (Bhardwaj, Paragraph 83, machine-readable medium having instructions). The remaining claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, these claims are also obvious over Bhardwaj in view of Bennett, further in view of Nagahara and Rajasekaran.
Claims 5-7, 12-14, and 18-20 are rejected under 35 U.S.C 103 as being unpatentable over Bhardwaj in view of Bennett, further in view of Nagahara and Rajasekaran as applied to claims 1, 8, and 15, and further in view of Liu et al. (US 20220147252 A1), hereinafter Liu.
Regarding claim 5, Bhardwaj in view of Bennett, further in view of Nagahara and Rajasekaran teaches the system of claim 1, but does not explicitly teach wherein the operations further comprise: detecting an interrupt event with respect to data being written to the target block; determining whether to continue writing to the target block after the interrupt event; and in response to determining to continue writing to the target block after the interrupt event, causing the write operation to continue.
However, Liu teaches wherein the operations further comprise: detecting an interrupt event with respect to data being written to the target block (Paragraphs 46, 56, 58-59; Fig. 3, steps 332-333, in response to detecting a power-up event following a power-off [interrupt] event, selecting an open [target] block which is a block that is in the process of having data being programmed);
determining whether to continue writing to the target block after the interrupt event (Paragraphs 56, 60-64; Fig. 3, steps 334-336, determining whether to include or preclude the open block from programming [continue or discontinue write operations] after the power-off [interrupt] event); and
in response to determining to continue writing to the target block after the interrupt event, causing the write operation to continue (Paragraphs 60-64; Fig. 3, steps 334-336, in response to determining that the open [target] block’s age is less than or equal to a health threshold, refraining from precluding the open block from programming [continuing write operations]).
Bhardwaj, Bennett, Nagahara, Rajasekaran, and Liu are analogous art because they are in the same field of endeavor, that being storage block management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Bhardwaj in view of Bennett, further in view of Nagahara and Rajasekaran to further include the interrupt event and the continuation/discontinuation of writing in response according to the teachings of Liu. The motivation for doing so would have been to mitigate errors associated with open blocks after a power-off event (Liu, Paragraph 56).
Regarding claim 6, Bhardwaj in view of Bennett, further in view of Nagahara, Rajasekaran, and Liu teaches the system of claim 5, wherein the interrupt event comprises a power loss event (Liu, Paragraph 56, performing open block management after a power-off event).
Regarding claim 7, Bhardwaj in view of Bennett, further in view of Nagahara, Rajasekaran, and Liu teaches the system of claim 5, wherein determining whether to continue writing to the target block after the interrupt event comprises determining whether a length of time that the target block has remained open satisfies a threshold condition (Liu, Paragraphs 60-64; Fig. 3, steps 334-336, in response to determining that the open [target] block’s age [length of time the target block has remained open] is less than a health threshold, refraining from precluding the open block from programming [continue writing]).
Regarding claims 12-14, these are method versions of the claimed system discussed above (claims 5-7, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, these claims are also obvious over Bhardwaj in view of Bennett, further in view of Nagahara, Rajasekaran, and Liu.
Regarding claims 18-20, these are non-transitory computer-readable storage medium versions of the claimed system discussed above (claims 5-7, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, these claims are also obvious over Bhardwaj in view of Bennett, further in view of Nagahara, Rajasekaran, and Liu.
Response to Arguments
Applicant’s arguments (see pages 8-11 of the remarks) filed 8/4/2026, with respect to the rejections of claims 1-20 under 35 U.S.C 103 have been fully considered but they are not persuasive.
The Applicant argues that Bennett’s “minimum write size” fails to teach the limitation of claim 1: “threshold amount of data … defined by a threshold number of wordlines of a target block”. However, Bennett describes a process of holding migration data in temporary cache memory until a threshold amount of data corresponding to an amount of wordlines in a target block has been reached (Paragraphs 61-62; Fig. 1, aggregating data in flight in volatile memory 112 until the data size equals two or more word-lines of a plurality of [target] erase blocks). Although Bennett is also concerned with a write granularity requirement for parallel programming, the processes involved are functionally similar to the “cache-to-target migration threshold condition” as required by the invention. Thus, the Examiner maintains that Bennett teaches the aforementioned limitation of claim 1.
Furthermore, the Applicant argues that Bhardwaj does not seem to teach or suggest determining whether the first cache block is fully written and whether an amount of data written to the second cache block is greater than or equal to a threshold amount of data defined by a threshold number of wordlines of a target block.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Thus, the Examiner further notes in the rejection that Bhardwaj teaches a threshold amount of data corresponding to first and second blocks while Bennett further defines a threshold amount of data corresponding to a number of wordlines of target block(s). Additionally, Bhardwaj teaches a two-part determination of whether a first cache block is fully written (Paragraphs 59-60; Fig. 3, step 325, determining whether the amount of data in non-zoned memory units satisfies a threshold condition, such as two fully-written non-zoned [cache] memory blocks that includes a first, fully written block) and whether an amount of data written to the second cache block is greater than or equal to a threshold amount of data (Paragraphs 59-60; Fig. 3, step 325, determining whether the amount of data in non-zoned memory units satisfies a threshold condition, such as two fully-written non-zoned [cache] memory blocks that includes a second block that is fully written [equal to a threshold amount of data]). Thus, the combination of Bhardwaj in view of Bennett teaches the contested limitations.
Lastly, in response to the Applicant’s argument that the Office Action’s stated motivation to combine Bhardwaj and Bennett is insufficient to establish a proper motivation for the combination, the Examiner submits that while the advantages of Bennett are primarily drawn from Bennett's concurrent writes across multiple dies, an improvement in programming efficiency is also drawn from a particular step of the concurrent write method, which is holding migration data in a cache until a threshold amount of data corresponding to a number of wordlines in a target block is achieved (Bennett, Paragraphs 62, 68, allowing the storage system to store data in flight until a minimum write size [threshold] corresponding to one or more wordlines in each [target] block is achieved improves overall write performance and programming efficiency) (emphasis added). Thus, it would have been obvious to one having ordinary skill in the art to have combined the migration threshold corresponding to a number of wordlines in a target block of Bennett with the migration threshold corresponding to an amount of data in a second cache block of Bhardwaj.
Accordingly, the Examiner argues that the cited areas of the Bhardwaj and Bennett references teach the contested limitations, and further notes any other arguments with respect to the contested limitations of claims 1, 8, and 15 are consummate in scope with the argument above. Thus, the Examiner maintains the rejections as set forth above.
Applicant’s arguments (see page 10 of the remarks) filed 8/4/2026, with respect to the rejections of claims 1-20 under 35 U.S.C 103 (particularly the arguments in regard to the limitations “migrated … one cache block at a time without using double buffering” and “after the data written to the first cache block … receive additional data from the host system”) have been fully considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Bhardwaj, Bennett, Nagahara, and Rajasekaran.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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