Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of the Claims
Claims 14-33 set forth in the preliminary amendment submitted 11/05/2024 form the basis of the present examination.
Drawings
The drawing is objected to because they fail to label the element boxes in Figure 6. Without some indication as to the content of the boxes (or preferably symbols of the actual elements) it is not clear as to what the elements are and they are not explanatory to a reader as a quick method of determining the general background of the invention. See MPEP 608.02 and 37 CFR 1.84 (o) -- Legends --
Suitable descriptive legends may be used, or may be required by the Examiner, where necessary for understanding of the drawing, subject to approval by the Office. They should contain as few words as possible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14-17, 23-27 and 29-32 are rejected under 35 U.S.C. 103 as being unpatentable over Valdrin Qunaj et al. in the NPL- An E-band Fully-Integrated True Power Detector in 28nm CMOS (2019 IEEE Radio Frequency Integrated Circuits Symposium-Pages 191-194) in view of WINOTO et al. (Hereinafter, “Winoto”) in the US Patent Application Publication Number US 20150199543 A1 and further in view of Colbeck in the US Patent Application Publication Number US 20160233759 A1.
Regarding claim 14, Valdrin teaches a power detector (a fully-integrated low-power mm-wave CMOS power detector that is able to measure the true output power of the PA operating at E-band frequencies; I. INTRODUCTION-Column 1 Page 191 Line 21-23; The architecture of the power detector is shown in Fig. 1; B. Power Detector-Column 2 Page 191 Line 1) comprising:
a transformer [k12] configured to generate a sense current based on a load current associated with a load (Due to this coupling, a sensing current Isense is generated that is proportional to the output current; B. Power Detector-Column 2 Page 191 Line 6-8);
a first multiplier including a first input to receive the sense current, a second input to receive a signal related to a voltage of the load [ZL] (The RF voltage is measured with a simple capacitive divider. Multiplying these two signals using an on chip mixer yields the instantaneous RF power; B. Power Detector Column 2Page 191 Line 8-9 Column 1 Page 192 Line 1; Figure 1: Modified Figure 1 of Valdrin below shows a first multiplier)
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Figure 1: Modified Figure 1 of Valdrin
a biasing input (First and last stage are biased at V g=0.45V and V g=0.6V respectively to improve linearity [6]. Using capacitive neutralization the power gain, stability and the reverse isolation is improved; A. Power Amplifier Column 2 Page 191 Line 4-7; biasing is applied to both the first and last stage of the multiplier by introducing voltage Vg), and
an output to provide a result, the first multiplier configured to multiply the sense current[ i(t)] and the signal [v(t)] to produce the result [Pout (t)] (Multiplying these two signals using an on chip mixer yields the instantaneous RF power. An OTA amplifies and filters the signal resulting in the average output power and is given by
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; B. Power Detector Column 2Page 191 Line 9 Column 1 Page 192 Line 1-7);
a filter [OTA] (OTA as the filter) coupled to the output of the first multiplier (An OTA amplifies and filters the signal resulting in the average output power; Column 1 Page 192 Line 1-3) and configured to remove high frequency components from the result to produce a direct current (DC) signal (The OTA amplifies the DC signal and filters out the second harmonic, it has a bandwidth of 120MHz; Column 2 Page 192 Line 26 & Column 1 Page 193 Line 1-2).
However Valdrin fails to teach a biasing circuit coupled to the biasing input of the first multiplier and configured to provide a biasing signal that is independent of one or more of temperature variations or process variations of the first multiplier; a peak voltage detector configured to determine a peak value of the voltage; and a second multiplier including a first input coupled to the filter, a second input coupled to the peak voltage detector, and an output, the second multiplier configured to perform a linear multiplication of the output of the filter with the peak value to determine a value indicative of power delivered to the load.
Winoto teaches a circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance (Paragraph [0007] Line 1-10),
wherein a biasing circuit [100] (Referring now to FIG. 3, a bias circuit 100 for generating a bias voltage V.sub.B=V.sub.T+I.sub.ref*R.sub.bias is shown. The bias circuit 100 includes a current source I.sub.ref that is connected to one end of a bias resistance R.sub.bias. Another end of the resistance R.sub.bias is connected to a first terminal and a control terminal of a transistor M5. A second terminal of the transistor M5 is connected to a reference potential such as ground; Paragraph [0027] Line 1-7) coupled to the biasing input of the first multiplier [200] and configured to provide a biasing signal [V.sub.B] (In FIG. 4, the multiplier circuit 200 includes a mixer 206, such as a Gilbert cell, with transistors M1, M2, M3, and M4. The sampled voltage V.sub.PA is connected to first terminals of capacitances C.sub.1 and C.sub.2. Second terminals of the capacitances C.sub.1 and C.sub.2 are connected to control terminals of transistors M1, M2, M3, and M4 and to first terminals of resistances R.sub.1 and R.sub.2. Second terminals of the resistances R.sub.1 and R.sub.2 provide a bias voltage V.sub.B to the bias circuit 100; Paragraph [0029] Line 3-10) that is independent of one or more of temperature variations or process variations of the first multiplier (In other features, the mixer includes a Gilbert cell mixer. The bias circuit is configured to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature; Paragraph [0008] Line 1-4). The purpose of doing so is to provide a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature, to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin by including a biasing circuit as disclosed by Winoto, because Winoto teaches to include a biasing circuit coupled to the biasing input of the first multiplier and configured to provide a biasing signal provides a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature (Paragraph [0010]), generates the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature (Paragraph [0008]).
The combination of Valdrin and Winoto fails to teach a peak voltage detector configured to determine a peak value of the voltage; and a second multiplier including a first input coupled to the filter, a second input coupled to the peak voltage detector, and an output, the second multiplier configured to perform a linear multiplication of the output of the filter with the peak value to determine a value indicative of power delivered to the load.
Colbeck teaches a controller for use in a power factor correction converter includes a power factor enhancer that includes a zero-crossing detector coupled to receive an ac line input voltage signal and is coupled to output a zero-crossing signal. A peak detector is coupled to receive the ac line input voltage signal and the zero-crossing signal and is coupled to output a peak signal (Abstract),
wherein a peak voltage detector [212] in Figure 2B configured to determine a peak value of the voltage [214] (In FIG. 2B the PF Enhancer 210 receives the rectified/AC line cycles signals 206. Input signal 206 is coupled to zero-crossing detector 211 as well as to peak detector 212. The input line signal 206 is used by zero-crossing detector 211 to detect zero-crossing of line cycles where the zero-crossing signal 213 would be used by peak detector 212 to generate the peak value signals 214; Paragraph [0038] Line 1-7); and
a second multiplier [223] including a first input coupled to the filter [105] in Figure 1 (FIG. 1 is a functional block diagram illustrating an example PFC converter 100, in accordance with an embodiment of the invention. The illustrated example PFC converter 100 is an off-line PFC Boost switching power converter that receives AC sinusoidal input voltage V.sub.AC 102 with the line period TL and draws an input current I.sub.AC 104 from the line. PFC converter 100 includes an input EMI filter block 105; Paragraph [0025] Line 1-7; Input capacitor 110 is coupled across bridge rectifier 106 to bypass and filter out the high frequency current from switching device 140; Paragraph [0026] Line 1-3; The pre-distortion function 221 is such that when multiplied through multiplier 223 to the current signals 222 (that is sensed current 284, scaled through block 260), would result in the reshaped current waveform 224 which compensates in the opposite direction of original distortion; Paragraph [0040] Line 7-12),
a second input coupled to the peak voltage detector, and an output, the second multiplier configured to perform a linear multiplication of the output of the filter with the peak value to determine a value indicative of power delivered to the load (FIG. 2C is a functional block diagram illustrating another example implementation of a PF enhancer 210C where the rectified or AC line signal 206 (in one example the scaled rectified/AC sensed input voltage) is processed in Zero-Crossing detector 211 and by peak detector 212 as described in FIGS. 2A & 2B). By receiving the zero-crossing signal 213 the Peak Detect block 212 generates Vpk signal 214 and the peak modulator block 215 generates the peak modulator function 217 that, in comparison to implementation option in FIG. 2B, are first multiplied through multiplier 316 and the result 218 is then exposed to the line feed forward function 219 to generate the pre-distortion signal 221 at each half line cycle at output 221 of the PF Enhancer 210C. The pre-distortion signal 221 at each half line cycle is then imposed on the scaled sensed current signal 222 that is generated by the scaled sensed current block 260 upon receiving the sensed current 284 (that in one example could be through a sense FET or a sense resistor). The pre-distorted current signal 224 could be utilized by the on-time controller 250 to control switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition. If the PF Enhancer feature is not enabled through the enable signal “En 225” (eg; at low line and/or high load operating condition that PF naturally is high) then signal 224 received by the on-time ramp block 250 is simply the peak detect signal 214 imposed (modulated) by the line feed forward function 219 and multiplied to the scaled/sensed current signal 222. The switching control unit (block) 270 that is part of a PFC controller IC, in one example, may include multiple required blocks and receive some control signals 276 to generate switching signal 279 that through driver 282 turns PFC power switch 285 on and off to control transfer of energy to the power converter output; Paragraph [0041] Line 1-33). The purpose of doing so is to control switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition and to control transfer of energy to the power converter output, to enhance the power factor of line current at a predefined load and input voltage.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin and Winoto by including a peak voltage detector and a second multiplier as disclosed by Colbeck, because Colbeck teaches to include a peak voltage detector to determine a peak value of the voltage and a second multiplier controls switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition and to control transfer of energy to the power converter output (Paragraph [0041]), enhances the power factor of line current at a predefined load and input voltage (Paragraph [0022]).
Regarding claim 15, the combination of Valdrin and Winoto fails to teach a power detector, wherein the signal related to the voltage of the load comprises a sign of the voltage of the load.
Colbeck teaches a controller for use in a power factor correction converter includes a power factor enhancer that includes a zero-crossing detector coupled to receive an ac line input voltage signal and is coupled to output a zero-crossing signal. A peak detector is coupled to receive the ac line input voltage signal and the zero-crossing signal and is coupled to output a peak signal (Abstract),
wherein the signal related to the voltage of the load comprises a sign of the voltage of the load (In general, if the input ac current and voltage waveforms are sinusoidal and perfectly in phase, the power factor of the power supply is 1 (or 100%). In other words, a power factor corrected input will present a load to the ac source that is equivalent to coupling a fixed resistance across the ac source. As harmonic distortion and/or phase displacement of the input current relative to the ac source voltage increases, the power factor decreases below 1. Power factor requirements typically require power factors greater than 0.9 and may have requirements for the harmonic content of the input current waveform; Paragraph [0020] Line 13-23; therefore, the signal related to the voltage of the load comprises a sign of the voltage of the load if it is sinusoidal or not). The purpose of doing so is to decrease losses in the ac mains distribution system, to provide for the power factor correction of the input current waveform (Paragraph [0020]).
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Valdrin and Winoto in view of Colbeck, because Colbeck teaches to include a sign of the voltage of the load decreases losses in the ac mains distribution system, provides for the power factor correction of the input current waveform (Paragraph [0020]).
.
Regarding claim 16, Valdrin teaches a power detector,
wherein the signal related to the voltage of the load comprises a cosine of a phase difference between the load current and the voltage of the load (Multiplying these two signals using an on chip mixer yields the instantaneous RF power. An OTA amplifies and filters the signal resulting in the average output power and is given by
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where φ represents the relative phase difference between the voltage and current signal.
; B. Power Detector Column 2Page 191 Line 9 Column 1 Page 192 Line 1-9; Therefore, the signal Pavg related to the voltage of the load comprises a cosine of a phase difference between the load current [Im] and the voltage of the load [Vm]).
Regarding claim 17, the combination of Valdrin and Colbeck fails to teach a power detector, wherein the biasing circuit comprises one of a constant current source or voltage source of a bandgap.
Winoto teaches a circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance (Paragraph [0007] Line 1-10),
wherein the biasing circuit comprises one of a constant current source or voltage source of a bandgap (Referring now to FIG. 3, a bias circuit 100 for generating a bias voltage V.sub.B=V.sub.T+I.sub.ref*R.sub.bias is shown. The bias circuit 100 includes a current source I.sub.ref that is connected to one end of a bias resistance R.sub.bias. Another end of the resistance R.sub.bias is connected to a first terminal and a control terminal of a transistor M5. A second terminal of the transistor M5 is connected to a reference potential such as ground; Paragraph [0027] Line 1-7; The bias circuit includes a current source configured to generate the constant reference current, a bias resistance having the bias resistance and including one end in communication with the first current source, and a first transistor including a first terminal and a control terminal in communication with one end of the bias resistance. The bias signal is generated at a node between the bias resistance and the current source.; Paragraph [0008] Line 2-11). The purpose of doing so is to provide a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature, to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin and Colbeck by including a constant current source or voltage source of a bandgap as a biasing circuit as disclosed by Winoto, because Winoto teaches to include a constant current source or voltage source of a bandgap provides a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature (Paragraph [0010]), generates the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature (Paragraph [0008]).
Regarding claim 23, the combination of Valdrin and Colbeck fails to teach a power detector, wherein the first multiplier comprises a passive switching mixer comprising: a first transistor including a first drain coupled to a first terminal of the transformer, a first gate coupled to the biasing circuit, and a first source; a second transistor including a second drain coupled to a second terminal of the transformer, a second gate coupled to the biasing circuit, and a second source; a trans-impedance amplifier including a first input coupled to the first source, a second input coupled to the second source, and an output configured to provide a voltage signal to the filter.
Winoto teaches a circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance (Paragraph [0007] Line 1-10),
wherein the first multiplier [200] in Figure 4 comprises a passive switching mixer [M1, M2, M3, M4] comprising:
a first transistor [M1/M2] including a first drain coupled to a first terminal of the transformer, a first gate coupled to the biasing circuit [100], and a first source; a second transistor [M3/M4] including a second drain coupled to a second terminal of the transformer, a second gate coupled to the biasing circuit, and a second source; a trans-impedance amplifier [22] including a first input [V+] coupled to the first source, a second input [V-] coupled to the second source, and an output configured to provide a voltage signal to the filter (Referring now to FIGS. 4 and 5, an example of the multiplier circuit 200 according to the present disclosure is shown. In FIG. 4, the multiplier circuit 200 includes a mixer 206, such as a Gilbert cell, with transistors M1, M2, M3, and M4. The sampled voltage V.sub.PA is connected to first terminals of capacitances C.sub.1 and C.sub.2. Second terminals of the capacitances C.sub.1 and C.sub.2 are connected to control terminals of transistors M1, M2, M3, and M4 and to first terminals of resistances R.sub.1 and R.sub.2. Second terminals of the resistances R.sub.1 and R.sub.2 provide a bias voltage V.sub.B to the bias circuit 100. First terminals of first and second transistors M1 and M2 and third and fourth transistors M3 and M4 are connected to I.sub.PA. A second terminal of transistor M3 is connected to a second terminal of transistor M1. A second terminal of transistor M2 is connected to a second terminal of transistor M4; Paragraph [0029] Line 1-15; Figure 4: Modified Figure 4 of Winoto below shows multiplier). The purpose of doing so is to provide a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature, to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature.
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Figure 4: Modified Figure 4 of Winoto
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin and Colbeck by including a constant current source or voltage source of a bandgap as a biasing circuit as disclosed by Winoto, because Winoto teaches to include a first transistor including a first drain coupled to a first terminal of the transformer, a first gate coupled to the biasing circuit, and a first source; a second transistor provides a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature (Paragraph [0010]), generates the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature (Paragraph [0008]).
Regarding claim 24, Valdrin teaches a method for providing a measurement of electric power of a load (a fully-integrated low-power mm-wave CMOS power detector that is able to measure the true output power of the PA operating at E-band frequencies; I. INTRODUCTION-Column 1 Page 191 Line 21-23; The architecture of the power detector is shown in Fig. 1; B. Power Detector-Column 2 Page 191 Line 1) comprising the steps:
generating, using a transformer [k12] a sense current related to an electrical current of a load (Due to this coupling, a sensing current Isense is generated that is proportional to the output current; B. Power Detector-Column 2 Page 191 Line 6-8);
providing a biasing signal to a first multiplier (First and last stage are biased at V g=0.45V and V g=0.6V respectively to improve linearity [6]. Using capacitive neutralization the power gain, stability and the reverse isolation is improved; A. Power Amplifier Column 2 Page 191 Line 4-7; biasing is applied to both the first and last stage of the multiplier by introducing voltage Vg; The RF voltage is measured with a simple capacitive divider. Multiplying these two signals using an on chip mixer yields the instantaneous RF power; B. Power Detector Column 2Page 191 Line 8-9 Column 1 Page 192 Line 1; Figure 1: Modified Figure 1 of Valdrin above shows a first multiplier), and
multiplying using the first multiplier the sense current, with a signal related to a voltage of the load to produce a result (The RF voltage is measured with a simple capacitive divider. Multiplying these two signals using an on chip mixer yields the instantaneous RF power; B. Power Detector Column 2Page 191 Line 8-9 Column 1 Page 192 Line 1; Figure 1: Modified Figure 1 of Valdrin above shows a first multiplier; Multiplying these two signals using an on chip mixer yields the instantaneous RF power. An OTA amplifies and filters the signal resulting in the average output power and is given by
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; B. Power Detector Column 2Page 191 Line 9 Column 1 Page 192 Line 1-7);
filtering by a filter [OTA] (OTA as the filter) (An OTA amplifies and filters the signal resulting in the average output power; Column 1 Page 192 Line 1-3) the result to produce a direct current (DC) signal (The OTA amplifies the DC signal and filters out the second harmonic, it has a bandwidth of 120MHz; Column 2 Page 192 Line 26 & Column 1 Page 193 Line 1-2).
However Valdrin fails to teach a biasing circuit providing a biasing signal to a first multiplier, the biasing signal being independent of temperature and process variations of the first multiplier; determining, using a peak detector, a peak value of the voltage of the load; multiplying, using a second multiplier, the DC signal with the peak value to produce an output indicative of power supplied to the load.
Winoto teaches a circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance (Paragraph [0007] Line 1-10),
wherein a biasing circuit [100] (Referring now to FIG. 3, a bias circuit 100 for generating a bias voltage V.sub.B=V.sub.T+I.sub.ref*R.sub.bias is shown. The bias circuit 100 includes a current source I.sub.ref that is connected to one end of a bias resistance R.sub.bias. Another end of the resistance R.sub.bias is connected to a first terminal and a control terminal of a transistor M5. A second terminal of the transistor M5 is connected to a reference potential such as ground; Paragraph [0027] Line 1-7) providing a biasing signal to a first multiplier (In FIG. 4, the multiplier circuit 200 includes a mixer 206, such as a Gilbert cell, with transistors M1, M2, M3, and M4. The sampled voltage V.sub.PA is connected to first terminals of capacitances C.sub.1 and C.sub.2. Second terminals of the capacitances C.sub.1 and C.sub.2 are connected to control terminals of transistors M1, M2, M3, and M4 and to first terminals of resistances R.sub.1 and R.sub.2. Second terminals of the resistances R.sub.1 and R.sub.2 provide a bias voltage V.sub.B to the bias circuit 100; Paragraph [0029] Line 3-10) the biasing signal being independent of temperature and process variations of the first multiplier (In other features, the mixer includes a Gilbert cell mixer. The bias circuit is configured to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature; Paragraph [0008] Line 1-4). The purpose of doing so is to provide a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature, to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin by including a biasing circuit as disclosed by Winoto, because Winoto teaches to include a biasing circuit and to provide a biasing signal provides a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature (Paragraph [0010]), generates the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature (Paragraph [0008]).
The combination of Valdrin and Winoto fails to teach determining, using a peak detector, a peak value of the voltage of the load; multiplying, using a second multiplier, the DC signal with the peak value to produce an output indicative of power supplied to the load.
Colbeck teaches a controller for use in a power factor correction converter includes a power factor enhancer that includes a zero-crossing detector coupled to receive an ac line input voltage signal and is coupled to output a zero-crossing signal. A peak detector is coupled to receive the ac line input voltage signal and the zero-crossing signal and is coupled to output a peak signal (Abstract),
determining, using a peak voltage detector [212] in Figure 2B a peak value of the voltage [214] of the load (In FIG. 2B the PF Enhancer 210 receives the rectified/AC line cycles signals 206. Input signal 206 is coupled to zero-crossing detector 211 as well as to peak detector 212. The input line signal 206 is used by zero-crossing detector 211 to detect zero-crossing of line cycles where the zero-crossing signal 213 would be used by peak detector 212 to generate the peak value signals 214; Paragraph [0038] Line 1-7); and
multiplying, using a second multiplier [223] (FIG. 1 is a functional block diagram illustrating an example PFC converter 100, in accordance with an embodiment of the invention. The illustrated example PFC converter 100 is an off-line PFC Boost switching power converter that receives AC sinusoidal input voltage V.sub.AC 102 with the line period TL and draws an input current I.sub.AC 104 from the line. PFC converter 100 includes an input EMI filter block 105; Paragraph [0025] Line 1-7; Input capacitor 110 is coupled across bridge rectifier 106 to bypass and filter out the high frequency current from switching device 140; Paragraph [0026] Line 1-3; The pre-distortion function 221 is such that when multiplied through multiplier 223 to the current signals 222 (that is sensed current 284, scaled through block 260), would result in the reshaped current waveform 224 which compensates in the opposite direction of original distortion; Paragraph [0040] Line 7-12), the DC signal with the peak value to produce an output indicative of power supplied to the load (FIG. 2C is a functional block diagram illustrating another example implementation of a PF enhancer 210C where the rectified or AC line signal 206 (in one example the scaled rectified/AC sensed input voltage) is processed in Zero-Crossing detector 211 and by peak detector 212 as described in FIGS. 2A & 2B). By receiving the zero-crossing signal 213 the Peak Detect block 212 generates Vpk signal 214 and the peak modulator block 215 generates the peak modulator function 217 that, in comparison to implementation option in FIG. 2B, are first multiplied through multiplier 316 and the result 218 is then exposed to the line feed forward function 219 to generate the pre-distortion signal 221 at each half line cycle at output 221 of the PF Enhancer 210C. The pre-distortion signal 221 at each half line cycle is then imposed on the scaled sensed current signal 222 that is generated by the scaled sensed current block 260 upon receiving the sensed current 284 (that in one example could be through a sense FET or a sense resistor). The pre-distorted current signal 224 could be utilized by the on-time controller 250 to control switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition. If the PF Enhancer feature is not enabled through the enable signal “En 225” (eg; at low line and/or high load operating condition that PF naturally is high) then signal 224 received by the on-time ramp block 250 is simply the peak detect signal 214 imposed (modulated) by the line feed forward function 219 and multiplied to the scaled/sensed current signal 222. The switching control unit (block) 270 that is part of a PFC controller IC, in one example, may include multiple required blocks and receive some control signals 276 to generate switching signal 279 that through driver 282 turns PFC power switch 285 on and off to control transfer of energy to the power converter output; Paragraph [0041] Line 1-33). The purpose of doing so is to control switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition and to control transfer of energy to the power converter output, to enhance the power factor of line current at a predefined load and input voltage.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin and Winoto by including a peak detector and a second multiplier as disclosed by Colbeck, because Colbeck teaches to determine a peak value using a peak detector and to multiply using a second multiplier controls switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition and to control transfer of energy to the power converter output (Paragraph [0041]), enhances the power factor of line current at a predefined load and input voltage (Paragraph [0022]).
Regarding claim 25, the combination of Valdrin and Winoto fails to teach a method, wherein the signal related to the voltage of the load comprises a sign of the voltage of the load.
Colbeck teaches a controller for use in a power factor correction converter includes a power factor enhancer that includes a zero-crossing detector coupled to receive an ac line input voltage signal and is coupled to output a zero-crossing signal. A peak detector is coupled to receive the ac line input voltage signal and the zero-crossing signal and is coupled to output a peak signal (Abstract),
wherein the signal related to the voltage of the load comprises a sign of the voltage of the load (In general, if the input ac current and voltage waveforms are sinusoidal and perfectly in phase, the power factor of the power supply is 1 (or 100%). In other words, a power factor corrected input will present a load to the ac source that is equivalent to coupling a fixed resistance across the ac source. As harmonic distortion and/or phase displacement of the input current relative to the ac source voltage increases, the power factor decreases below 1. Power factor requirements typically require power factors greater than 0.9 and may have requirements for the harmonic content of the input current waveform; Paragraph [0020] Line 13-23; therefore, the signal related to the voltage of the load comprises a sign of the voltage of the load if it is sinusoidal or not). The purpose of doing so is to decrease losses in the ac mains distribution system, to provide for the power factor correction of the input current waveform (Paragraph [0020]).
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Valdrin and Winoto in view of Colbeck, because Colbeck teaches to include a sign of the voltage of the load decreases losses in the ac mains distribution system, provides for the power factor correction of the input current waveform (Paragraph [0020]).
.
Regarding claim 26, Valdrin teaches a method,
wherein the signal related to the voltage of the load comprises a cosine of a phase difference between the load current and the voltage of the load (Multiplying these two signals using an on chip mixer yields the instantaneous RF power. An OTA amplifies and filters the signal resulting in the average output power and is given by
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where φ represents the relative phase difference between the voltage and current signal.
; B. Power Detector Column 2Page 191 Line 9 Column 1 Page 192 Line 1-9; Therefore, the signal Pavg related to the voltage of the load comprises a cosine of a phase difference between the load current [Im] and the voltage of the load [Vm]).
Regarding claim 27, the combination of Valdrin and Colbeck fails to teach a method, wherein the biasing circuit comprises one of a constant current source or voltage source of a bandgap.
Winoto teaches a circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance (Paragraph [0007] Line 1-10),
wherein the biasing circuit comprises one of a constant current source or voltage source of a bandgap (Referring now to FIG. 3, a bias circuit 100 for generating a bias voltage V.sub.B=V.sub.T+I.sub.ref*R.sub.bias is shown. The bias circuit 100 includes a current source I.sub.ref that is connected to one end of a bias resistance R.sub.bias. Another end of the resistance R.sub.bias is connected to a first terminal and a control terminal of a transistor M5. A second terminal of the transistor M5 is connected to a reference potential such as ground; Paragraph [0027] Line 1-7; The bias circuit includes a current source configured to generate the constant reference current, a bias resistance having the bias resistance and including one end in communication with the first current source, and a first transistor including a first terminal and a control terminal in communication with one end of the bias resistance. The bias signal is generated at a node between the bias resistance and the current source.; Paragraph [0008] Line 2-11). The purpose of doing so is to provide a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature, to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin and Colbeck by including a constant current source or voltage source of a bandgap as a biasing circuit as disclosed by Winoto, because Winoto teaches to include a constant current source or voltage source of a bandgap provides a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature (Paragraph [0010]), generates the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature (Paragraph [0008]).
Regarding claim 29, Valdrin teaches a power detector (a fully-integrated low-power mm-wave CMOS power detector that is able to measure the true output power of the PA operating at E-band frequencies; I. INTRODUCTION-Column 1 Page 191 Line 21-23; The architecture of the power detector is shown in Fig. 1; B. Power Detector-Column 2 Page 191 Line 1) comprising:
a transformer [k12] configured to generate a sense current related to an electrical current provided to a load (Due to this coupling, a sensing current Isense is generated that is proportional to the output current; B. Power Detector-Column 2 Page 191 Line 6-8);
a first multiplier (The RF voltage is measured with a simple capacitive divider. Multiplying these two signals using an on chip mixer yields the instantaneous RF power; B. Power Detector Column 2Page 191 Line 8-9 Column 1 Page 192 Line 1; Figure 1: Modified Figure 1 of Valdrin above shows a first multiplier) configured to multiply the sense current with a signal related to a voltage across the load [ZL] to produce a result (Multiplying these two signals using an on chip mixer yields the instantaneous RF power. An OTA amplifies and filters the signal resulting in the average output power and is given by
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; B. Power Detector Column 2Page 191 Line 9 Column 1 Page 192 Line 1-7);
a filter [OTA] (OTA as the filter) including an input coupled to the first multiplier to receive the result (An OTA amplifies and filters the signal resulting in the average output power; Column 1 Page 192 Line 1-3), the filter configured to remove high frequency components from the result to produce a direct current (DC) output; (The OTA amplifies the DC signal and filters out the second harmonic, it has a bandwidth of 120MHz; Column 2 Page 192 Line 26 & Column 1 Page 193 Line 1-2).
However Valdrin fails to teach a peak voltage detector configured to determine a peak value of the voltage; a second multiplier configured to perform a linear multiplication of the DC output and the peak value to produce an output value indicative of power supplied to the load; and a biasing circuit configured to provide, to the first multiplier, a biasing signal that is independent of one or more of temperature variation or process variation of the first multiplier.
Colbeck teaches a controller for use in a power factor correction converter includes a power factor enhancer that includes a zero-crossing detector coupled to receive an ac line input voltage signal and is coupled to output a zero-crossing signal. A peak detector is coupled to receive the ac line input voltage signal and the zero-crossing signal and is coupled to output a peak signal (Abstract),
wherein a peak voltage detector [212] in Figure 2B configured to determine a peak value of the voltage [214] (In FIG. 2B the PF Enhancer 210 receives the rectified/AC line cycles signals 206. Input signal 206 is coupled to zero-crossing detector 211 as well as to peak detector 212. The input line signal 206 is used by zero-crossing detector 211 to detect zero-crossing of line cycles where the zero-crossing signal 213 would be used by peak detector 212 to generate the peak value signals 214; Paragraph [0038] Line 1-7); and
a second multiplier [223] in Figure 1 (FIG. 1 is a functional block diagram illustrating an example PFC converter 100, in accordance with an embodiment of the invention. The illustrated example PFC converter 100 is an off-line PFC Boost switching power converter that receives AC sinusoidal input voltage V.sub.AC 102 with the line period TL and draws an input current I.sub.AC 104 from the line. PFC converter 100 includes an input EMI filter block 105; Paragraph [0025] Line 1-7; Input capacitor 110 is coupled across bridge rectifier 106 to bypass and filter out the high frequency current from switching device 140; Paragraph [0026] Line 1-3; The pre-distortion function 221 is such that when multiplied through multiplier 223 to the current signals 222 (that is sensed current 284, scaled through block 260), would result in the reshaped current waveform 224 which compensates in the opposite direction of original distortion; Paragraph [0040] Line 7-12) configured to perform a linear multiplication of the DC output and the peak value to produce an output value indicative of power supplied to the load (FIG. 2C is a functional block diagram illustrating another example implementation of a PF enhancer 210C where the rectified or AC line signal 206 (in one example the scaled rectified/AC sensed input voltage) is processed in Zero-Crossing detector 211 and by peak detector 212 as described in FIGS. 2A & 2B). By receiving the zero-crossing signal 213 the Peak Detect block 212 generates Vpk signal 214 and the peak modulator block 215 generates the peak modulator function 217 that, in comparison to implementation option in FIG. 2B, are first multiplied through multiplier 316 and the result 218 is then exposed to the line feed forward function 219 to generate the pre-distortion signal 221 at each half line cycle at output 221 of the PF Enhancer 210C. The pre-distortion signal 221 at each half line cycle is then imposed on the scaled sensed current signal 222 that is generated by the scaled sensed current block 260 upon receiving the sensed current 284 (that in one example could be through a sense FET or a sense resistor). The pre-distorted current signal 224 could be utilized by the on-time controller 250 to control switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition. If the PF Enhancer feature is not enabled through the enable signal “En 225” (eg; at low line and/or high load operating condition that PF naturally is high) then signal 224 received by the on-time ramp block 250 is simply the peak detect signal 214 imposed (modulated) by the line feed forward function 219 and multiplied to the scaled/sensed current signal 222. The switching control unit (block) 270 that is part of a PFC controller IC, in one example, may include multiple required blocks and receive some control signals 276 to generate switching signal 279 that through driver 282 turns PFC power switch 285 on and off to control transfer of energy to the power converter output; Paragraph [0041] Line 1-33). The purpose of doing so is to control switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition and to control transfer of energy to the power converter output, to enhance the power factor of line current at a predefined load and input voltage.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin by including a peak voltage detector and a second multiplier as disclosed by Colbeck, because Colbeck teaches to include a peak voltage detector to determine a peak value of the voltage and a second multiplier controls switching on-time and compensate for the current distortion and improving the power factor at high line and/or low load operating condition and to control transfer of energy to the power converter output (Paragraph [0041]), enhances the power factor of line current at a predefined load and input voltage (Paragraph [0022]).
The combination of Valdrin and Colbeck fails to teach a biasing circuit configured to provide, to the first multiplier, a biasing signal that is independent of one or more of temperature variation or process variation of the first multiplier.
Winoto teaches a circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance (Paragraph [0007] Line 1-10),
wherein a biasing circuit [100] (Referring now to FIG. 3, a bias circuit 100 for generating a bias voltage V.sub.B=V.sub.T+I.sub.ref*R.sub.bias is shown. The bias circuit 100 includes a current source I.sub.ref that is connected to one end of a bias resistance R.sub.bias. Another end of the resistance R.sub.bias is connected to a first terminal and a control terminal of a transistor M5. A second terminal of the transistor M5 is connected to a reference potential such as ground; Paragraph [0027] Line 1-7) configured to provide, to the first multiplier, a biasing signal [V.sub.B] (In FIG. 4, the multiplier circuit 200 includes a mixer 206, such as a Gilbert cell, with transistors M1, M2, M3, and M4. The sampled voltage V.sub.PA is connected to first terminals of capacitances C.sub.1 and C.sub.2. Second terminals of the capacitances C.sub.1 and C.sub.2 are connected to control terminals of transistors M1, M2, M3, and M4 and to first terminals of resistances R.sub.1 and R.sub.2. Second terminals of the resistances R.sub.1 and R.sub.2 provide a bias voltage V.sub.B to the bias circuit 100; Paragraph [0029] Line 3-10) that is independent of one or more of temperature variation or process variation of the first multiplier (In other features, the mixer includes a Gilbert cell mixer. The bias circuit is configured to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature; Paragraph [0008] Line 1-4). The purpose of doing so is to provide a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature, to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin and Colbeck by including a biasing circuit as disclosed by Winoto, because Winoto teaches to include a biasing circuit coupled to the biasing input of the first multiplier and configured to provide a biasing signal provides a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature (Paragraph [0010]), generates the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature (Paragraph [0008]).
Regarding claim 30, the combination of Valdrin and Winoto fails to teach a power detector, wherein the signal related to the voltage of the load comprises a sign of the voltage of the load.
Colbeck teaches a controller for use in a power factor correction converter includes a power factor enhancer that includes a zero-crossing detector coupled to receive an ac line input voltage signal and is coupled to output a zero-crossing signal. A peak detector is coupled to receive the ac line input voltage signal and the zero-crossing signal and is coupled to output a peak signal (Abstract),
wherein the signal related to the voltage of the load comprises a sign of the voltage of the load (In general, if the input ac current and voltage waveforms are sinusoidal and perfectly in phase, the power factor of the power supply is 1 (or 100%). In other words, a power factor corrected input will present a load to the ac source that is equivalent to coupling a fixed resistance across the ac source. As harmonic distortion and/or phase displacement of the input current relative to the ac source voltage increases, the power factor decreases below 1. Power factor requirements typically require power factors greater than 0.9 and may have requirements for the harmonic content of the input current waveform; Paragraph [0020] Line 13-23; therefore, the signal related to the voltage of the load comprises a sign of the voltage of the load if it is sinusoidal or not). The purpose of doing so is to decrease losses in the ac mains distribution system, to provide for the power factor correction of the input current waveform (Paragraph [0020]).
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Valdrin and Winoto in view of Colbeck, because Colbeck teaches to include a sign of the voltage of the load decreases losses in the ac mains distribution system, provides for the power factor correction of the input current waveform (Paragraph [0020]).
Regarding claim 31, Valdrin teaches a power detector,
wherein the signal related to the voltage of the load comprises a cosine of a phase difference between the load current and the voltage of the load (Multiplying these two signals using an on chip mixer yields the instantaneous RF power. An OTA amplifies and filters the signal resulting in the average output power and is given by
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where φ represents the relative phase difference between the voltage and current signal.
; B. Power Detector Column 2Page 191 Line 9 Column 1 Page 192 Line 1-9; Therefore, the signal Pavg related to the voltage of the load comprises a cosine of a phase difference between the load current [Im] and the voltage of the load [Vm]).
Regarding claim 32, the combination of Valdrin and Colbeck fails to teach a power detector, wherein the biasing circuit comprises one of a constant current source or voltage source of a bandgap.
Winoto teaches a circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance (Paragraph [0007] Line 1-10),
wherein the biasing circuit comprises one of a constant current source or voltage source of a bandgap (Referring now to FIG. 3, a bias circuit 100 for generating a bias voltage V.sub.B=V.sub.T+I.sub.ref*R.sub.bias is shown. The bias circuit 100 includes a current source I.sub.ref that is connected to one end of a bias resistance R.sub.bias. Another end of the resistance R.sub.bias is connected to a first terminal and a control terminal of a transistor M5. A second terminal of the transistor M5 is connected to a reference potential such as ground; Paragraph [0027] Line 1-7; The bias circuit includes a current source configured to generate the constant reference current, a bias resistance having the bias resistance and including one end in communication with the first current source, and a first transistor including a first terminal and a control terminal in communication with one end of the bias resistance. The bias signal is generated at a node between the bias resistance and the current source.; Paragraph [0008] Line 2-11). The purpose of doing so is to provide a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature, to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin and Colbeck by including a constant current source or voltage source of a bandgap as a biasing circuit as disclosed by Winoto, because Winoto teaches to include a constant current source or voltage source of a bandgap provides a conversion gain of the mixer (multiplier) substantially constant regardless of variations in process and temperature (Paragraph [0010]), generates the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature (Paragraph [0008]).
Claim(s) 18-22, 28 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Valdrin in the NPL- An E-band Fully-Integrated True Power Detector in 28nm CMOS (2019 IEEE Radio Frequency Integrated Circuits Symposium-Pages 191-194) in view of Winoto’543 A1 and Colbeck ‘759 A1, as applied to claim 14 above, and further in view of Dames et al. (Hereinafter, “Dames”) in the US Patent Application Publication Number US 20220091167 A1.
Regarding claim 18, the combination of Valdrin, Winoto and Colbeck fails to teach a power detector, further comprising an attenuator including an output coupled to the first multiplier, the attenuator configured to provide an attenuation signal to the first
multiplier to adapt a working range of the first multiplier.
Dames teaches an electricity meter, in particular to an electricity meter capable of measuring dc power (Paragraph [0001] Line 1-3),
further comprising an attenuator [17] (The electricity meter 12 may include an attenuation circuit 17 for passively attenuating the voltage signal 14. The attenuation circuit 17 may take the form of a voltage divider; Paragraph [0058] Line 1-3) including an output coupled to the first multiplier [53/54] in Figure 3 (Referring to FIG. 3, a modulator 22, 23 can be viewed as a pair of switches 51, 52 that route an input signal 12, 14 alternatively through a pair of multipliers 53, 54; Paragraph [0073] Line 1-3; Figure 1 shows output from the attenuator 17 goes to the modulator 22 and Figure 3 shows that the modulator comprises multiplier), the attenuator configured to provide an attenuation signal to the first multiplier to adapt a working range of the first multiplier [53] (Referring to FIG. 3, a modulator 22, 23 can be viewed as a pair of switches 51, 52 that route an input signal 12, 14 alternatively through a pair of multipliers 53, 54, one having a multiplication factor of +1 and the other having a multiplication factors of 1, to produce a modulated output 34, 35. The switches 51, 52 are synchronised with a common timing signal 55 created from a control circuit 56 derived from the timing reference 25; Paragraph [0073] Line 1-8). The purpose of doing so is to synchronously modulate current and voltage measurement signals and to output synchronously-modulated current and voltage measurement signals, to reduce electrical and magnetic interference.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin, Winoto and Colbeck in view of Dames, because Dames teaches to include an attenuator including an output coupled to the first multiplier synchronously modulates current and voltage measurement signals and outputs synchronously-modulated current and voltage measurement signals (Paragraph [0003]), reduces electrical and magnetic interference (Paragraph [0056]).
Regarding claim 19, the combination of Valdrin, Winoto and Colbeck fails to teach a power detector, wherein the attenuator is programmable.
Dames teaches an electricity meter, in particular to an electricity meter capable of measuring dc power (Paragraph [0001] Line 1-3),
wherein the attenuator is programmable [17] (The electricity meter 12 may include an attenuation circuit 17 for passively attenuating the voltage signal 14. The attenuation circuit 17 may take the form of a voltage divider; Paragraph [0058] Line 1-3; The voltage signal, which can be attenuated before analogue-to-digital conversion, can also be modulated if desired before sampling or done after sampling; Paragraph [0095] Line 4-6; therefore, the attenuator is programmable). The purpose of doing so is to reduce the zero offset to an extremely low level (e.g. less than 0.1 μV) permitting a wider dynamic range (e.g., up to 1000 to 1) of current and power measurement to be performed with a given shunt, especially useful in high current (e.g., 200 or 400 A) systems where the maximum emf across the shunt has to be limited to control power dissipation and losses.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin, Winoto and Colbeck in view of Dames, because Dames teaches to include a programmable attenuator to reduce the zero offset to an extremely low level (e.g. less than 0.1 μV) permitting a wider dynamic range (e.g., up to 1000 to 1) of current and power measurement to be performed with a given shunt, especially useful in high current (e.g., 200 or 400 A) systems where the maximum emf across the shunt has to be limited to control power dissipation and losses (Paragraph [0095]).
Regarding claim 20, the combination of Valdrin, Winoto and Colbeck fails to teach a power detector, wherein the second multiplier comprises one of a digital multiplier or an analog multiplier.
Dames teaches an electricity meter, in particular to an electricity meter capable of measuring dc power (Paragraph [0001] Line 1-3),
wherein the second multiplier comprises one of a digital multiplier or an analog multiplier (The first and second modulators may comprise first and second sets of 4-quadrant analogue multipliers, respectively; Paragraph [0010] Line 13-15). The purpose of doing so is to synchronously modulate current and voltage measurement signals and to output synchronously-modulated current and voltage measurement signals, to reduce electrical and magnetic interference.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin, Winoto and Colbeck in view of Dames, because Dames teaches to include a digital multiplier or an analog multiplier synchronously modulates current and voltage measurement signals and outputs synchronously-modulated current and voltage measurement signals (Paragraph [0003]), reduces electrical and magnetic interference (Paragraph [0056]).
Regarding claim 21, the combination of Valdrin, Winoto and Colbeck fails to teach a power detector, wherein the first multiplier comprises a hard-switching multiplier.
Dames teaches an electricity meter, in particular to an electricity meter capable of measuring dc power (Paragraph [0001] Line 1-3),
wherein the first multiplier comprises a hard-switching multiplier (The modulators 22, 23 can be implemented in several difference ways. Generally, however, analogue multipliers tend to be costly and unstable and so an implementation employing switches, such as MOSFETS and other forms of transistors, can be used; Paragraph [0074] Line 1-5). The purpose of doing so is to synchronously modulate current and voltage measurement signals and outputs synchronously-modulated current and voltage measurement signals, to reduce cost and to provide stable operation.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin, Winoto and Colbeck in view of Dames, because Dames teaches to include a hard-switching multiplier synchronously modulates current and voltage measurement signals and outputs synchronously-modulated current and voltage measurement signals (Paragraph [0003]), reduces electrical and magnetic interference (Paragraph [0056]) and reduces cost and provides stable operation (paragraph [0074]).
Regarding claim 22, the combination of Valdrin, Winoto and Colbeck fails to teach a power detector, wherein the biasing circuit and the attenuator are implemented in a single element.
Dames teaches an electricity meter, in particular to an electricity meter capable of measuring dc power (Paragraph [0001] Line 1-3),
wherein the biasing circuit and the attenuator are implemented in a single element (The electricity meter 12 may include an attenuation circuit 17 for passively attenuating the voltage signal 14. The attenuation circuit 17 may take the form of a voltage divider; Paragraph [0058] Line 1-3; Referring to FIG. 3, a modulator 22, 23 can be viewed as a pair of switches 51, 52 that route an input signal 12, 14 alternatively through a pair of multipliers 53, 54; Paragraph [0073] Line 1-3; Referring to FIG. 3, a modulator 22, 23 can be viewed as a pair of switches 51, 52 that route an input signal 12, 14 alternatively through a pair of multipliers 53, 54, one having a multiplication factor of +1 and the other having a multiplication factors of 1, to produce a modulated output 34, 35. The switches 51, 52 are synchronised with a common timing signal 55 created from a control circuit 56 derived from the timing reference 25; Paragraph [0073] Line 1-8; Dames in view of Winoto discloses the biasing circuit and the attenuator are implemented in a single element). The purpose of doing so is to synchronously modulate current and voltage measurement signals and to output synchronously-modulated current and voltage measurement signals, to reduce electrical and magnetic interference.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin, Winoto and Colbeck in view of Dames, because Dames teaches to implement the biasing circuit and the attenuator in a single element synchronously modulates current and voltage measurement signals and outputs synchronously-modulated current and voltage measurement signals (Paragraph [0003]), reduces electrical and magnetic interference (Paragraph [0056]).
Regarding claim 28, the combination of Valdrin, Winoto and Colbeck fails to teach a method, further comprising providing, by an attenuator an attenuation signal to the first
multiplier to adapt a working range of the first multiplier.
Dames teaches an electricity meter, in particular to an electricity meter capable of measuring dc power (Paragraph [0001] Line 1-3),
further comprising providing, by an attenuator [17] (The electricity meter 12 may include an attenuation circuit 17 for passively attenuating the voltage signal 14. The attenuation circuit 17 may take the form of a voltage divider; Paragraph [0058] Line 1-3) an attenuation signal to the first multiplier to adapt a working range of the first multiplier (Referring to FIG. 3, a modulator 22, 23 can be viewed as a pair of switches 51, 52 that route an input signal 12, 14 alternatively through a pair of multipliers 53, 54; Paragraph [0073] Line 1-3; Referring to FIG. 3, a modulator 22, 23 can be viewed as a pair of switches 51, 52 that route an input signal 12, 14 alternatively through a pair of multipliers 53, 54, one having a multiplication factor of +1 and the other having a multiplication factors of 1, to produce a modulated output 34, 35. The switches 51, 52 are synchronised with a common timing signal 55 created from a control circuit 56 derived from the timing reference 25; Paragraph [0073] Line 1-8). The purpose of doing so is to synchronously modulate current and voltage measurement signals and to output synchronously-modulated current and voltage measurement signals, to reduce electrical and magnetic interference.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin, Winoto and Colbeck in view of Dames, because Dames teaches to include an attenuator i synchronously modulates current and voltage measurement signals and outputs synchronously-modulated current and voltage measurement signals (Paragraph [0003]), reduces electrical and magnetic interference (Paragraph [0056]).
Regarding claim 33, the combination of Valdrin, Winoto and Colbeck fails to teach a power detector, further comprising an attenuator including an output coupled to the first multiplier, the attenuator configured to provide an attenuation signal to the first
multiplier to adapt a working range of the first multiplier.
Dames teaches an electricity meter, in particular to an electricity meter capable of measuring dc power (Paragraph [0001] Line 1-3),
further comprising an attenuator [17] (The electricity meter 12 may include an attenuation circuit 17 for passively attenuating the voltage signal 14. The attenuation circuit 17 may take the form of a voltage divider; Paragraph [0058] Line 1-3) including an output coupled to the first multiplier [53/54] in Figure 3 (Referring to FIG. 3, a modulator 22, 23 can be viewed as a pair of switches 51, 52 that route an input signal 12, 14 alternatively through a pair of multipliers 53, 54; Paragraph [0073] Line 1-3; Figure 1 shows output from the attenuator 17 goes to the modulator 22 and Figure 3 shows that the modulator comprises multiplier), the attenuator configured to provide an attenuation signal to the first multiplier to adapt a working range of the first multiplier [53] (Referring to FIG. 3, a modulator 22, 23 can be viewed as a pair of switches 51, 52 that route an input signal 12, 14 alternatively through a pair of multipliers 53, 54, one having a multiplication factor of +1 and the other having a multiplication factors of 1, to produce a modulated output 34, 35. The switches 51, 52 are synchronised with a common timing signal 55 created from a control circuit 56 derived from the timing reference 25; Paragraph [0073] Line 1-8). The purpose of doing so is to synchronously modulate current and voltage measurement signals and to output synchronously-modulated current and voltage measurement signals, to reduce electrical and magnetic interference.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the power detector of Valdrin, Winoto and Colbeck in view of Dames, because Dames teaches to include an attenuator including an output coupled to the first multiplier synchronously modulates current and voltage measurement signals and outputs synchronously-modulated current and voltage measurement signals (Paragraph [0003]), reduces electrical and magnetic interference (Paragraph [0056]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shih (US 20110140758 A1) discloses, “ANALOG MULTIPLIER- [0003] The present invention relates to an analog multiplier, and more particularly to an analog multiplier having a simple architecture. [0019] FIG. 1 is a system block diagram of the present invention. An analog current mirror comprises a bias circuit 10, a level shifter 20, a multiplying circuit 30, and a current mirror 40. The bias circuit 10 and the level shifter 20 are connected to the multiplying circuit 30. The multiplying circuit 30 is connected to the current mirror 40. The current mirror 40 mirrors the current output by the multiplying circuit 30 and outputs a current thereof. [0020] The bias circuit 10 is used for inputting a first voltage V1, and forces an output at the first voltage V1. The bias circuit 10 is also technically referred to as an unit gain buffer amplifier or an isolation amplifier. [0021] The level shifter 20 is used for inputting a second voltage V2, and shifts the second voltage V2 to a third voltage V3. The third voltage V3 is approximately equal to the second voltage V2 plus a threshold voltage Vthp (a P-channel Metal Oxide Semiconductor (PMOS) threshold voltage). [0022] The multiplying circuit 30 is used for inputting the first voltage V1 and the third voltage V3, and generating a product current Is. The product current is proportional to a product of the first voltage V1 and the third voltage V3 minus a threshold voltage Vthn (an N-channel Metal Oxide Semiconductor (NMOS) threshold voltage). [0023] The current mirror 40 has a master side and a slave side. The master side receives the output product current Is of the multiplying circuit 30, and the slave side generates a mirror current Im equal to the product current Is. The slave side eventually delivers the mirror current to a load 50-However Shih does not disclose a peak voltage detector configured to determine a peak value of the voltage; and a second multiplier including a first input coupled to the filter, a second input coupled to the peak voltage detector, and an output, the second multiplier configured to perform a linear multiplication of the output of the filter with the pcak value to determine a value indicative of power delivered to the load. a peak voltage detector configured to determine a peak value of the voltage; and a second multiplier including a first input coupled to the filter, a second input coupled to the peak voltage detector, and an output, the second multiplier configured to perform a linear multiplication of the output of the filter with the pcak value to determine a value indicative of power delivered to the load.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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