DETAILED ACTION
This action is responsive to the following: the application and information disclosure statement filed on November 5, 2024 and the information disclosure statement filed on June 10, 2025.
Claims 1-21 are pending. Claims 1, 16, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to because Figure 6 appears to be incomplete in its illustration of the transistors connected to Sub Bit-line[0], Sub Bit-line[3], Sub Bit-line[6]. As an example, the transistor on the left (connected to Sub Bit-line[0]) is missing gate connection to WR_SEL<1> and source/drain connection for Vw.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the “weight calibration module” in claims 2-5, and also the steps of “controlling a switch,” “measuring the weight voltage,” and “calibrating the weight resistance” in claims 18-21.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112 - written description requirement
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-5 and 18-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2 (and its dependents) recite and limit the “weight calibration module.” The “weight calibration module” is a term that invokes means-plus-function, supra. The originally filed disclosure does not provide adequate written description for this means-plus-function invoking term.
The “weight calibration module” is only illustrated in application Figure 12, but there are no connections or details to identify what it is. Application Specification paragraphs 165-166 explain that the “weight calibration module” as follows:
[0165] The weight calibration module 400 may measure a weight voltage by controlling a switch. The term "module" used herein may be a unit including one or a combination of two or more of hardware, software, and firmware. The term "module" may be used interchangeably with other terms, for example, "unit", "logic", "logical block", "component", or "circuit". The "module" may be a minimum unit of an integrally formed component or part thereof. The "module" may be a minimum unit for performing one or more functions or part thereof. The "module" may be implemented mechanically or electronically. For example, the "module" may include at least one of an application-specific integrated circuit (ASIC) chip, a field-programmable gate array (FPGA), and/or a programmable-logic device for performing certain operations that are well known or to be developed in the future.
[0166] The weight calibration module 400 may control the switch to be in a first state (e.g., a on state), may input the weight voltage, which is analog data, to the converter, may convert the weight voltage into digital data, and may measure the weight voltage converted into the digital data. The weight calibration module 400 may compare the measured weight voltage with a target voltage and may determine whether there is an error. For example, when the difference between the measured weight voltage and the target voltage exceeds a predetermined threshold, the weight calibration module 400 may determine that the measured weight voltage has an error. The weight calibration module 400, when determining that there is an error, may calibrate the weight resistance to the target voltage.
These paragraphs do not disclose the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. MPEP 2181(IV); MPEP 2185.
Method claims 18-21 implicate this “weight calibration module” (even though not claimed) because these method claims require “controlling a switch,” “measuring the weight voltage,” and “calibrating the weight resistance,” which are the functions the mentioned “weight calibration module” performs. For similar reasons, these claims are not supported by sufficient description of the computer and algorithm in a way that would demonstrate to one of ordinary skill in the art that the inventor possessed the invention.
Claim Rejections - 35 USC § 112 - definiteness requirement
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5 and 18-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitation “weight calibration module” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. For example, the “weight calibration module” is claimed to “measure the weight voltage” (claim 2, and as implicated in claim 18), “control the switch” (claim 3, and as implicated in claims 18 and 19), “compare the measured weight voltage” (claim 4, and as implicated in claim 20) , and “calibrate the weight resistance” (claim 5, and as implicated in claim 21). The “weight calibration module” is only illustrated in Figure 12 as a box with no further detail of it connections or components. The “switch,” which the “weight calibration module” controls, is illustrated in exemplary Figure 5A as switch 160, but there are no connections to its gate. Application Specification paragraphs 165-166 do not adequately describe the computer and algorithm.
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-18 are rejected under 35 U.S.C. 103 as being unpatentable over Myung et al (US 20220326910 A1) in view of Yen et al (US 20200356620 A1).
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Regarding Independent Claim 1, Myung teaches a multi-bit operation device comprising:
a plurality of multi-bit cells (Fig. 12: 200); and
a converter (Fig. 12: 300) configured to convert second sum data into digital data, wherein the second sum data is generated by summing pieces of first sum data output from each of the plurality of multi-bit cells, and
each of the plurality of multi-bit cells comprises:
a memory (Fig. 5: 110) configured to store a weight resistance corresponding to a multi-bit weight;
a current source (Fig. 5: 120) configured to apply current to the memory (Fig. 5: 110) such that a weight voltage (Fig. 5: Vw) is generated from the weight resistance;
a plurality of multiplexers (Fig. 5: 130) connected to one another in parallel and connected to the memory (Fig. 5: 110) in series and each configured to output a signal of one of the weight voltage and a first fixed voltage, based on a multi-bit input;
a plurality of capacitors (Fig. 5: 140) connected respectively to the plurality of multiplexers (Fig. 5: 130) and each configured to store a separate weight capacitance and generate charge data by performing an operation on the output signal and the weight capacitance;
a bit line (Fig. 5: VB) configured to output first sum data generated by summing pieces of charge data generated by each of the plurality of capacitors (Fig. 5: 140);
However, Myung fails to teach a switch of which an end is connected to the memory and an opposite end to the end is connected to the bit line.
Yen teaches a switch (Fig. 3: 314-5) capable of shorting the ends of the capacitor array together.
Yen also teaches that a switch in parallel with the capacitors and coupled to both nodes of the charge storing capacitors in the cell can be used to reset the cell (para 28). Therefore, this reset switch would be useful for addressing when the capacitors are over or undercharged in error and need to have the error corrected.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Yen to the teachings of Myung to produce a multibit memory cell with a reset switch.
Regarding Claim 6, Myung and Yen teach the limitations of claim 1. Myung further teaches the memory (Fig. 5: 110) comprises resistance elements (para 16 “The memory may include a first memory and a second memory that each store different weight resistances”) of which the number corresponds to the number of bits of the multi-bit weight and that are connected to one another in series (Fig. 6: 111a, 110) 33, and
the multi-bit cell is configured to control each of the resistance elements to be on/off and adjust the weight resistance (Fig. 6: WR_SEL).
Regarding Claim 7, Myung and Yen teach the limitations of claim 1. Myung further teaches wherein the plurality of multiplexers (fig. 5: 140) each receives an input of 1 or 0 (Fig. 5: 151), and
a multiplexer (Fig. 5: 131) that receives 1 is configured to output the weight voltage and a multiplexer that receives 0 is configured to output the first fixed voltage among the plurality of multiplexers (para 81 “The individual input 151 received by the multiplexer 131 may act as a selector signal (SEL) with respect to the multiplexer 131, to cause one of the weight voltage and the first fixed voltage to be output from the multiplexer 131.”) .
Regarding Claim 8, Myung and Yen teach the limitations of claim 1. Myung further teaches in response to the first fixed voltage being output from all the plurality of multiplexers, the multi-bit cell is configured to control the current source to be off and reduce power consumption.
Regarding Claim 9, Myung and Yen teach the limitations of claim 1. Myung further teaches the size of a second fixed voltage (Fig. 5: Vb) that is relayed to an opposite end to an end of a capacitor (Fig. 5: CAP0) to which the output signal is relayed is the same as the size of the first fixed voltage, and
a capacitor that receives the first fixed voltage among the plurality of capacitors and has the same potential at both ends of the capacitor is configured to generate 0 C charge data in response to a 0 V voltage being applied to the capacitor (para 95 “the capacitor that receives the first fixed voltage may have the same potential at both terminals thereof and thus a potential difference of 0 V. In this case, the capacitor may receive a voltage of 0 V and generate charge data of 0 C.”).
Regarding Claim 10, Myung and Yen teach the limitations of claim 9. Myung further teaches the weight resistance is set to linearly increase as the multi-bit weight increases (para 83 “The weight resistance may be set to linearly increase as the corresponding multi-bit weight increases.”), and the size of the second fixed voltage is set such that a differential value from the weight voltage is proportional to the multi-bit weight (para 91 “The magnitude of the second fixed voltage may be set such that the difference value with the weight voltage is proportional to the multi-bit weight.”).
Regarding Claim 11, Myung and Yen teach the limitations of claim 1. Myung further teaches the multi-bit cell (Fig. 5: 100) comprises the plurality of capacitors (Fig. 5: 140) of which the number corresponds to the number of bits of the multi-bit input (Fig. 5: 150), and
each of the plurality of capacitors is configured to store a weight capacitance of a value corresponding to each digit of the multi-bit input.
Regarding Claim 12, Myung and Yen teach the limitations of claim 11. Myung further teaches a value of each digit (Fig. 5: 151) of the multi-bit input (Fig. 5: 150) is input to a multiplexer (Fig. 5: 131) connected to a capacitor (Fig. 5: 141) corresponding to the digit.
Regarding Claim 13, Myung and Yen teach the limitations of claim 1. Myung further teaches the plurality of capacitors (Fig. 5: 140) is further configured to
receive the output signal (Fig. 10: VB) at one end and receive a second fixed voltage (Fig. 10: VB) at an opposite end to the end, perform a differential operation on the second fixed voltage with respect to the output signal, and generate the charge data by performing a multiplication operation on a value of the differential operation and the weight capacitance (para 140 “perform a subtraction operation of the second fixed voltage with respect to the output signal, and multiply the difference value by the weight capacitance to generate the charge data.”).
Regarding Claim 14, Myung and Yen teach the limitations of claim 1. Myung further teaches the memory comprises a first memory (Fig. 9: 110a) and a second memory (Fig. 9: 110b) configured to store different weight resistances,
the multi-bit cell further comprises a sign multiplexer (Fig. 9: 132) configured to determine, based on a sign input (Fig. 9: 152), one memory to which the current (Fig. 9: 120) is to be applied between the first memory (Fig. 9: 110a) and the second memory (Fig. 9: 110b), and
a weight voltage (Fig. 9: Vw) is generated from a weight resistance stored in the determined memory.
Regarding Claim 15, Myung and Yen teach the limitations of claim 1. Myung further teaches the memory (Fig. 10: 110) comprises a first memory (Fig. 10: 110a) configured to store a first weight resistance (Fig. 10: 110a) and a second memory (Fig. 10: 110b) configured to store a second weight resistance (Fig. 10: 110b),
the current source comprises a first current source (Fig. 10: 120a) configured to apply current to the first memory (Fig. 10: 110a) to generate a first weight voltage (Fig. 10: Vw1) and a second current source (Fig. 10: 120b) configured to apply current to the second memory (Fig. 10: 110b) to generate a second weight voltage (Fig. 10: Vw2), and
each of the plurality of multiplexers (Fig. 10: 130) is configured to output one signal of the first weight voltage (Fig. 10: Vw1), the second weight voltage (Fig. 10: Vw2), and the first fixed voltage (Fig. 10: VA), based on the multi-bit input (Fig. 10: 150) comprising a sign input (Fig. 10: SIGN).
Regarding Independent Claim 16, Myung teaches a multi-bit cell (Fig. 5: 100) comprising:
a memory (Fig. 5: 110) configured to store a weight resistance corresponding to a multi-bit weight;
a current source (Fig. 5: 120) configured to apply current to the memory (Fig. 5: 110) such that a weight voltage (Fig. 5: Vw) is generated from the weight resistance;
a plurality of multiplexers (Fig. 5: 130) connected to one another in parallel and connected to the memory (Fig. 5: 110) in series and each configured to output a signal of one of the weight voltage and a first fixed voltage, based on a multi-bit input;
a plurality of capacitors (Fig. 5: 140) connected respectively to the plurality of multiplexers (Fig. 5: 130) and each configured to store a separate weight capacitance and generate charge data by performing an operation on the output signal and the weight capacitance;
a bit line (Fig. 5: VB) configured to output first sum data generated by summing pieces of charge data generated by each of the plurality of capacitors;
However, Myung fails to teach a switch of which an end is connected to the memory and an opposite end to the end is connected to the bit line.
Yen teaches a switch (Fig. 3: 314-5) capable of shorting the ends of the capacitor array together.
Yen also teaches that a switch in parallel with the capacitors and coupled to both nodes of the charge storing capacitors in the cell can be used to reset the cell (para 28). Therefore, this reset switch would be useful for addressing when the capacitors are over or undercharged in error and need to have the error corrected.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Yen to the teachings of Myung to produce a multibit memory cell with a reset switch.
Regarding Claim 17, Myung and Yen teach the limitations of claim 16. Myung further teaches a plurality of multi-bit cells (Fig. 12: 200); and
a converter (Fig. 12: 300) configured to convert second sum data into digital data, wherein the second sum data is generated by summing pieces of first sum data output from each of the plurality of multi-bit cells.
Regarding Independent Claim 18, Myung teaches a multi-bit operation method comprising:
generating a weight voltage (Fig. 5: Vw) from a weight resistance (Fig. 5: 110) by applying current (Fig. 5: 120) to a memory (Fig. 5: 110) in which the weight resistance corresponding to a multi-bit weight is stored;
receiving a multi-bit input (Fig. 5: 100) for a plurality of capacitors (Fig. 5: 140) each configured to store a separate weight capacitance;
relaying one signal of the weight voltage (Fig 5: Vw) and a first fixed voltage (Fig. 5: VA) to each of the plurality of capacitors (Fig. 5: 140), based on the multi-bit input (Fig. 5: 150);
generating charge data that is stored in each of the plurality of capacitors by performing an operation on the relayed signal and the weight capacitance (Fig. 11: 1140);
outputting first sum data generated by summing pieces of charge data generated by each of the plurality of capacitors through a bit line (Fig. 15: 1510);
However, Myung fails to teach a switch of which an end is connected to the memory and an opposite end to the end is connected to the bit line.
Yen teaches a switch (Fig. 3: 314-5) capable of shorting the ends of the capacitor array together.
Yen also teaches that a switch in parallel with the capacitors and coupled to both nodes of the charge storing capacitors in the cell can be used to reset the cell (para 28). Therefore, this reset switch would be useful for addressing when the capacitors are over or undercharged in error and need to have the error corrected.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Yen to the teachings of Myung to produce a multibit memory cell with a reset switch.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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