DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/10/2025 and 11/05/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Preliminary Amendment
The preliminary amendment filed on 05/22/2025 has been received and entered. Claim 1 has been amended, and new claims 2-20 have been added. Accordingly, claims 1-20 are examined in this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, this claim recites the limitation "the amplification unit" in line 5 on page 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Regarding claims 2-10, these claims are directly or indirectly dependent from claim 1, and therefore inheriting the indefiniteness from claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2 and 11-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12,177,594.
Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application claims are broader than the Patent claims, and are therefore encompassed by the Patent claims as listed in the following table.
Application Claims
Patent Claims (US 12,177,594)
1. A photoelectric conversion device comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are output, respectively; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, a signal corresponding to an output of the output line being input to the first input terminal, a reference signal being input to the second input terminal; a switch having a first terminal and a second terminal; and a first input capacitor arranged corresponding to each of the plurality of output lines, wherein a signal corresponding to an output of the output line is input to the first input terminal via the first input capacitor, wherein the plurality of output lines includes a first output line and a second output line, wherein the first terminal is connected to a node between a pixel corresponding to the first output line and a first input capacitor corresponding to the first output line, wherein the second terminal is connected to a node between a pixel corresponding to the second output line and a first input capacitor corresponding to the second output line, wherein the comparison unit is configured to perform an offset clamping operation of setting an offset based on potentials input to the first input terminal and the second input terminal, wherein the comparison unit is configured to perform a comparison operation between the signal corresponding to the output of the amplification unit and the reference signal, wherein during a period before the offset clamping operation is completed, the switch is turned on, and wherein during a period after the offset clamping operation is completed and before the comparison operation begins for the first time from a completion of the offset clamping operation, the switch is turned off.
Examiner’s note: Since the application claim 1 does not recite an amplification unit as in the Patent claim 1, the output lines and input lines as claimed are corresponding to the output lines and input lines without the amplification unit (simply bypassing the amplification unit or less limitations). Therefore, the subject matter is broader and met by the Patent claim 1.
1. A photoelectric conversion device comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are output, respectively; an amplification unit arranged corresponding to each of the plurality of output lines and configured to amplify a signal output to a corresponding output line; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, a signal corresponding to an output of the amplification unit being input to the first input terminal, a reference signal being input to the second input terminal; a switch having a first terminal and a second terminal; a first input capacitor arranged corresponding to each of the plurality of output lines; a holding capacitor arranged corresponding to each of the plurality of output lines and configured to hold a signal output from the amplification unit; and a first buffer arranged corresponding to each of the plurality of output lines and arranged between the holding capacitor and the first input capacitor, wherein the plurality of output lines includes a first output line and a second output line, wherein the first terminal is connected to a node between an amplification unit corresponding to the first output line and a comparison unit corresponding to the first output line, wherein the second terminal is connected to a node between an amplification unit corresponding to the second output line and a comparison unit corresponding to the second output line, wherein the comparison unit is configured to perform an offset clamping operation of setting an offset based on potentials input to the first input terminal and the second input terminal, wherein the comparison unit is configured to perform a comparison operation between the signal corresponding to the output of the amplification unit and the reference signal, wherein during a period before the offset clamping operation is completed, the switch is turned on, wherein during a period after the offset clamping operation is completed and before the comparison operation begins for the first time from a completion of the offset clamping operation, the switch is turned off, wherein a signal corresponding to an output of the amplification unit is input to the first input terminal via the first input capacitor, wherein the first terminal is connected to a first input capacitor of the first output line, wherein the second terminal is connected to a first input capacitor of the second output line, wherein the first terminal is connected to a node between a first buffer corresponding to the first output line and the first input capacitor corresponding to the first output line, and wherein the second terminal is connected to a node between a first buffer corresponding to the second output line and the first input capacitor corresponding to the second output line.
2. The photoelectric conversion device according to claim 1, wherein an operation of the switch varies depending on a gain setting of the comparison unit.
2. The photoelectric conversion device according to claim 1, wherein an operation of the switch varies depending on a gain setting of the amplification unit.
11. Equipment comprising: the photoelectric conversion device according to claim 1; and at least any one of: an optical device adapted for the photoelectric conversion device, a control device configured to control the photoelectric conversion device, a processing device configured to process a signal output from the photoelectric conversion device, a display device configured to display information obtained by the photoelectric conversion device, a storage device configured to store information obtained by the photoelectric conversion device, and a mechanical device configured to operate based on information obtained by the photoelectric conversion device.
3. Equipment comprising: the photoelectric conversion device according to claim 1; and at least any one of: an optical device adapted for the photoelectric conversion device, a control device configured to control the photoelectric conversion device, a processing device configured to process a signal output from the photoelectric conversion device, a display device configured to display information obtained by the photoelectric conversion device, a storage device configured to store information obtained by the photoelectric conversion device, and a mechanical device configured to operate based on information obtained by the photoelectric conversion device.
12. A photoelectric conversion device comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are output, respectively; an amplification unit arranged corresponding to each of the plurality of output lines and configured to amplify a signal output to a corresponding output line; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, a signal corresponding to an output of the amplification unit being input to the first input terminal, a reference signal being input to the second input terminal; a switch having a first terminal and a second terminal; and a first input capacitor arranged corresponding to each of the plurality of output lines, wherein a signal corresponding to an output of the amplification unit is input to the first input terminal via the first input capacitor, wherein the plurality of output lines includes a first output line and a second output line, wherein the first terminal is connected to a node between an amplification unit corresponding to the first output line and a first input capacitor corresponding to the first output line, wherein the second terminal is connected to a node between an amplification unit corresponding to the second output line and a first input capacitor corresponding to the second output line, wherein the comparison unit is configured to perform an offset clamping operation of setting an offset based on potentials input to the first input terminal and the second input terminal, wherein the comparison unit is configured to perform a comparison operation between the signal corresponding to the output of the amplification unit and the reference signal, and wherein during a period before the offset clamping operation is completed, the switch is turned on, and wherein during a period after the offset clamping operation is completed and before the comparison operation begins for the first time from a completion of the offset clamping operation, the switch is turned off.
13. The photoelectric conversion device according to claim 12, further comprising a holding capacitor arranged corresponding to each of the plurality of output lines and configured to hold a signal output from the amplification unit, wherein the first terminal is connected to a node between an amplification unit corresponding to the first output line and a holding capacitor corresponding to the first output line, and wherein the second terminal is connected to a node between an amplification unit corresponding to the second output line and a holding capacitor corresponding to the second output line.
1. A photoelectric conversion device comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are output, respectively; an amplification unit arranged corresponding to each of the plurality of output lines and configured to amplify a signal output to a corresponding output line; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, a signal corresponding to an output of the amplification unit being input to the first input terminal, a reference signal being input to the second input terminal; a switch having a first terminal and a second terminal; a first input capacitor arranged corresponding to each of the plurality of output lines; a holding capacitor arranged corresponding to each of the plurality of output lines and configured to hold a signal output from the amplification unit; and a first buffer arranged corresponding to each of the plurality of output lines and arranged between the holding capacitor and the first input capacitor, wherein the plurality of output lines includes a first output line and a second output line, wherein the first terminal is connected to a node between an amplification unit corresponding to the first output line and a comparison unit corresponding to the first output line, wherein the second terminal is connected to a node between an amplification unit corresponding to the second output line and a comparison unit corresponding to the second output line, wherein the comparison unit is configured to perform an offset clamping operation of setting an offset based on potentials input to the first input terminal and the second input terminal, wherein the comparison unit is configured to perform a comparison operation between the signal corresponding to the output of the amplification unit and the reference signal, wherein during a period before the offset clamping operation is completed, the switch is turned on, wherein during a period after the offset clamping operation is completed and before the comparison operation begins for the first time from a completion of the offset clamping operation, the switch is turned off, wherein a signal corresponding to an output of the amplification unit is input to the first input terminal via the first input capacitor, wherein the first terminal is connected to a first input capacitor of the first output line, wherein the second terminal is connected to a first input capacitor of the second output line, wherein the first terminal is connected to a node between a first buffer corresponding to the first output line and the first input capacitor corresponding to the first output line, and wherein the second terminal is connected to a node between a first buffer corresponding to the second output line and the first input capacitor corresponding to the second output line.
14. The photoelectric conversion device according to claim 12, further comprising: a holding capacitor arranged corresponding to each of the plurality of output lines and configured to hold a signal output from the amplification unit; and a first buffer arranged corresponding to each of the plurality of output lines and arranged between the holding capacitor and the first input capacitor, wherein the first terminal is connected to a node between a first buffer corresponding to the first output line and the first input capacitor corresponding to the first output line, and wherein the second terminal is connected to a node between a first buffer corresponding to the second output line and the first input capacitor corresponding to the second output line.
1. A photoelectric conversion device comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are output, respectively; an amplification unit arranged corresponding to each of the plurality of output lines and configured to amplify a signal output to a corresponding output line; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, a signal corresponding to an output of the amplification unit being input to the first input terminal, a reference signal being input to the second input terminal; a switch having a first terminal and a second terminal; a first input capacitor arranged corresponding to each of the plurality of output lines; a holding capacitor arranged corresponding to each of the plurality of output lines and configured to hold a signal output from the amplification unit; and a first buffer arranged corresponding to each of the plurality of output lines and arranged between the holding capacitor and the first input capacitor, wherein the plurality of output lines includes a first output line and a second output line, wherein the first terminal is connected to a node between an amplification unit corresponding to the first output line and a comparison unit corresponding to the first output line, wherein the second terminal is connected to a node between an amplification unit corresponding to the second output line and a comparison unit corresponding to the second output line, wherein the comparison unit is configured to perform an offset clamping operation of setting an offset based on potentials input to the first input terminal and the second input terminal, wherein the comparison unit is configured to perform a comparison operation between the signal corresponding to the output of the amplification unit and the reference signal, wherein during a period before the offset clamping operation is completed, the switch is turned on, wherein during a period after the offset clamping operation is completed and before the comparison operation begins for the first time from a completion of the offset clamping operation, the switch is turned off, wherein a signal corresponding to an output of the amplification unit is input to the first input terminal via the first input capacitor, wherein the first terminal is connected to a first input capacitor of the first output line, wherein the second terminal is connected to a first input capacitor of the second output line, wherein the first terminal is connected to a node between a first buffer corresponding to the first output line and the first input capacitor corresponding to the first output line, and wherein the second terminal is connected to a node between a first buffer corresponding to the second output line and the first input capacitor corresponding to the second output line.
15. The photoelectric conversion device according to claim 12, wherein an operation of the switch varies depending on a gain setting of the amplification unit.
2. The photoelectric conversion device according to claim 1, wherein an operation of the switch varies depending on a gain setting of the amplification unit.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, 8, 12, 13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Egawa (US 2011/0155890 A1).
Regarding claim 1, Egawa discloses a photoelectric conversion device (Figs. 1-13) comprising:
a plurality of pixels (Fig. 1);
a plurality of output lines (column lines VLIN1, VLIN2, VLIN3, …), to which signals (Vsig1, Vsig1, Vsig3, …) from corresponding pixels are output, respectively (Figs 1 & 2 and par. [0022]-[0023]);
a comparison unit (AP2) arranged corresponding to each of the plurality of output lines and having a first input terminal (the first input terminal that receives signal from C1 and/or C4) and a second input terminal (the second input terminal that is connected to NR as shown in Fig. 2), a signal corresponding to an output of the output line being input to the first input terminal, a reference signal (NR) being input to the second input terminal (Fig. 2 and par. [0041]-[0043]);
a switch having (SW3) a first terminal (upper terminal) and a second terminal (lower terminal) (Fig. 2); and
a first input capacitor (C4 or C1) arranged corresponding to each of the plurality of output lines, wherein a signal corresponding to an output of the output line is input to the first input terminal via the first input capacitor (Fig. 2 and par. [0042]-[0043]), wherein the plurality of output lines includes a first output line (VLIN1/Vsig1) and a second output line (VLN2/Vsig2), wherein the first terminal (upper terminal) is connected to a node (the node above C4 in Fig. 2) between a pixel corresponding to the first output line and a first input capacitor corresponding to the first output line (see Fig. 2), wherein the second terminal (lower terminal) is connected to a node between a pixel corresponding to the second output line and a first input capacitor corresponding to the second output line (see Fig. 2), wherein the comparison unit is configured to perform an offset clamping operation of setting an offset based on potentials input to the first input terminal and the second input terminal (see Fig. 3 and par. [0046]-[0048] in which the offset is indicated by “BLACK LEVEL”), wherein the comparison unit is configured to perform a comparison operation between the signal corresponding to the output of the amplification unit and the reference signal (NR), wherein during a period before the offset clamping operation is completed, the switch (SW3) is turned on (Fig. 3 shows that SW3 is on during and before the offset clamping set by SW1 and SW4 is completed), and wherein during a period after the offset clamping operation is completed and before the comparison operation begins (“FIRST ADC DOWN-COUNTING”) for the first time from a completion of the offset clamping operation, the switch is turned off (see Fig. 3 and par. [0048]-[0054] and note that SW3 is off before the first ADC down-counting).
Regarding claim 2, Egawa also discloses that an operation of the switch varies depending on a gain setting of the comparison unit (see par. [0048] in which the operation of switch SW3 varies when the gain setting of the comparison unit AP2 varies based on the input and output terminals of the comparison unit being short-circuited or not).
Regarding claim 3, as also disclosed by Egawa, an operation of the switch varies depending on an amount of change per unit time of a potential of the reference signal (see Fig. 3 in which the operation of SW3 depends on the amount of charge per time unit of a potential of the reference signal NR represented by down-counting and up-counting ramps).
Regarding claim 4, it is also seen in Egawa that an operation of the switch varies depending on temperature of the photoelectric conversion device (see par. [0061]. It should be
noted that the KTC noise is inherently proportional to temperature, and the operation of switch
SW3 reduces the KTC noise. Thus, the operation of the switch varies depending on temperature of the photoelectric conversion device).
Regarding claim 5, as also shown in Fig. 3 in Egawa, after the switch (SW3) is turned off, a potential of the reference signal starts to change depending on time.
Regarding claim 7, Egawa further discloses that the signal includes a noise signal and a photoelectric conversion signal, and wherein the noise signal and the photoelectric conversion signal are used in the comparison operation (see par. [0046]-[0054]).
Regarding claim 8, as shown in Figs. 1-3 in Egawa, a pixel of the plurality of pixels includes a transfer transistor (Td in Fig. 1 which is controlled by signal φT shown in Fig. 3), wherein the pixel outputs the photoelectric conversion signal when the transfer transistor is turned on, and wherein in a period before the transfer transistor is turned on, the switch is turned off (note Fig. 3 where SW3 is turned off before φT is active high to turn on transfer transistor Td).
Regarding claim 12, Egawa also discloses the subject matter of claim 12 that comprises similar limitations as discussed in claim 1. Egawa further discloses an amplification unit (column amplifier AP1 in Fig. 2) arranged corresponding to each of the plurality of output lines and configured to amplify a signal output to a corresponding output line (Fig. 2 and par. [0041]); a comparison unit (AP2) arranged corresponding to each of the plurality of output lines and having a first input terminal (the first input terminal that receives signal from C1 and/or C4) and a second input terminal (the second input terminal that is connected to reference signal NR), a signal corresponding to an output of the amplification unit being input to the first input terminal, a reference signal (NR) being input to the second input terminal (see Fig. 2 and par. [0041]-[0043]).
Regarding claim 13, further disclosed by Egawa is a holding capacitor (C4) arranged corresponding to each of the plurality of output lines and configured to hold a signal output from the amplification unit (Fig. 2), wherein the first terminal (upper terminal of SW3 in Fig. 2) is connected to a node between an amplification unit (AP1) corresponding to the first output line (Vsig1) and a holding capacitor (C4) corresponding to the first output line, and wherein the second terminal (lower terminal of SW3 in Fig. 2) is connected to a node between an amplification unit corresponding to the second output line (Vsig2) and a holding capacitor (C4) corresponding to the second output line (Fig. 2 and par. [0040]-[0044]).
Regarding claim 15, Egawa also discloses that an operation of the switch varies depending on a gain setting of the amplification unit (see par. [0044]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Egawa in view of Yamazaki et al. (US 2020/0084397 A1).
Regarding claim 11, Egawa teaches the photoelectric conversion device as discussed in claim 1. Egawa fails to teach an equipment comprising at least any one of: an optical device adapted for the photoelectric conversion device, a control device configured to control the photoelectric conversion device, a processing device configured to process a signal output from the photoelectric conversion device, a display device configured to display information obtained by the photoelectric conversion device, a storage device configured to store information obtained by the photoelectric conversion device, and a mechanical device configured to operate based on information obtained by the photoelectric conversion device.
However, as taught by Yamazaki, a solid state imaging device can be applied to various imaging system including an equipment (Figs. 8 & 9) comprising a photoelectric conversion device (100), and at least one of: an optical device (202, 204, 206) adapted for the photoelectric conversion device, a control device (218) configured to control the photoelectric conversion device, a processing device (208) configured to process a signal output from the photoelectric conversion device, a display device (computer display) configured to display information obtained by the photoelectric conversion device, a storage device (210, 214) configured to store information obtained by the photoelectric conversion device, and a mechanical device (drive units for driving focus lens and aperture) configured to operate based on information obtained by the photoelectric conversion device (Yamazaki, Fig. 8 and par. [0121]).
Therefore, it would have been obvious to one of ordinary skill in the art combine the teachings of Egawa and Yamazaki to arrive at the Applicant’s claimed invention to implement an equipment such as a digital camera, a mobile phone, on-vehicle camera, etc., for practical use as taught by Yamazaki in paragraph [0120].
Allowable Subject Matter
Claims 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19 and 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 16, the prior art references of record fail to teach or suggest: “the plurality of output lines further includes a third output line, and wherein at a time point when the offset clamping operation is completed, a potential of a reference signal input to a comparison unit corresponding to the first output line and a potential of a reference signal input to a comparison unit corresponding to the third output line are different from each other.”
Regarding claim 17, the prior art references of record also fail to teach or suggest: “an output line connection switch having a third terminal and a fourth terminal, wherein the third terminal is connected to a node between a pixel corresponding to the first output line and the amplification unit corresponding to the first output line, and wherein the fourth terminal is connected to a node between a pixel corresponding to the second output line and the amplification unit corresponding to the second output line.”
Regarding claim 18, this claim is dependent from claim 17.
Regarding claim 19, the prior art references of record fail to teach or suggest the combination of limitations recited in claim 19: “the reference signal is input to the second input terminal via the second input capacitor, wherein the plurality of output lines includes a first output line and a second output line, wherein the first terminal is connected to a second input capacitor corresponding to the first output line, wherein the second terminal is connected to a second input capacitor corresponding to the second output line, wherein the comparison unit is configured to perform an offset clamping operation of setting an offset based on potentials input to the first input terminal and the second input terminal, wherein during a period before the offset clamping operation is completed, the switch is turned on, and wherein after the offset clamping operation is completed, the switch is turned off.”
Regarding claim 20, this claim is dependent from claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/NHAN T TRAN/Primary Examiner, Art Unit 2638