DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 21-40 are pending. Claims 1-20 have been canceled as per Applicants' request. Claims 21-40 have been added as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on June 18, 2026
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 24-30 and 39 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 24 recites “the second memory controller is configured to receive from the first memory the third read data associated with the second memory address, and generate forwarding third read data and an eighth response control signal; and the memory controller subsystem is configured to: compare the read data received by the first memory controller with the read data received by the second memory controller; and generate a second error signal in response to the read data received by the first memory controller not being equal to the read data received by the second memory controller”. Claim 39 recites “generating, by the second memory controller, forwarding read data and a fourth response control signal; comparing, by the memory controller subsystem, the read data received by the first memory controller with the read data received by the second memory controller; and generating, by the memory controller subsystem, a second error signal in response to the read data received by the first memory controller not being equal to the read data received by the second memory controller”.
Applicant points to Figures 9 and 10 for support. Paragraphs [0131]-[0152] corresponds to the figure 10, disclose operations performed in response to a read request, but do not provide written-description support for the limitations recited in claims 24 and 39. In particular, although the specification describes the first memory controller 500a receiving read data DATA_OUTa from the first memory 42a, and describes the data DATA_OUTa being provided on the IO lines to the second memory controller 500b, the specification does not disclose that the first memory controller transfers or forwards the read data it received to the second memory controller. Rather, paragraph [0146] explains that the data DATA_OUTa output by the first memory is provided to the second memory controller through the IO lines, such that the second memory controller can receive the data from the memory interface. Paragraphs [0146]-[0147] further describe the second memory controller receiving/sampling the data and treating the sampled data as DATA_OUTb. Thus, the disclosed arrangement does not teach the claimed operation of the second memory controller generating “forwarding third read data” as recited in claim 24 or “forwarding read data” as recited in claim 39. Nor does it disclose the corresponding claimed sequence in which the second memory controller generates the forwarding read data and associated response control signal for forwarding data received from the first memory controller. Although paragraphs [0149]-[0150] disclose comparing DATA_OUTa and DATA_OUTb and generating an error signal when the data differ, those paragraphs do not cure the absence of written-description support for the preceding claimed forwarding operation. Accordingly, Figures 9 and 10 and paragraphs [0131]-[0152] do not provide written-description support for the limitations of claims 24 and 39 requiring the second memory controller to generate forwarding read data (or forwarding third read data) and the associated response control signal.
Therefore the specification as originally filed does not provide support for “the second memory controller is configured to receive from the first memory the third read data associated with the second memory address, and generate forwarding third read data and an eighth response control signal; and the memory controller subsystem is configured to: compare the read data received by the first memory controller with the read data received by the second memory controller; and generate a second error signal in response to the read data received by the first memory controller not being equal to the read data received by the second memory controller” and “generating, by the second memory controller, forwarding read data and a fourth response control signal; comparing, by the memory controller subsystem, the read data received by the first memory controller with the read data received by the second memory controller; and generating, by the memory controller subsystem, a second error signal in response to the read data received by the first memory controller not being equal to the read data received by the second memory controller”.
Claims 25-30 depends on claim 24 and therefore inherit this deficiency.
Claim 26 recites “wherein the memory controller subsystem is configured to, in response to receiving the read request: compare the third read data forwarded by the first memory controller with the forwarding third read data generated by the second memory controller; and generate a third error signal in response to the third read data forwarded by the first memory controller not being equal to the forwarding third read data generated by the second memory controller”.
Applicant points to Figures 9 and 10 for support and paragraphs [0131]-[0152] corresponds to the in response to read request portion. These portions of the specification, however, do not provide written-description support for these limitations. As discussed above, the specification does not disclose the second memory controller generating any separate “forwarding third read data.” Rather, paragraphs [0146]-[0147] disclose that the first memory 42a outputs DATA_OUTa on the IO lines and that corresponding data is received by the second memory controller 500b through the IO lines. Similarly, DATA_OUTb is data output by the second memory 42b, rather than data generated by the second memory controller 500b. Thus, the cited disclosure does not identify any read data generated or forwarded by the second memory controller corresponding to the claimed “forwarding third read data generated by the second memory controller.” Consequently, the specification also does not disclose the claimed comparison between the third read data forwarded by the first memory controller and forwarding third read data generated by the second memory controller. The comparison disclosed in paragraphs [0149]-[0150] is instead between read data received by the respective memory controllers and does not disclose a comparison involving a separately generated forwarding third read data from the second memory controller. Accordingly, because the specification does not disclose the second memory controller generating the claimed forwarding third read data, it does not disclose the two claimed data items that are required to be compared under claim 26.
Therefore the specification as originally filed does not provide support for “wherein the memory controller subsystem is configured to, in response to receiving the read request: compare the third read data forwarded by the first memory controller with the forwarding third read data generated by the second memory controller; and generate a third error signal in response to the third read data forwarded by the first memory controller not being equal to the forwarding third read data generated by the second memory controller”.
Claims 27 depends on claim 26 and therefore inherit this deficiency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 24-30 and 39 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 24 recites, in part, that “the second memory controller is configured to receive from the first memory the third read data associated with the second memory address, and generate forwarding third read data and an eighth response control signal.”
Claim 39 similarly recites “generating, by the second memory controller, forwarding read data and a fourth response control signal.” The metes and bounds of these limitations are unclear because it is not apparent what is meant by “forwarding third read data” or “forwarding read data,” or what data is required to be generated by the second memory controller.
In particular, claim 24 first requires the second memory controller to receive “the third read data” from the first memory, but then requires the second memory controller to “generate forwarding third read data.” The claim does not make clear whether the “forwarding third read data” is the same third read data received from the first memory, a copy of that data, modified data, or a separately generated data value. Moreover, the claim does not identify what operation performed by the second memory controller constitutes “generat[ing]” the forwarding third read data. This ambiguity is particularly problematic because “read data” ordinarily represents data read from a memory, whereas the claim attributes generation of the “forwarding third read data” to the second memory controller. The same ambiguity is present in claim 39, which requires the second memory controller to “generat[e] ... forwarding read data” without identifying the relationship between the forwarding read data and the read data previously received by the second memory controller. The claim therefore does not provide a reasonably clear boundary as to what data satisfies the “forwarding read data” limitation or when the second memory controller has performed the claimed generation of that data.
Further, both claims subsequently require the memory controller subsystem to compare the read data received by the first memory controller with the read data received by the second memory controller. It is unclear how the claimed “forwarding” operation relates to this comparison, including whether the forwarding third read data/forwarding read data is the same data as the “read data received by the second memory controller”, the “generated read data”, or is a separate data item. Thus, the claims do not clearly establish the identity and relationship of the data items that are received, generated, and compared. Accordingly, claims 24 and 39, when read as a whole, fail to particularly point out and distinctly claim the subject matter regarded as the invention because the terms “forwarding third read data” and “forwarding read data,” and their relationship to the read data received by the respective memory controllers, do not provide reasonably clear metes and bounds.
For purposes of examination, and consistent with the disclosure relied upon by Applicant, the limitations of claims 24 and 39 reciting that the second memory controller generates “forwarding third read data” or “forwarding read data” are interpreted as the second memory controller receiving DATA_OUTb from the memory in response to the read request. Accordingly, the subsequent limitation requiring comparison of the read data received by the first memory controller with the read data received by the second memory controller is interpreted as requiring comparison of DATA_OUTa received by the first memory controller with DATA_OUTb received by the second memory controller, consistent with paragraphs [0138] and [0147] and Figure 10.
Claims 25-30 depends on claim 24 and therefore inherits this deficiency.
Claim 26 recites, that the memory controller subsystem is configured to “compare the third read data forwarded by the first memory controller with the forwarding third read data generated by the second memory controller” and to “generate a third error signal” in response to the two data being unequal. The metes and bounds of these limitations are unclear because the claim does not clearly identify what constitutes the “third read data forwarded by the first memory controller” or the “forwarding third read data generated by the second memory controller,” or how the two data items are related. In particular, the claim characterizes the first data item as “third read data forwarded by the first memory controller,” while characterizing the second data item as “forwarding third read data generated by the second memory controller.” It is unclear whether the “forwarding third read data” generated by the second memory controller is intended to be the same third read data received by the second memory controller, a copy of the third read data, or some different data generated by the second memory controller.
The claim does not identify what operation constitutes “forwarding” or “generating” the forwarding third read data, nor does it establish how the second memory controller generates such data from the third read data. The ambiguity is further compounded by the requirement that the subsystem compare the two data items. The claim does not clearly identify two distinct data values that are to be compared, particularly because both data items are referred to as “third read data” and the second is additionally characterized as “forwarding” data. Thus, it is unclear whether the claimed comparison is intended to compare the same read data as received or forwarded through the respective memory controllers, or instead to compare two separately generated data values. Because the claim does not clearly define the identity, source, or relationship of the two data items, it is also unclear what circumstances would satisfy the requirement to generate the “third error signal” when the first data item is not equal to the second data item. Accordingly, claim 26 fails to particularly point out and distinctly claim the subject matter regarded as the invention because the scope of the “third read data forwarded by the first memory controller” and the “forwarding third read data generated by the second memory controller,” as well as the required comparison between them, cannot be determined with reasonable certainty.
For purposes of examination, and consistent with the disclosure relied upon by Applicant, the limitations of claim 26 reciting “the third read data forwarded by the first memory controller” and “the forwarding third read data generated by the second memory controller” are interpreted as referring to DATA_OUTa received by the first memory controller from the first memory and DATA_OUTb received by the second memory controller from the second memory, respectively, in response to the read request. Accordingly, the limitation requiring comparison of the third read data forwarded by the first memory controller with the forwarding third read data generated by the second memory controller is interpreted as requiring comparison of DATA_OUTa with DATA_OUTb, consistent with paragraphs [0138] and [0147] and Figure 10.
Claims 27 depends on claim 26 and therefore inherits this deficiency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 22, and 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over JIN et al. (US 2021/0173785) (hereinafter Jin) (published June 10, 2021) in view of LEE et al. (US 2021/0223991) (hereinafter Lee) (published July 22, 2021).
Regarding Claims 21 and 38, taking claim 21 as exemplary, Jin discloses a processing system integrated in an integrated circuit, the processing system comprising: a communication system;
“The processor 1010 may control overall operation of the memory controller 1000 and may perform a logical operation. The processor 1010 may communicate with the host through the host interface 1040 and communicate with the memory device through the memory interface 1060” (Jin [0199] the communication system is what connects the host to the host interface)
a memory controller subsystem configured to interface with first and second memories external to the integrated circuit; and
“The host interface 210 may perform communication with the host 300 and the first memory controller 200_1. The flash controller 220_1 may control overall operation of the first memory controller 200_1 and operation of the first memory device group 100_1. The flash controller 220_1 may control the first memory device group 100_1 to perform an operation according to the request of the host 300. The flash controller 220_1 may control the second memory controller 200_2 so that the second memory device group 100_2 performs the operation according to the request of the host 300” (Jin [0114] see fig. 5, first and second memory device groups are external to the controllers)
“The processor 1010 may control overall operation of the memory controller 1000 and may perform a logical operation. The processor 1010 may communicate with the host through the host interface 1040 and communicate with the memory device through the memory interface 1060” (Jin [0199])
a master circuit configured to send write and read requests via the communication system to the memory controller subsystem to store write data to and retrieve read data from at least the first memory;
“The memory device 100 is configured to receive a command and an address from the memory controller 200 and access an area selected by the address of the memory cell array. That is, the memory device 100 may perform an operation instructed by the command on the area selected by the address. For example, the memory device 100 may perform a write operation (program operation), a read operation, and an erase operation” (Jin [0036])
“The host interface 210 may perform communication with the host 300 and the first memory controller 200_1. The flash controller 220_1 may control overall operation of the first memory controller 200_1 and operation of the first memory device group 100_1. The flash controller 220_1 may control the first memory device group 100_1 to perform an operation according to the request of the host 300. The flash controller 220_1 may control the second memory controller 200_2 so that the second memory device group 100_2 performs the operation according to the request of the host 300” (Jin [0114] see fig. 5, the host/master circuit sends requests over “communication system” to the controller where the request are processed)
wherein the memory controller subsystem is connected to the communication system and to a communication channel connected to terminals of the integrated circuit configured to be connected to the first and second memories;
“Referring to FIG. 5, the first memory controller 200_1 may include a host interface 210, a flash controller 220_1, a memory interface 230_1, a chip interface 240_1, and a memory buffer 250_1” (Jin [0113] see fig. 5, the first memory controller includes host interface for connection via the “communication system” to the host and memory interface for connection via the “communication channel” to the first memory device)
“The second memory controller 200_2 may include a flash controller 220_2, a memory interface 230_2, a chip interface 240_2, and a memory buffer 250_2” (Jin [0116] see fig. 5, the second memory controller includes memory interface for connection via the “communication channel” to the second memory device)
wherein the memory controller subsystem comprises first and second memory controllers, and the memory controller subsystem is configured to receive, from the communication system, a write request comprising a first memory address and write data, and a read request comprising a second memory address;
“In FIG. 5, the first memory controller 200_1 is shown as the main controller and the second memory controller 200_2 is shown as the only sub controller” (Jin [0118])
“The operation controller 410 may receive a write request for storing data in the memory device groups 100_1 and 100_2 from the host 300. The operation controller 410 may receive the write request, write data, and a logical address in which the write data is to be stored from the host 300. The operation controller 410 may generate a write command according to the write request” (Jin [0125])
“The operation controller 410 may receive the read request for reading data stored in the memory device groups 100_1 and 100_2 from the host 300. The operation controller 410 may receive the read request and a logical address in which the data to be read is stored from the host 300. The operation controller 410 may generate a read command according to the read request” (Jin [0129])
wherein, in a first operating mode: in response to the write request and to the first memory address being in a first address range, the first memory controller is configured to transmit to the first memory a first write command comprising the first memory address and the write data, and the second memory controller is configured to disregard the write request;
“In an embodiment, when the logical address is included in a first logical address range, the operation controller 410 may provide the write command and the write data to the first memory device group 100_1. When the logical address is included in a second logical address range, the operation controller 410 may provide the write command and the write data to the second memory controller 500” (Jin [0127] the second memory controller would disregard the write request as it is not directed to its address range)
in response to the write request and to the first memory address being in a second address range different from the first address range, the second memory controller is configured to transmit to a second memory a second write command comprising the first memory address and the write data, and the first memory controller is configured to disregard the write request;
“In an embodiment, when the logical address is included in a first logical address range, the operation controller 410 may provide the write command and the write data to the first memory device group 100_1. When the logical address is included in a second logical address range, the operation controller 410 may provide the write command and the write data to the second memory controller 500” (Jin [0127] the first memory controller would disregard the write request as it is not directed to its address range)
in response to the read request and to the second memory address being in the first address range, the first memory controller is configured to transmit to the first memory a first read command comprising the second memory address, receive from the first memory first read data associated with the second memory address, and forward to the communication system the first read data, and the second memory controller is configured to disregard the read request; and
“When the logical address is included in the first mapping table, the operation controller 410 may provide the read command to the first memory device group 100_1. When the logical address is included in the second mapping table, the operation controller 410 may provide the read command to the second memory device group 100_2” (Jin [0131] the second memory controller would disregard the read request as it is not directed to its address range)
“The operation controller 410 may provide read data obtained from the memory device group that performed the read operation according to the read command to the host 300 in response to the read request” (Jin [0132])
in response to the read request and to the second memory address being in the second address range, the second memory controller is configured to transmit to the second memory a second read command comprising the second memory address, receive from the second memory second read data associated with the second memory address, and forward to the communication system the second read data, and the first memory controller is configured to disregard the read request.
“When the logical address is included in the first mapping table, the operation controller 410 may provide the read command to the first memory device group 100_1. When the logical address is included in the second mapping table, the operation controller 410 may provide the read command to the second memory device group 100_2” (Jin [0131] the first memory controller would disregard the read request as it is not directed to its address range)
“The operation controller 410 may provide read data obtained from the memory device group that performed the read operation according to the read command to the host 300 in response to the read request” (Jin [0132])
But does not explicitly state forward to the communication system a first response control signal, forward to the communication system a second response control signal, forward to the communication system a third response control signal, and forward to the communication system a fourth response control signal.
Jin and Lee discloses forward to the communication system a first response control signal, forward to the communication system a second response control signal, forward to the communication system a third response control signal, and forward to the communication system a fourth response control signal.
“In an embodiment, when the logical address is included in a first logical address range, the operation controller 410 may provide the write command and the write data to the first memory device group 100_1. When the logical address is included in a second logical address range, the operation controller 410 may provide the write command and the write data to the second memory controller 500” (Jin [0127])
“When the logical address is included in the first mapping table, the operation controller 410 may provide the read command to the first memory device group 100_1. When the logical address is included in the second mapping table, the operation controller 410 may provide the read command to the second memory device group 100_2” (Jin [0131])
“When a read/write operation is completed, the data storage device 300 provides a complete signal indicating that processing of a command has been completed to the host processor 100 via the bus circuit 400” (Lee [0053] with respect to each of the write/read commands of Jin a respective complete signal is provided)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system of Jin in view of Lee to provide, for each of the write and read operations performed by the first and second memory controllers, a respective response control signal that is forwarded to the communication system. By applying Lee's completion signaling to Jin's request-processing architecture would have resulted in the first and second memory controllers providing corresponding response control signals for their respective write and read operations and forwarding those signals through the communication system to the host. Such a modification would have involved the use of known signaling functionality for its known purpose and would have been within the ordinary skill in the art. The motivation for doing so would have been to provide the host with an explicit indication of the status or completion of each command issued to the memory controller subsystem, thereby allowing the host to determine when a requested operation has been processed and, where applicable, when the associated read data is available. Lee demonstrates that providing a completion signal to a host processor upon completion of command processing was a known technique for coordinating communication between a host and a data storage device. Incorporating such signaling into Jin would have improved the coordination and synchronization between the host and the memory controller subsystem, particularly where different memory controllers selectively process requests according to different address ranges. The combination also would have provided a predictable and straightforward way for the host to distinguish completion of operations directed to the respective memory devices without changing Jin's basic address-based allocation of requests or its underlying memory-controller architecture.
Regarding Claim 22, Jin further discloses wherein the memory controller subsystem is further configured to receive, from the communication system, a request control signal indicating a write or a read.
“The flash controller 220_1 may control the first memory device group 100_1 to perform an operation according to the request of the host 300. The flash controller 220_1 may control the second memory controller 200_2 so that the second memory device group 100_2 performs the operation according to the request of the host 300” (Jin [0114])
“The operation controller 410 may receive a request REQ associated with a write operation, an address ADDR, and data DATA from the host 300. The operation controller 410 may provide data DATA to the host 300 in response to a request REQ associated with a read operation” (Jin [0124])
Claim 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (published June 10, 2021) and Lee (published July 22, 2021) as applied to claim 21 above, and further in view of Tanaka et al. (US 2020/0076645) (hereinafter Tanaka) (published March 05, 2020).
Regarding Claim 23, the combination of Jin and Lee disclosed the system of claim 21, but does not explicitly state wherein: in response to the first or second memory address being in the first address range, the first memory controller is further configured to assert a first chip select signal to select the first memory; and in response to the first or second memory address being in the second address range, the second memory controller is further configured to assert a second chip select signal to select the second memory.
Jin and Tanaka discloses wherein: in response to the first or second memory address being in the first address range, the first memory controller is further configured to assert a first chip select signal to select the first memory; and in response to the first or second memory address being in the second address range, the second memory controller is further configured to assert a second chip select signal to select the second memory.
“In FIG. 5, the first memory controller 200_1 is shown as the main controller and the second memory controller 200_2 is shown as the only sub controller” (Jin [0118] the memories are connected to the controllers)
“The memory controller and the memory are connected by using a serial interface such as a Serial Peripheral Interface (SPI). Here, the memory controller operates as a master device, and the memory as a slave device to be controlled by the master device. According to the SPI standard, a master device can select a memory to communicate by asserting a chip select signal, and transmit signals to the selected memory for data read and write” (Tanaka [0003])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system in the combination of Jin and Lee, further in view of Tanaka to implement the communication to Jin's first and second memory controllers using an SPI interface. By applying Tanaka's SPI interface and chip-select signaling to Jin would provide a serial communication link between the memory side of the system and the first and second memory controllers, while allowing the appropriate memory controller to be selected for communication based on the address range of the request. Thus, when a request is directed to the first address range, the first memory controller could assert its first chip select signal and communicate with the memory over the SPI interface, and when a request is directed to the second address range, the second memory controller could assert its second chip select signal and communicate with the memory over the same SPI interface. Such a modification would have been a straightforward application of Tanaka's known SPI communication and chip-select technique to Jin's existing architecture having two separate memory controllers. The motivation for doing so would have been to provide a simple and conventional serial communication interface through which the two memory controllers could selectively communicate with the memory. Tanaka teaches that SPI permits a master to select a device for communication using a chip select signal and then transmit read and write signals to the selected device. Applying this known SPI arrangement to Jin would have provided a predictable mechanism for allowing the first and second memory controllers to share communication with the memory while maintaining separate selection of the respective controller based on the address range of a request.
Claims 24-26, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (published June 10, 2021) and Lee (published July 22, 2021) as applied to claim 21 above, and further in view of Costa et al. (US 2020/0310683) (hereinafter Costa) (published October 01, 2020).
Regarding Claim 24, the combination of Jin and Lee disclosed the system of claim 21, but does not explicitly state wherein the communication channel is a shared communication channel, and wherein, in a second operating mode: in response to receiving the write request: the first memory controller is configured to transmit to the first memory a third write command comprising the first memory address and the write data, and forward to the communication system a fifth response control signal; the second memory controller is configured to generate a fourth write command comprising the write data, and generate a sixth response control signal; and the memory controller subsystem is configured to: compare the write data transmitted by the first memory controller with the write data generated by the second memory controller; and generate a first error signal in response to the write data transmitted by the first memory controller not being equal to the write data generated by the second memory controller; and in response to receiving the read request: the first memory controller is configured to transmit to the first memory a third read command comprising the second memory address, receive from the first memory third read data associated with the second memory address, and forward to the communication system the third read data and a seventh response control signal; the second memory controller is configured to receive from the first memory the third read data associated with the second memory address, and generate forwarding third read data and an eighth response control signal; and the memory controller subsystem is configured to: compare the read data received by the first memory controller with the read data received by the second memory controller; and generate a second error signal in response to the read data received by the first memory controller not being equal to the read data received by the second memory controller.
Costa and Lee discloses wherein the communication channel is a shared communication channel, and wherein, in a second operating mode: in response to receiving the write request: the first memory controller is configured to transmit to the first memory a third write command comprising the first memory address and the write data, and forward to the communication system a fifth response control signal; the second memory controller is configured to generate a fourth write command comprising the write data, and generate a sixth response control signal; and
“More specifically, if the decoded write address corresponds with a lockstep region of the memory 140, the lockstep processor 124L is configured to generate, based on the decoded write address, primary and redundant memory write addresses XPTO_A, XPTO_B and corresponding primary and redundant copies of the write data XY_A, XY_B in lockstep” (Costa [0021])
“As shown in FIG. 1B, the lockstep processor 124L comprises a primary data path processor 124LP and a redundant data path processor 124LR. The address XPTO and data XY arrive from one path to both the primary data path processor 124LP and the redundant data path processor 114LR, which operate in lockstep. The primary data path processor 124LP generates the primary memory write address XPTO_A and the primary copy of the write data XY_A. The redundant data path processor 114LR generates the redundant memory write address XPTO_B and the redundant copy of the write data XY_B in lockstep with the primary data path processor 114LP” (Costa [0022])
“When a read/write operation is completed, the data storage device 300 provides a complete signal indicating that processing of a command has been completed to the host processor 100 via the bus circuit 400” (Lee [0053] with respect to each of the write commands of Costa a respective complete signal is provided)
the memory controller subsystem is configured to: compare the write data transmitted by the first memory controller with the write data generated by the second memory controller; and generate a first error signal in response to the write data transmitted by the first memory controller not being equal to the write data generated by the second memory controller; and
“The comparator 126 is configured to compare the primary and redundant copies of the write data XY_A, XY_B. The comparator 126 is also configured to compare the primary and redundant memory write addresses XPTO_A, XPTO_B. This comparison is to determine if there are any errors before the data is written in the memory 140. If the primary (XPTO_A) and redundant (XPTO_B) memory write addresses differ from what they should be, or the primary (XY_A) and redundant (XY_B) copies of the write data differ, the comparator 116 is configured to generate an error signal” (Costa [0024])
in response to receiving the read request: the first memory controller is configured to transmit to the first memory a third read command comprising the second memory address, receive from the first memory third read data associated with the second memory address, and forward to the communication system the third read data and a seventh response control signal;
“If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B. The primary data path processor 220LP is configured to generate the primary memory read address XPTO_A. The redundant data path processor 220LR is configured to generate the redundant memory read address XPTO_B in lockstep with the primary data path processor 220LP” (Costa [0032])
“The primary copy of the read data XY_A is read from the primary memory 240A and transmitted to the memory dispatcher 220 via the memory controller 230A, and the redundant copy of the read data XY_B is read from the redundant memory 240B and transmitted to the memory dispatcher 220 via the memory controller 230B” (Costa [0033])
“When a read/write operation is completed, the data storage device 300 provides a complete signal indicating that processing of a command has been completed to the host processor 100 via the bus circuit 400” (Lee [0053] with respect to each of the read commands of Costa a respective complete signal is provided)
the second memory controller is configured to receive from the first memory the third read data associated with the second memory address, and generate forwarding third read data and an eighth response control signal; and (see 112 rejections above)
“The primary copy of the read data XY_A is read from the primary memory 240A and transmitted to the memory dispatcher 220 via the memory controller 230A, and the redundant copy of the read data XY_B is read from the redundant memory 240B and transmitted to the memory dispatcher 220 via the memory controller 230B” (Costa [0033])
“When a read/write operation is completed, the data storage device 300 provides a complete signal indicating that processing of a command has been completed to the host processor 100 via the bus circuit 400” (Lee [0053] with respect to each of the read commands of Costa a respective complete signal is provided)
the memory controller subsystem is configured to: compare the read data received by the first memory controller with the read data received by the second memory controller; and generate a second error signal in response to the read data received by the first memory controller not being equal to the read data received by the second memory controller. (see 112 rejections above)
“The comparator 226 is configured to compare the primary and redundant copies of the read data XY_A, XY_B. The comparator 226 is also configured to compare the primary and redundant memory read addresses XPTO_A, XPTO_B. If the primary (XPTO_A) and redundant (XPTO_B) memory read addresses differ from what they should be, or the primary (XY_A) and redundant (XY_B) copies of the read data differ, the comparator 116 is configured to generate an error signal” (Costa [0034])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system in the combination of Jin and Lee, and further in view of Costa to provide a second operating mode in which the first and second memory controllers operate in lockstep to process corresponding copies of write and read operations. By applying Costa's lockstep architecture to Jin would result in the first memory controller processing the write request to generate a corresponding write command and write data for the first memory, while the second memory controller processes the same write request in lockstep to generate a corresponding write command and write data for the second memory. The respective write data generated by the first and second memory controllers could then be compared to detect an error. Costa similarly provides corresponding lockstep processing and comparison for read operations. Lee's completion signaling could further be applied to these operations to provide the respective response control signals to the host. Such a modification would have been a predictable application of Costa's known lockstep and error-detection techniques and Lee's known completion signaling to Jin's existing memory-controller architecture. The motivation for doing so would have been to improve the reliability and fault-detection capability of Jin's memory system by allowing corresponding operations performed through the first and second memory controllers to be independently generated and compared. Costa uses redundant data paths operating in lockstep and compares corresponding addresses and data to detect errors before data is written and during read operations. Incorporating this functionality into Jin would therefore have provided a known mechanism for detecting discrepancies between the outputs of the first and second memory controllers, including discrepancies in write data and read data. This would have been particularly beneficial in applications in which data integrity and reliable memory operation are important, because an erroneous command or data value produced by one controller could be identified by comparison with the corresponding operation of the other controller.
Regarding Claim 25, Costa and Lee further discloses wherein the memory controller subsystem is further configured to: in response to receiving the write request: compare the fifth response control signal with the sixth response control signal; and generate the second error signal in response to the fifth response control signal not being equal to the sixth response control signal; and in response to receiving the read request: compare the seventh response control signal with the eighth response control signal; and generate the second error signal in response to the seventh response control signal not being equal to the eighth response control signal.
Costa provides a lockstep architecture in which primary and redundant data paths receive the same request and operate in lockstep, and Costa compares corresponding outputs of the primary and redundant paths to detect errors. Costa further describes this architecture in the context of achieving an automotive safety integrity level (ASIL), where detecting discrepancies between redundant processing paths is used to identify faults. Lee, in turn, discloses that, when a read/write operation is completed, the data storage device provides a complete signal indicating that processing of the command has been completed to the host processor via the bus circuit (Lee [0053]). When the completion signals from the two lockstep paths are considered as corresponding outputs of the respective paths, comparing those signals provides another way to detect a divergence between the paths. For example, if the first path generates a completion signal while the second path does not, the completion signals would not be equal, indicating that the two paths did not complete the corresponding operation in the same manner. Thus, in the combined Costa and Lee system, the fifth and sixth response control signals associated with the corresponding write operations could be compared, and an error could be generated when the signals differ. Likewise, the seventh and eighth response control signals associated with the corresponding read operations could be compared, with a difference between the signals indicating a corresponding fault or divergence between the redundant paths.
It would have been obvious before the effective filing date of the invention to compare the respective completion/response control signals of the primary and redundant paths in the combination of Jin, Lee, and Costa. Costa's lockstep architecture is specifically configured to identify discrepancies between corresponding operations of redundant paths, including by comparing corresponding data and addresses and generating an error when the corresponding outputs differ. Lee's complete signal provides an output indicating whether processing of a command has been completed. Comparing the completion signals would therefore have been a straightforward extension of Costa's existing comparison-based fault-detection scheme to another corresponding output of the redundant paths. Such a comparison would provide an additional indication of whether the two paths remained in agreement during processing and would be particularly consistent with Costa's ASIL-oriented objective of detecting faults in safety-critical processing. If one redundant path completed an operation while the other did not, the unequal completion signals would identify that discrepancy; moreover, such a discrepancy would be consistent with, and potentially provide an independent indication of, a failure that would prevent the two lockstep paths from producing matching results. Accordingly, a person of ordinary skill in the art would have been motivated to compare the corresponding completion signals to improve fault detection and system reliability, with a reasonable expectation that the comparison would operate predictably with Costa's existing lockstep architecture and Lee's completion signaling.
Regarding Claim 26, Costa further discloses wherein the memory controller subsystem is configured to, in response to receiving the read request: compare the third read data forwarded by the first memory controller with the forwarding third read data generated by the second memory controller; and generate a third error signal in response to the third read data forwarded by the first memory controller not being equal to the forwarding third read data generated by the second memory controller. (See 112 rejection above)
“If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B. The primary data path processor 220LP is configured to generate the primary memory read address XPTO_A. The redundant data path processor 220LR is configured to generate the redundant memory read address XPTO_B in lockstep with the primary data path processor 220LP” (Costa [0032])
“The primary copy of the read data XY_A is read from the primary memory 240A and transmitted to the memory dispatcher 220 via the memory controller 230A, and the redundant copy of the read data XY_B is read from the redundant memory 240B and transmitted to the memory dispatcher 220 via the memory controller 230B” (Costa [0033])
“The comparator 226 is configured to compare the primary and redundant copies of the read data XY_A, XY_B. The comparator 226 is also configured to compare the primary and redundant memory read addresses XPTO_A, XPTO_B. If the primary (XPTO_A) and redundant (XPTO_B) memory read addresses differ from what they should be, or the primary (XY_A) and redundant (XY_B) copies of the read data differ, the comparator 116 is configured to generate an error signal” (Costa [0034])
Regarding Claim 29, Jin further discloses wherein the memory controller subsystem is further configured to receive, from the communication system, a request control signal indicating a write or a read.
“The flash controller 220_1 may control the first memory device group 100_1 to perform an operation according to the request of the host 300. The flash controller 220_1 may control the second memory controller 200_2 so that the second memory device group 100_2 performs the operation according to the request of the host 300” (Jin [0114])
“The operation controller 410 may receive a request REQ associated with a write operation, an address ADDR, and data DATA from the host 300. The operation controller 410 may provide data DATA to the host 300 in response to a request REQ associated with a read operation” (Jin [0124])
Claim 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (published June 10, 2021), Lee (published July 22, 2021), and Costa (published October 01, 2020) as applied to claim 26 above, and further in view of Colombo et al. (US 2022/0318109) (hereinafter Colombo) (published October 06, 2022).
Regarding Claim 27, the combination of Jin, Lee, and Costa disclosed the system of claim 26, but does not explicitly state wherein the memory controller subsystem is further configured to assert a first primary error signal in response to the first, second or third error signals being asserted.
Colombo discloses wherein the memory controller subsystem is further configured to assert a first primary error signal in response to the first, second or third error signals being asserted.
“Thus, essentially the signal ET corresponds to a combined error signal determined by combining the error signals ERR as a function of the error trigger enable bits ETE” (Colombo [0032])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to further modify the system in the combination of Jin, Lee, and Costa, and further in view of Colombo to provide a second primary error signal that is asserted in response to assertion of any of the fourth error signal, fifth error signal, third uncorrectable-error signal, or fourth uncorrectable-error signal. By applying Colombo's known error-signal aggregation technique to the error signals generated in the Jin, Lee, and Costa system would therefore provide a common second primary error signal that is asserted when any of the individual error conditions is detected. Such an arrangement would allow the various error conditions identified by the redundant memory controllers and associated error detection and correction circuits to be consolidated into a single error indication without changing the underlying mechanisms that detect the individual errors. The motivation for doing so would have been to simplify error reporting and provide a common error indication for the various fault conditions detected throughout the memory controller subsystem. The combination of Jin, Lee, and Costa produces multiple error indications corresponding to different potential failures, including discrepancies between redundant operations and uncorrectable errors detected by the respective error detection and correction circuits. Colombo demonstrates that combining such individual error signals into a single error signal was a known technique for providing a consolidated indication that an error condition has occurred. Using Colombo's approach would therefore have allowed the system to efficiently communicate the occurrence of any of the relevant error conditions through a common second primary error signal, while retaining the individual error signals for identifying the particular source or type of error.
Claim 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (published June 10, 2021), Lee (published July 22, 2021), and Costa (published October 01, 2020) as applied to claim 24 above, and further in view of KIM et al. (US 2016/0042809) (hereinafter Kim) (published February 11, 2016).
Regarding Claim 28, the combination of Jin, Lee, and Costa disclosed the system of claim 24, but does not explicitly state further comprising: a first error detection and correction circuit coupled between the first memory controller and the communication system, and configured to: generate a first correctable-error signal in response to determining the third read data forwarded by the first memory controller contains a first correctable error; and generate a first uncorrectable-error signal in response to determining the third read data forwarded by the first memory controller contains a first uncorrectable error; a second error detection and correction circuit coupled between the second memory controller and the communication system, and configured to: generate a second correctable-error signal in response to determining the forwarding third read data generated by the second memory controller contains a second correctable error; and generate a second uncorrectable-error signal in response to determining the forwarding third read data generated by the second memory controller contains a second uncorrectable error.
Kim discloses further comprising: a first error detection and correction circuit coupled between the first memory controller and the communication system, and configured to:
“According to some example embodiments, a memory system may include a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device may include a memory cell array, an input/output (I/O) gating circuit, an error check and correction (ECC) circuit and a register unit” (Kim [0025] each memory controller can have its own ECC connected)
generate a first correctable-error signal in response to determining the third read data forwarded by the first memory controller contains a first correctable error; and generate a first uncorrectable-error signal in response to determining the third read data forwarded by the first memory controller contains a first uncorrectable error;
“When the error decision circuit 400 determines the correctability of errors in the test result data TR by the first unit whose size is smaller the size of the codeword CW, in other words when the size of the first unit is smaller the size of the codeword, the first error kind signal EKS1 may also include, but is not limited to the “partial no error” (pNE) code, which means that the number of errors in the first unit is zero, the partial correctable error (pCE) code, which means that the number of errors in the first unit is within the error correction capability of the ECC circuit 360, or the partial uncorrectable error (pUE) code, which means that the number of errors in the first unit exceeds the error correction capability of the ECC circuit 360” (Kim [0096])
a second error detection and correction circuit coupled between the second memory controller and the communication system, and configured to:
“According to some example embodiments, a memory system may include a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device may include a memory cell array, an input/output (I/O) gating circuit, an error check and correction (ECC) circuit and a register unit” (Kim [0025] each memory controller can have its own ECC connected)
generate a second correctable-error signal in response to determining the forwarding third read data generated by the second memory controller contains a second correctable error; and generate a second uncorrectable-error signal in response to determining the forwarding third read data generated by the second memory controller contains a second uncorrectable error.
“When the error decision circuit 400 determines the correctability of errors in the test result data TR by the first unit whose size is smaller the size of the codeword CW, in other words when the size of the first unit is smaller the size of the codeword, the first error kind signal EKS1 may also include, but is not limited to the “partial no error” (pNE) code, which means that the number of errors in the first unit is zero, the partial correctable error (pCE) code, which means that the number of errors in the first unit is within the error correction capability of the ECC circuit 360, or the partial uncorrectable error (pUE) code, which means that the number of errors in the first unit exceeds the error correction capability of the ECC circuit 360” (Kim [0096])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to further modify the system in the combination of Jin, Lee, and Costa, and further in view of Kim to provide respective error detection and correction circuits associated with the first and second memory controllers and their respective read-data paths. By applying Kim's ECC and error-classification functionality to the first and second read-data paths of the system in the combination would therefore provide a first error detection and correction circuit associated with the first memory controller and a second error detection and correction circuit associated with the second memory controller. Each circuit could determine whether read data forwarded by its respective memory controller contains a correctable or uncorrectable error and generate the corresponding correctable-error or uncorrectable-error signal. Providing respective ECC circuits for the two redundant read-data paths would be consistent with Costa's architecture, in which the primary and redundant paths independently process corresponding read operations and their outputs are evaluated for discrepancies. The motivation for doing so would have been to improve the reliability and fault-detection capability of the system in the combination of Jin, Lee, and Costa by detecting and classifying errors in the read data produced by each of the redundant memory paths. Kim demonstrates that ECC circuitry can be used not merely to detect an error, but also to determine whether the detected error is within the correction capability of the ECC circuit or exceeds that capability. Incorporating this known functionality into the respective read-data paths of the system would have allowed the system to distinguish correctable errors from uncorrectable errors on each path and respond appropriately to the detected condition. This would have complemented Costa's lockstep and ASIL-oriented fault-detection architecture by providing additional information concerning the integrity of the data produced by each redundant path.
Claim 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (published June 10, 2021), Lee (published July 22, 2021), and Costa (published October 01, 2020) as applied to claim 24 above, and further in view of Tanaka (published March 05, 2020).
Regarding Claim 30, the combination of Jin, Lee, and Costa disclosed the system of claim 24, but does not explicitly state wherein the first memory controller is further configured to assert a first chip select signal to select the first memory.
Jin and Tanaka discloses wherein the first memory controller is further configured to assert a first chip select signal to select the first memory.
“In FIG. 5, the first memory controller 200_1 is shown as the main controller and the second memory controller 200_2 is shown as the only sub controller” (Jin [0118] the memories are connected to the controllers)
“The memory controller and the memory are connected by using a serial interface such as a Serial Peripheral Interface (SPI). Here, the memory controller operates as a master device, and the memory as a slave device to be controlled by the master device. According to the SPI standard, a master device can select a memory to communicate by asserting a chip select signal, and transmit signals to the selected memory for data read and write” (Tanaka [0003])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system in the combination of Jin, Lee, and Costa, and further in view of Tanaka to implement the communication between the first memory controller and the first memory using an SPI interface. By applying Tanaka's SPI interface to the connection between Jin's first memory controller and first memory would therefore result in the first memory controller operating as an SPI master and asserting a first chip select signal to select the first memory for communication. The first memory controller could then transmit the read and write signals associated with the requested operations to the selected first memory. Such a modification would have been a straightforward application of Tanaka's known SPI interface and chip-select technique to Jin's existing controller-to-memory connection and would have been within the ordinary skill in the art. The motivation for doing so would have been to provide a known and conventional serial communication interface through which Jin's first memory controller could selectively communicate with the first memory. Tanaka teaches that SPI provides a mechanism by which a memory controller operating as a master selects a memory for communication by asserting a chip select signal and then transmits signals to the selected memory for read and write operations. Incorporating the SPI interface into Jin would therefore have provided a predictable mechanism for the first memory controller to select and communicate with its associated first memory. In particular, the first memory controller could assert the first chip select signal when a request is directed to the first memory, thereby ensuring that the first memory is selected to receive the corresponding command and data. The use of Tanaka's SPI interface would thus have provided a known mechanism for carrying out the communication already contemplated by Jin between the first memory controller and first memory, without requiring a change to Jin's underlying address-based allocation or memory-controller architecture.
Claim 31, 32, 36, and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (published June 10, 2021) and Lee (published July 22, 2021) as applied to claim 21 above, and further in view of Tanaka (published March 05, 2020) and Costa (published October 01, 2020).
Regarding Claim 31, the combination of Jin and Lee disclosed the system of claim 21, but does not explicitly state wherein the communication channel is a shared communication channel, wherein the processing system further comprises a selection circuit configured to select the first memory controller exclusive of the second memory controller, and select the second memory controller exclusive of the first memory controller, and, wherein, in a third operating mode: in response to the write request and the first memory controller being selected, the first memory controller is configured to transmit to the first memory a fifth write command comprising the first memory address and the write data, and forward to the communication system a ninth response control signal; in response to the write request and the second memory controller being selected, the second memory controller is configured to transmit to the second memory a sixth write command comprising the first memory address and the write data, and forward to the communication system a tenth response control signal; in response to the read request and the first memory controller being selected, the first memory controller is configured to transmit to the first memory a fifth read command comprising the second memory address, receive from the first memory fourth read data associated with the second memory address, and forward to the communication system the fourth read data and a eleventh response control signal; in response to the read request and the second memory controller being selected, the second memory controller is configured to transmit to the second memory a sixth read command comprising the second memory address, receive from the second memory fifth read data associated with the second memory address, and forward to the communication system the fifth read data and a twelfth response control signal; and the memory controller subsystem is configured to: in response to receiving the write request: compare the ninth response control signal with the tenth response control signal; and generate a fourth error signal in response to the ninth response control signal not being equal to the tenth response control signal; and in response to receiving the read request: compare the eleventh response control signal with the twelfth response control signal; and generate the fourth error signal in response to the eleventh response control signal not being equal to the twelfth response control signal.
Tanaka discloses wherein the communication channel is a shared communication channel, wherein the processing system further comprises a selection circuit configured to select the first memory controller exclusive of the second memory controller, and select the second memory controller exclusive of the first memory controller, and, wherein, in a third operating mode:
“A master device that performs communication in compliance with the SPI standard can be connected with a plurality of memory devices via a bridge device. The master device asserts a chip select signal to the bridge device to notify the bridge device of a start of communication” (Tanaka [0005])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system in the combination of Jin and Lee, and further in view of Tanaka to use an SPI interface as the shared communication channel between the processing system and the first and second memory controllers, with a selection circuit for selectively communicating with one memory controller at a time. Because SPI uses a shared communication channel and chip-select signaling to identify the device with which the master communicates, applying Tanaka's SPI arrangement to Jin would provide a predictable mechanism for selecting the first memory controller exclusive of the second memory controller, or the second memory controller exclusive of the first memory controller. The motivation for doing so would have been to provide an efficient shared communication channel while ensuring that only the selected memory controller communicates with the processing system at a given time. Tanaka's chip-select mechanism provides a known and straightforward way to select a particular device on a shared SPI interface and prevent simultaneous communication with the other device. Applying this arrangement to Jin would therefore reduce the need for separate communication channels and provide orderly, mutually exclusive communication with the first and second memory controllers.
Tanaka, Costa, and Lee discloses in response to the write request and the first memory controller being selected, the first memory controller is configured to transmit to the first memory a fifth write command comprising the first memory address and the write data, and forward to the communication system a ninth response control signal; in response to the write request and the second memory controller being selected, the second memory controller is configured to transmit to the second memory a sixth write command comprising the first memory address and the write data, and forward to the communication system a tenth response control signal;
“According to the SPI standard, a master device can select a memory to communicate by asserting a chip select signal, and transmit signals to the selected memory for data read and write” (Tanaka [0003] to communicate with two controllers would require selecting the controllers sequentially to communicate with them)
“More specifically, if the decoded write address corresponds with a lockstep region of the memory 140, the lockstep processor 124L is configured to generate, based on the decoded write address, primary and redundant memory write addresses XPTO_A, XPTO_B and corresponding primary and redundant copies of the write data XY_A, XY_B in lockstep” (Costa [0021])
“When a read/write operation is completed, the data storage device 300 provides a complete signal indicating that processing of a command has been completed to the host processor 100 via the bus circuit 400” (Lee [0053] with respect to each of the write commands of Costa a respective complete signal is provided)
in response to the read request and the first memory controller being selected, the first memory controller is configured to transmit to the first memory a fifth read command comprising the second memory address, receive from the first memory fourth read data associated with the second memory address, and forward to the communication system the fourth read data and a eleventh response control signal; in response to the read request and the second memory controller being selected, the second memory controller is configured to transmit to the second memory a sixth read command comprising the second memory address, receive from the second memory fifth read data associated with the second memory address, and forward to the communication system the fifth read data and a twelfth response control signal; and
“According to the SPI standard, a master device can select a memory to communicate by asserting a chip select signal, and transmit signals to the selected memory for data read and write” (Tanaka [0003] to communicate with two controllers would require selecting the controllers sequentially to communicate with them)
“If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B. The primary data path processor 220LP is configured to generate the primary memory read address XPTO_A. The redundant data path processor 220LR is configured to generate the redundant memory read address XPTO_B in lockstep with the primary data path processor 220LP” (Costa [0032])
“The primary copy of the read data XY_A is read from the primary memory 240A and transmitted to the memory dispatcher 220 via the memory controller 230A, and the redundant copy of the read data XY_B is read from the redundant memory 240B and transmitted to the memory dispatcher 220 via the memory controller 230B” (Costa [0033])
“When a read/write operation is completed, the data storage device 300 provides a complete signal indicating that processing of a command has been completed to the host processor 100 via the bus circuit 400” (Lee [0053] with respect to each of the read commands of Costa a respective complete signal is provided)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to further modify the system in the combination of Jin, Lee, and Tanaka, and further in view of Costa to provide a lockstep operating mode in which the first and second memory controllers perform corresponding read and write operations for the same request. By incorporating Costa's lockstep processing into the Jin, Lee, and Tanaka system would cause the first and second memory controllers to perform corresponding operations on their respective memories, while Tanaka's already-provided shared SPI communication channel and selection mechanism would allow the controllers to be accessed sequentially. Thus, when the first memory controller is selected, it can transmit the corresponding write or read command to the first memory and, when the second memory controller is selected, it can transmit the corresponding write or read command to the second memory. Lee's completion signaling would provide a respective response control signal upon completion of each operation. The motivation for doing so would have been to improve the reliability and fault-detection capability of the system in the combination by incorporating Costa's known lockstep and redundant processing techniques. Costa provides corresponding primary and redundant operations so that the results of the two paths can be compared to detect errors, including errors in memory addresses and read or write data. Applying this technique to Jin's two memory controllers would allow the controllers to perform corresponding operations on their respective memories while preserving the existing shared SPI communication architecture of Tanaka. The use of Tanaka's selection mechanism would permit the first and second controllers to communicate over the shared channel sequentially, while Costa's lockstep processing would ensure that the corresponding operations remain coordinated.
Costa and Lee further discloses the memory controller subsystem is configured to: in response to receiving the write request: compare the ninth response control signal with the tenth response control signal; and generate a fourth error signal in response to the ninth response control signal not being equal to the tenth response control signal; and in response to receiving the read request: compare the eleventh response control signal with the twelfth response control signal; and generate the fourth error signal in response to the eleventh response control signal not being equal to the twelfth response control signal.
Costa provides a lockstep architecture in which primary and redundant paths receive corresponding requests and perform corresponding read and write operations, and Costa compares corresponding outputs of the paths to detect errors. Lee discloses that, when a read/write operation is completed, a complete signal indicating that processing of the command has been completed is provided to the host processor via the bus circuit (Lee [0053]). Thus, for the corresponding write operations performed by the first and second memory controllers, the respective completion signals provided by Lee correspond to the ninth and tenth response control signals. These signals can be compared to determine whether the two lockstep paths completed the corresponding write operation consistently. If one path provides a completion signal and the other does not, the ninth and tenth response control signals would not be equal, indicating a discrepancy between the two paths and permitting generation of the fourth error signal. Likewise, for the corresponding read operations, the respective completion signals correspond to the eleventh and twelfth response control signals, and a difference between those signals would indicate that the two lockstep paths did not complete the corresponding read operation consistently and would permit generation of the fourth error signal. Such comparison is consistent with Costa's lockstep and ASIL-oriented error-detection architecture, which detects faults by identifying differences between corresponding operations and outputs of the primary and redundant paths.
Regarding Claim 32, Costa further discloses wherein the memory controller subsystem is configured to, in response to receiving the read request: compare the fourth read data forwarded by the first memory controller with the fifth read data forwarded by the second memory controller; and generate a fifth error signal in response to the fourth read data forwarded by the first memory controller not being equal to the fifth read data forwarded by the second memory controller.
“The comparator 226 is configured to compare the primary and redundant copies of the read data XY_A, XY_B. The comparator 226 is also configured to compare the primary and redundant memory read addresses XPTO_A, XPTO_B. If the primary (XPTO_A) and redundant (XPTO_B) memory read addresses differ from what they should be, or the primary (XY_A) and redundant (XY_B) copies of the read data differ, the comparator 116 is configured to generate an error signal” (Costa [0034])
Regarding Claim 36, Jin further discloses wherein the memory controller subsystem is further configured to receive, from the communication system, a request control signal indicating a write or a read.
“The flash controller 220_1 may control the first memory device group 100_1 to perform an operation according to the request of the host 300. The flash controller 220_1 may control the second memory controller 200_2 so that the second memory device group 100_2 performs the operation according to the request of the host 300” (Jin [0114])
“The operation controller 410 may receive a request REQ associated with a write operation, an address ADDR, and data DATA from the host 300. The operation controller 410 may provide data DATA to the host 300 in response to a request REQ associated with a read operation” (Jin [0124])
Regarding Claim 37, Jin and Tanaka further discloses wherein: the first memory controller is further configured to assert a first chip select signal to select the first memory; and the second memory controller is further configured to assert a second chip select signal to select the second memory.
“In FIG. 5, the first memory controller 200_1 is shown as the main controller and the second memory controller 200_2 is shown as the only sub controller” (Jin [0118] the memories are connected to the controllers)
“The memory controller and the memory are connected by using a serial interface such as a Serial Peripheral Interface (SPI). Here, the memory controller operates as a master device, and the memory as a slave device to be controlled by the master device. According to the SPI standard, a master device can select a memory to communicate by asserting a chip select signal, and transmit signals to the selected memory for data read and write” (Tanaka [0003])
Claim 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (published June 10, 2021), Lee (published July 22, 2021), Tanaka (published March 05, 2020), and Costa (published October 01, 2020) as applied to claim 32 above, and further in view of Kim (published February 11, 2016).
Regarding Claim 33, the combination of Jin, Lee, Tanaka, and Costa disclosed the system of claim 32, but does not explicitly state further comprising: a third error detection and correction circuit coupled between the first memory controller and the communication system, and configured to: generate a third correctable-error signal in response to determining the fourth read data forwarded by the first memory controller contains a third correctable error; and generate a third uncorrectable-error signal in response to determining the fourth read data forwarded by the first memory controller contains a third uncorrectable error; and a fourth error detection and correction circuit coupled between the second memory controller and the communication system, and configured to: generate a fourth correctable-error signal in response to determining the fifth read data generated by the second memory controller contains a fourth correctable error; and generate a fourth uncorrectable-error signal in response to determining the fifth read data generated by the second memory controller contains a fourth uncorrectable error.
Kim discloses further comprising: a third error detection and correction circuit coupled between the first memory controller and the communication system, and configured to:
“According to some example embodiments, a memory system may include a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device may include a memory cell array, an input/output (I/O) gating circuit, an error check and correction (ECC) circuit and a register unit” (Kim [0025] each memory controller can have its own ECC connected)
generate a third correctable-error signal in response to determining the fourth read data forwarded by the first memory controller contains a third correctable error; and generate a third uncorrectable-error signal in response to determining the fourth read data forwarded by the first memory controller contains a third uncorrectable error; and
“When the error decision circuit 400 determines the correctability of errors in the test result data TR by the first unit whose size is smaller the size of the codeword CW, in other words when the size of the first unit is smaller the size of the codeword, the first error kind signal EKS1 may also include, but is not limited to the “partial no error” (pNE) code, which means that the number of errors in the first unit is zero, the partial correctable error (pCE) code, which means that the number of errors in the first unit is within the error correction capability of the ECC circuit 360, or the partial uncorrectable error (pUE) code, which means that the number of errors in the first unit exceeds the error correction capability of the ECC circuit 360” (Kim [0096])
a fourth error detection and correction circuit coupled between the second memory controller and the communication system, and configured to:
“According to some example embodiments, a memory system may include a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device may include a memory cell array, an input/output (I/O) gating circuit, an error check and correction (ECC) circuit and a register unit” (Kim [0025] each memory controller can have its own ECC connected)
generate a fourth correctable-error signal in response to determining the fifth read data generated by the second memory controller contains a fourth correctable error; and generate a fourth uncorrectable-error signal in response to determining the fifth read data generated by the second memory controller contains a fourth uncorrectable error.
“When the error decision circuit 400 determines the correctability of errors in the test result data TR by the first unit whose size is smaller the size of the codeword CW, in other words when the size of the first unit is smaller the size of the codeword, the first error kind signal EKS1 may also include, but is not limited to the “partial no error” (pNE) code, which means that the number of errors in the first unit is zero, the partial correctable error (pCE) code, which means that the number of errors in the first unit is within the error correction capability of the ECC circuit 360, or the partial uncorrectable error (pUE) code, which means that the number of errors in the first unit exceeds the error correction capability of the ECC circuit 360” (Kim [0096])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to further modify the system in the combination of Jin, Lee, Tanaka, and Costa, and further in view of Kim to provide respective error detection and correction circuits associated with the first and second memory controllers and their respective read-data paths. By applying Kim's ECC and error-classification functionality to the first and second read-data paths of the system in the combination would therefore provide a first error detection and correction circuit associated with the first memory controller and a second error detection and correction circuit associated with the second memory controller. Each circuit could determine whether read data forwarded by its respective memory controller contains a correctable or uncorrectable error and generate the corresponding correctable-error or uncorrectable-error signal. Providing respective ECC circuits for the two redundant read-data paths would be consistent with Costa's architecture, in which the primary and redundant paths independently process corresponding read operations and their outputs are evaluated for discrepancies. The motivation for doing so would have been to improve the reliability and fault-detection capability of the system in the combination of Jin, Lee, Tanaka, and Costa by detecting and classifying errors in the read data produced by each of the redundant memory paths. Kim demonstrates that ECC circuitry can be used not merely to detect an error, but also to determine whether the detected error is within the correction capability of the ECC circuit or exceeds that capability. Incorporating this known functionality into the respective read-data paths of the system would have allowed the system to distinguish correctable errors from uncorrectable errors on each path and respond appropriately to the detected condition. This would have complemented Costa's lockstep and ASIL-oriented fault-detection architecture by providing additional information concerning the integrity of the data produced by each redundant path.
Claim 34 and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (published June 10, 2021), Lee (published July 22, 2021), Tanaka (published March 05, 2020), Costa (published October 01, 2020) and Kim (published February 11, 2016) as applied to claim 33 above, and further in view of Colombo (published October 06, 2022).
Regarding Claim 33, the combination of Jin, Lee, Tanaka, and Costa disclosed the system of claim 32, but does not explicitly state wherein the memory controller subsystem is further configured to assert a second primary error signal in response to the fourth error signal, the fifth error signal, the third uncorrectable-error signal, or the fourth uncorrectable-error signal being asserted.
Colombo discloses wherein the memory controller subsystem is further configured to assert a second primary error signal in response to the fourth error signal, the fifth error signal, the third uncorrectable-error signal, or the fourth uncorrectable-error signal being asserted.
“Thus, essentially the signal ET corresponds to a combined error signal determined by combining the error signals ERR as a function of the error trigger enable bits ETE” (Colombo [0032])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to further modify the system in the combination of Jin, Lee, Tanaka, and Costa, and further in view of Colombo to provide a second primary error signal that is asserted in response to assertion of any of the fourth error signal, fifth error signal, third uncorrectable-error signal, or fourth uncorrectable-error signal. By applying Colombo's known error-signal aggregation technique to the error signals generated in the Jin, Lee, Tanaka, and Costa system would therefore provide a common second primary error signal that is asserted when any of the individual error conditions is detected. Such an arrangement would allow the various error conditions identified by the redundant memory controllers and associated error detection and correction circuits to be consolidated into a single error indication without changing the underlying mechanisms that detect the individual errors. The motivation for doing so would have been to simplify error reporting and provide a common error indication for the various fault conditions detected throughout the memory controller subsystem. The combination of Jin, Lee, Tanaka, and Costa produces multiple error indications corresponding to different potential failures, including discrepancies between redundant operations and uncorrectable errors detected by the respective error detection and correction circuits. Colombo demonstrates that combining such individual error signals into a single error signal was a known technique for providing a consolidated indication that an error condition has occurred. Using Colombo's approach would therefore have allowed the system to efficiently communicate the occurrence of any of the relevant error conditions through a common second primary error signal, while retaining the individual error signals for identifying the particular source or type of error.
Regarding Claim 34, the combination of Jin, Lee, Tanaka, and Costa disclosed the system of claim 32, but does not explicitly state wherein the memory controller subsystem is further configured to assert a third primary error signal in response to the third or fourth correctable-error signals being asserted.
Colombo discloses wherein the memory controller subsystem is further configured to assert a third primary error signal in response to the third or fourth correctable-error signals being asserted.
“Thus, essentially the signal ET corresponds to a combined error signal determined by combining the error signals ERR as a function of the error trigger enable bits ETE” (Colombo [0032])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to further modify the system in the combination of Jin, Lee, Tanaka, and Costa, and further in view of Colombo to provide a second primary error signal that is asserted in response to assertion of any of the fourth error signal, fifth error signal, third uncorrectable-error signal, or fourth uncorrectable-error signal. By applying Colombo's known error-signal aggregation technique to the error signals generated in the Jin, Lee, Tanaka, and Costa system would therefore provide a common second primary error signal that is asserted when any of the individual error conditions is detected. Such an arrangement would allow the various error conditions identified by the redundant memory controllers and associated error detection and correction circuits to be consolidated into a single error indication without changing the underlying mechanisms that detect the individual errors. The motivation for doing so would have been to simplify error reporting and provide a common error indication for the various fault conditions detected throughout the memory controller subsystem. The combination of Jin, Lee, Tanaka, and Costa produces multiple error indications corresponding to different potential failures, including discrepancies between redundant operations and uncorrectable errors detected by the respective error detection and correction circuits. Colombo demonstrates that combining such individual error signals into a single error signal was a known technique for providing a consolidated indication that an error condition has occurred. Using Colombo's approach would therefore have allowed the system to efficiently communicate the occurrence of any of the relevant error conditions through a common second primary error signal, while retaining the individual error signals for identifying the particular source or type of error.
Claims 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa (published October 01, 2020) in view of Lee (published July 22, 2021).
Regarding Claim 39, Costa discloses a method of operating a processing system integrated in an integrated circuit, the processing system comprising a communication system, a memory controller subsystem comprising first and second memory controllers and connected to a communication channel connected to terminals of the integrated circuit connected to a first memory external to the integrated circuit, and a master circuit, the method comprising, in a second operating mode:
“The MCU comprises a computation unit 110, a memory dispatcher 120, and a memory controller 130” (Costa [0014] the communication system is the bus/network connected to MCU used for receiving the read and writes)
“The memory controller 130 comprises a memory controller 130A and a memory controller 130B. The memory controller 130 may be, for example, a Dynamic Random Access Memory (DRAM) controller or a Direct Memory Access (DMA) controller” (Costa [0016] the paths connecting the memory controller to the memory is the communication channel)
“The memory 140 comprises a memory 140A and a memory 140B. Each of the memory 140A and memory 140B may be referred to as a channel. The memory 140A is written using memory controller 130A, and the memory 140B is written using memory controller 130B. The memory 140A and the memory 140B may be physically separate memories, or alternatively, separate areas of a same physical memory. The memory 140 may by an external DRAM memory, though the disclosure is not limited in these respects. The memory 140 may be external or internal, and/or may be any memory type (e.g., flash) as suitable” (Costa [0017])
receiving, by the memory controller subsystem from the communication system, a write request comprising a first memory address and write data;
“The address decoder 122 receives a single logical write address XPTO and write data XY. The received write data XY has an integrity level ASIL-D. The address decoder 122 is configured to decode the logical write address XPTO” (Costa [0019])
in response to receiving the write request: transmitting, by the first memory controller to the first memory, a first write command comprising the first memory address and the write data; generating, by the second memory controller, a second write command comprising the write data;
“More specifically, if the decoded write address corresponds with a lockstep region of the memory 140, the lockstep processor 124L is configured to generate, based on the decoded write address, primary and redundant memory write addresses XPTO_A, XPTO_B and corresponding primary and redundant copies of the write data XY_A, XY_B in lockstep” (Costa [0021])
“As shown in FIG. 1B, the lockstep processor 124L comprises a primary data path processor 124LP and a redundant data path processor 124LR. The address XPTO and data XY arrive from one path to both the primary data path processor 124LP and the redundant data path processor 114LR, which operate in lockstep. The primary data path processor 124LP generates the primary memory write address XPTO_A and the primary copy of the write data XY_A. The redundant data path processor 114LR generates the redundant memory write address XPTO_B and the redundant copy of the write data XY_B in lockstep with the primary data path processor 114LP” (Costa [0022])
comparing, by the memory controller subsystem, the write data transmitted by the first memory controller with the write data generated by the second memory controller; and generating, by the memory controller subsystem, a first error signal in response to the write data transmitted by the first memory controller not being equal to the write data generated by the second memory controller;
“The comparator 126 is configured to compare the primary and redundant copies of the write data XY_A, XY_B. The comparator 126 is also configured to compare the primary and redundant memory write addresses XPTO_A, XPTO_B. This comparison is to determine if there are any errors before the data is written in the memory 140. If the primary (XPTO_A) and redundant (XPTO_B) memory write addresses differ from what they should be, or the primary (XY_A) and redundant (XY_B) copies of the write data differ, the comparator 116 is configured to generate an error signal” (Costa [0024])
receiving, by the memory controller subsystem from the communication system, a read request comprising a second memory address; and
“The address decoder 222 receives a single logical read address XPTO. The address decoder is configured to decode a logical read address XPTO” (Costa [0031])
in response to receiving the read request: transmitting, by the first memory controller to the first memory, a first read command comprising the second memory address, receiving, by the first memory controller from the first memory, read data associated with the second memory address, and forwarding, by the first memory controller to the communication system, the read data; receiving, by the second memory controller from the first memory, the read data associated with the second memory address, and generating, by the second memory controller, forwarding read data; (see 112 rejections above)
“If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B. The primary data path processor 220LP is configured to generate the primary memory read address XPTO_A. The redundant data path processor 220LR is configured to generate the redundant memory read address XPTO_B in lockstep with the primary data path processor 220LP” (Costa [0032])
“The primary copy of the read data XY_A is read from the primary memory 240A and transmitted to the memory dispatcher 220 via the memory controller 230A, and the redundant copy of the read data XY_B is read from the redundant memory 240B and transmitted to the memory dispatcher 220 via the memory controller 230B” (Costa [0033])
comparing, by the memory controller subsystem, the read data received by the first memory controller with the read data received by the second memory controller; and generating, by the memory controller subsystem, a second error signal in response to the read data received by the first memory controller not being equal to the read data received by the second memory controller. (see 112 rejections above)
“The comparator 226 is configured to compare the primary and redundant copies of the read data XY_A, XY_B. The comparator 226 is also configured to compare the primary and redundant memory read addresses XPTO_A, XPTO_B. If the primary (XPTO_A) and redundant (XPTO_B) memory read addresses differ from what they should be, or the primary (XY_A) and redundant (XY_B) copies of the read data differ, the comparator 116 is configured to generate an error signal” (Costa [0034])
But does not explicitly state forwarding, by the first memory controller to the communication system, a first response control signal; generating, by the second memory controller, a second response control signal; forwarding, by the first memory controller to the communication system a third response control signal; generating, by the second memory controller, forwarding a fourth response control signal.
Lee discloses forwarding, by the first memory controller to the communication system, a first response control signal; generating, by the second memory controller, a second response control signal; forwarding, by the first memory controller to the communication system a third response control signal; generating, by the second memory controller, forwarding a fourth response control signal
“When a read/write operation is completed, the data storage device 300 provides a complete signal indicating that processing of a command has been completed to the host processor 100 via the bus circuit 400” (Lee [0053] with respect to each of the write/read commands of Costa a respective complete signal is provided)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system of Costa in view of Lee to provide, for each of the write and read operations performed by the first and second memory controllers, a respective response control signal that is forwarded to the communication system. By applying Lee's completion signaling to Costa’s request-processing architecture would have resulted in the first and second memory controllers providing corresponding response control signals for their respective write and read operations and forwarding those signals through the communication system. Such a modification would have involved the use of known signaling functionality for its known purpose and would have been within the ordinary skill in the art. The motivation for doing so would have been to provide the host with an explicit indication of the status or completion of each command issued to the memory controller subsystem, thereby allowing the host to determine when a requested operation has been processed and, where applicable, when the associated read data is available. Lee demonstrates that providing a completion signal to a host processor upon completion of command processing was a known technique for coordinating communication between a host and a data storage device. Incorporating such signaling into Jin would have improved the coordination and synchronization between the host and the memory controller subsystem, particularly where different memory controllers selectively process requests according to different address ranges. The combination also would have provided a predictable and straightforward way for the host to distinguish completion of operations directed to the respective memory devices without changing Jin's basic address-based allocation of requests or its underlying memory-controller architecture.
Claims 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa (published October 01, 2020) in view of Tanaka (published March 05, 2020) and Lee (published July 22, 2021).
Regarding Claim 40, Costa discloses a method of operating a processing system integrated in an integrated circuit, the processing system comprising a communication system, a memory controller subsystem comprising first and second memory controllers and connected to a communication channel connected to terminals of the integrated circuit connected to first and second memories external to the integrated circuit, a master circuit, and a selection circuit, the method comprising, in a third operating mode:
“The MCU comprises a computation unit 110, a memory dispatcher 120, and a memory controller 130” (Costa [0014] the communication system is the bus/network connected to MCU used for receiving the read and writes)
“The memory controller 130 comprises a memory controller 130A and a memory controller 130B. The memory controller 130 may be, for example, a Dynamic Random Access Memory (DRAM) controller or a Direct Memory Access (DMA) controller” (Costa [0016] the paths connecting the memory controller to the memory is the communication channel)
“The memory 140 comprises a memory 140A and a memory 140B. Each of the memory 140A and memory 140B may be referred to as a channel. The memory 140A is written using memory controller 130A, and the memory 140B is written using memory controller 130B. The memory 140A and the memory 140B may be physically separate memories, or alternatively, separate areas of a same physical memory. The memory 140 may by an external DRAM memory, though the disclosure is not limited in these respects. The memory 140 may be external or internal, and/or may be any memory type (e.g., flash) as suitable” (Costa [0017])
receiving, by the memory controller subsystem from the communication system, a write request comprising a first memory address and write data;
“The address decoder 122 receives a single logical write address XPTO and write data XY. The received write data XY has an integrity level ASIL-D. The address decoder 122 is configured to decode the logical write address XPTO” (Costa [0019])
transmitting, by the first memory controller to the first memory, a first write command comprising the first memory address and the write data; transmitting, by the second memory controller to the second memory, a second write command comprising the first memory address and the write data;
“More specifically, if the decoded write address corresponds with a lockstep region of the memory 140, the lockstep processor 124L is configured to generate, based on the decoded write address, primary and redundant memory write addresses XPTO_A, XPTO_B and corresponding primary and redundant copies of the write data XY_A, XY_B in lockstep” (Costa [0021])
“As shown in FIG. 1B, the lockstep processor 124L comprises a primary data path processor 124LP and a redundant data path processor 124LR. The address XPTO and data XY arrive from one path to both the primary data path processor 124LP and the redundant data path processor 114LR, which operate in lockstep. The primary data path processor 124LP generates the primary memory write address XPTO_A and the primary copy of the write data XY_A. The redundant data path processor 114LR generates the redundant memory write address XPTO_B and the redundant copy of the write data XY_B in lockstep with the primary data path processor 114LP” (Costa [0022])
receiving, by the memory controller subsystem from the communication system, a read request comprising a second memory address;
“The address decoder 222 receives a single logical read address XPTO. The address decoder is configured to decode a logical read address XPTO” (Costa [0031])
transmitting, by the first memory controller to the first memory, a first read command comprising the second memory address, receiving, by the first memory controller from the first memory, first read data associated with the second memory address, and forwarding, by the first memory controller to the communication system, the first read data; transmitting, by the second memory controller to the second memory, a second read command comprising the second memory address, receiving, by the second memory controller from the second memory, second read data associated with the second memory address, and forwarding, by the second memory controller to the communication system, the second read data;
“If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B. The primary data path processor 220LP is configured to generate the primary memory read address XPTO_A. The redundant data path processor 220LR is configured to generate the redundant memory read address XPTO_B in lockstep with the primary data path processor 220LP” (Costa [0032])
“The primary copy of the read data XY_A is read from the primary memory 240A and transmitted to the memory dispatcher 220 via the memory controller 230A, and the redundant copy of the read data XY_B is read from the redundant memory 240B and transmitted to the memory dispatcher 220 via the memory controller 230B” (Costa [0033])
But does not explicitly state selecting, by the selection circuit, the first memory controller exclusive of the second memory controller; in response to the write request and the first memory controller being selected, and forwarding, by the first memory controller to the communication system, a first response control signal; selecting, by the selection circuit, the second memory controller exclusive of the first memory controller; in response to the write request and the second memory controller being selected, and forwarding, by the second memory controller to the communication system, a second response control signal; comparing, by the memory controller subsystem, the first response control signal with the second response control signal; and generating, by the memory controller subsystem, a first error signal in response to the first response control signal not being equal to the second response control signal; selecting, by the selection circuit, the first memory controller exclusive of the second memory controller; in response to the read request and the first memory controller being selected,
forwarding, by the first memory controller to the communication system a third response control signal;
selecting, by the selection circuit, the second memory controller exclusive of the first memory controller; in response to the read request and the second memory controller being selected,
forwarding, by the second memory controller to the communication system a fourth response control signal; comparing, by the memory controller subsystem, the third response control signal with the fourth response control signal; and generating, by the memory controller subsystem, the first error signal in response to the third response control signal not being equal to the fourth response control signal.
Tanaka discloses selecting, by the selection circuit, the first memory controller exclusive of the second memory controller; in response to the write request and the first memory controller being selected, and selecting, by the selection circuit, the second memory controller exclusive of the first memory controller; in response to the write request and the second memory controller being selected, and selecting, by the selection circuit, the first memory controller exclusive of the second memory controller; in response to the read request and the first memory controller being selected, selecting, by the selection circuit, the second memory controller exclusive of the first memory controller; in response to the read request and the second memory controller being selected,
“The memory controller and the memory are connected by using a serial interface such as a Serial Peripheral Interface (SPI). Here, the memory controller operates as a master device, and the memory as a slave device to be controlled by the master device. According to the SPI standard, a master device can select a memory to communicate by asserting a chip select signal, and transmit signals to the selected memory for data read and write” (Tanaka [0003] SPI interface can only communicate with one device at a time and the selection of devices to communicate with would happen sequentially)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system in Costa in view of Tanaka to use an SPI interface as the shared communication channel between the processing system and the first and second memory controllers, with a selection circuit for selectively communicating with one memory controller at a time. Because SPI uses a shared communication channel and chip-select signaling to identify the device with which the master communicates, applying Tanaka's SPI arrangement to Jin would provide a predictable mechanism for selecting the first memory controller exclusive of the second memory controller, or the second memory controller exclusive of the first memory controller. The motivation for doing so would have been to provide an efficient shared communication channel while ensuring that only the selected memory controller communicates with the processing system at a given time. Tanaka's chip-select mechanism provides a known and straightforward way to select a particular device on a shared SPI interface and prevent simultaneous communication with the other device. Applying this arrangement to Jin would therefore reduce the need for separate communication channels and provide orderly, mutually exclusive communication with the first and second memory controllers.
Lee discloses forwarding, by the first memory controller to the communication system, a first response control signal; forwarding, by the second memory controller to the communication system, a second response control signal; forwarding, by the first memory controller to the communication system a third response control signal; forwarding, by the second memory controller to the communication system a fourth response control signal;
“When a read/write operation is completed, the data storage device 300 provides a complete signal indicating that processing of a command has been completed to the host processor 100 via the bus circuit 400” (Lee [0053] with respect to each of the write/read commands of Jin a respective complete signal is provided)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to modify the system in the combination of Costa and Tanaka, and further in view of Lee to provide, for each of the write and read operations performed by the first and second memory controllers, a respective response control signal that is forwarded to the communication system. By applying Lee's completion signaling to the request-processing architecture in the system of the combination would have resulted in the first and second memory controllers providing corresponding response control signals for their respective write and read operations and forwarding those signals through the communication system. Such a modification would have involved the use of known signaling functionality for its known purpose and would have been within the ordinary skill in the art. The motivation for doing so would have been to provide the host with an explicit indication of the status or completion of each command issued to the memory controller subsystem, thereby allowing the host to determine when a requested operation has been processed and, where applicable, when the associated read data is available. Lee demonstrates that providing a completion signal to a host processor upon completion of command processing was a known technique for coordinating communication between a host and a data storage device. Incorporating such signaling into Jin would have improved the coordination and synchronization between the host and the memory controller subsystem, particularly where different memory controllers selectively process requests according to different address ranges. The combination also would have provided a predictable and straightforward way for the host to distinguish completion of operations directed to the respective memory devices without changing Jin's basic address-based allocation of requests or its underlying memory-controller architecture.
Costa and Lee further discloses comparing, by the memory controller subsystem, the first response control signal with the second response control signal; and generating, by the memory controller subsystem, a first error signal in response to the first response control signal not being equal to the second response control signal; comparing, by the memory controller subsystem, the third response control signal with the fourth response control signal; and generating, by the memory controller subsystem, the first error signal in response to the third response control signal not being equal to the fourth response control signal.
Costa provides a lockstep architecture in which primary and redundant paths receive corresponding requests and perform corresponding read and write operations, and Costa compares corresponding outputs of the paths to detect errors. Lee discloses that, when a read/write operation is completed, a complete signal indicating that processing of the command has been completed is provided to the host processor via the bus circuit (Lee [0053]). Thus, for the corresponding write operations performed by the first and second memory controllers, the respective completion signals provided by Lee correspond to the ninth and tenth response control signals. These signals can be compared to determine whether the two lockstep paths completed the corresponding write operation consistently. If one path provides a completion signal and the other does not, the ninth and tenth response control signals would not be equal, indicating a discrepancy between the two paths and permitting generation of the fourth error signal. Likewise, for the corresponding read operations, the respective completion signals correspond to the eleventh and twelfth response control signals, and a difference between those signals would indicate that the two lockstep paths did not complete the corresponding read operation consistently and would permit generation of the fourth error signal. Such comparison is consistent with Costa's lockstep and ASIL-oriented error-detection architecture, which detects faults by identifying differences between corresponding operations and outputs of the primary and redundant paths.
Response to Arguments
Claim Objection
Applicant’s arguments, see page 15 of remarks, filed June 18, 2026, with respect to claim 13 have been fully considered and are persuasive. The claim objection of claim 13 has been withdrawn.
Section 102/103, and Section 112(b) Rejections
Applicant’s arguments, see page 15, filed June 18, 2023, with respect to claims 1-20 have been fully considered and are persuasive. The rejections of claims 1-20 has been withdrawn.
Claims 21–40 are newly presented claims that incorporate limitations from previously pending claims while introducing additional limitations, removing limitation, and resulting complications. Accordingly, these claims necessitate new rejections under 35 U.S.C. § 112, as well as consideration of additional prior art rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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