DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 05, 2024 is/are in compliance with the provisional of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 13 is objected to because of the following informalities: in the second to last line of the claim it states “assertign a fifth error signal”. Examiner believes this a typographical error and should instead be “asserting a fifth error signal”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites multiple operations of the inventions that appears to be mutually exclusive and disclosed in paragraphs [0094]-[0136] and Figures 7, 8, 9, and 10. On the bottom of the first page of the claims the section starting with “in response to receiving the write request” corresponds to Figure 7; on the top of the second page of claims the section starting with “in response to receiving a read request” corresponds to Figure 8; on the middle of the second page the section starting with “in response to receiving from the communication system the write request” corresponds to Figure 9; and on the top of the third page the section starting with “in response to receiving from the communication system the read request” corresponds to Figure 10.
It is unclear how each of these operations are generating the same first or second data signal when the data signals include different information and it does not appear to be same data signals across the different operations. Each of the operations appears to be generating different data signals that uses the communication channel to transmit and/or receive data from the memory. Examiner suggests amending the claims by using more identifiers to distinguish between the different data signals. For example, keep “first data signal” and “second data signal” when referring to the operation of Figure 7, use “third data signal” and “fourth data signal” when referring to the operation of Figure 8, use “fifth data signal” and “sixth data signal” when referring to the operation of Figure 9, use “seventh data signal” and “eighth data signal” when referring to the operation of Figure 10.
It is also unclear as to which data signals it is being compared or received in the last two limitation of the claim. The two limitations recites “in response to determining that the first memory controller transmits the extracted memory address via the first data signal …” and “in response to determining that the first memory controller receives the respective data via the first data signal …”. There are multiple recitations of first and second data signals being generated in different operations recited within the claims and is unclear as to which of these data signals is the limitations referring to. The above suggestion in amending the claims would help clarify this deficiency. For examination purposes examiner will these data signals as the ones with respect to Figure 10.
Furthermore this clarification necessary because the limitation then further requires “compare the first data signal with the second data signal” and “connect the first data signal to the second data signal”. In the first two parts of the claims when referring to Figure 7 and 8, the claims recites “generating respective a first or second data signal”, this requires just the generation of one data signal and in the last two limitation of the claims if referring back to these two first and second data signals would render the invention inoperable since one of the data signals would not be present and it requires both data signals to perform the comparing or connecting steps.
Claim 11 is a method claim with similar limitations to claim 1 with respect to Figures 9 and 10 and would have the same problems as described above.
Claims 2, 4, 12 and 14 refer to another operating mode and the generation of the same first and second data signals and therefore would have the same problems as described above.
Claims 2-10 and 12-20 depends on claim 1 and 11 respectively and inherits these deficiencies.
Claims 1, 2, 4, 7, 11, 12, 14, and 17, recites on the second page of the claims the limitation states “in response to receiving a read request”; on the fourth page of the claims the limitation states “in response to receiving from the communication system a write request” and “in response to receiving from the communication system a read request”; on the fifth and sixth pages of the claims the limitation states “in response to receiving from the communication system a write request” and “in response to receiving from the communication system a read request”; on the seventh and eighth pages of the claims the limitation states “in response to receiving a write request” and “in response to receiving a read request”; on the ninth page of the claims the limitation states “in response to receiving from the communication system a write request” and “in response to receiving from the communication system a read request”; on the tenth and eleventh pages of the claims the limitation states “in response to receiving from the communication system a write request” and “in response to receiving from the communication system a read request”; on the twelfth and thirteenth pages of the claims the limitation states “in response to receiving from the communication system a write request” and “in response to receiving from the communication system a read request”; and on the fourteenth page of the claims the limitation states “in response to receiving a write request” and “in response to receiving a read request” respectively.
There is a prior limitation that recites “receive a write or read request comprising …” in claim 1 or “sending, by the master circuit, write and read requests via the communication system …” in claim 11. It is unclear whether the above limitations are dependent upon the prior recitation or another instance of a writes and reads. Examiner suggests the use of extra identifiers such as first, second, third, etc. to help distinguish the different write and read requests. Since the claim appears to have multiple modes of operations each referencing write and read requests, for examination purposes examiner will treat these write and read requests as different write and read request.
Claims 3, 5, 6, 8-10, 13, 15, 16, and 18-20 depends on 1, 2, 4, 7, 11, 12, 14, and 17 and inherits these deficiencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Costa et al. (US 2020/0310683) (hereinafter Costa) (published October 01, 2020).
Regarding Claim 11, Costa discloses a method of operating a processing system integrated in an integrated circuit, the processing system comprising a communication system, a memory controller subsystem comprising first and second memory controllers and connected to a communication channel comprising a data signal and connected to terminals of the integrated circuit connected to a memory external to the integrated circuit, and a master circuit, the method comprising, in a first operating mode:
“the lockstep mode system 100A has a memory dispatcher 120 for writing data to a memory 140 in lockstep mode. The lockstep mode is for data requiring a high integrity level (e.g., ASIL-D). The memory dispatcher 120 duplicates the data and corresponding write address to write the original and duplicate data in two respective memories 140A, 140B without processing unit intervention” (Costa [0012] see Fig. 1A)
sending, by the master circuit, write and read requests via the communication system to the memory controller subsystem to store data to and read data from the memory;
“If the decoded write address corresponds with a lockstep region of the memory 140, the lockstep processor 124L performs the processing and provides a higher integrity level, such as ASIL-D, by generating primary and redundant copies of the data XY and addresses XPTO in lockstep” (Costa [0020] see Fig. 1A lockstep processor send write commands to memory controller 130)
“If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B” (Costa [0032] see Fig. 2A lockstep processor send read commands to memory controller 230)
connecting the first memory controller to the communication channel, a first data signal corresponding to the data signal;
“The lockstep mode system 100A comprises a MCU coupled to an external memory 140” (Costa [0013] see Fig. 1A and 2A the path connecting the memory controller and the memory is the communication channel)
in response to receiving from the communication system a write request: forwarding the received write request to the first memory controller and the second memory controller, wherein the first memory controller generates the respective first data signal used to transmit a respective extracted memory address and respective extracted data and the second memory controller generates a respective second data signal used to transmit the respective extracted memory address and the respective extracted data; and
“More specifically, if the decoded write address corresponds with a lockstep region of the memory 140, the lockstep processor 124L is configured to generate, based on the decoded write address, primary and redundant memory write addresses XPTO_A, XPTO_B and corresponding primary and redundant copies of the write data XY_A, XY_B in lockstep. Each of the primary and redundant copies of the write data XY_A, XY_B have an integrity level ASIL-B, but together in lockstep they have an integrity level ASIL-D” (Costa [0021] see Fig. 1A, processor forwards write request to controllers 130A and 130B which then generates a signal to the memories 140A and 140B)
comparing the first data signal with the second data signal and, in response to determining that the first data signal does not correspond to the second data signal, asserting a first error signal;
“The comparator 126 is configured to compare the primary and redundant copies of the write data XY_A, XY_B. The comparator 126 is also configured to compare the primary and redundant memory write addresses XPTO_A, XPTO_B. This comparison is to determine if there are any errors before the data is written in the memory 140” (Costa [0024])
The limitation “in response to determining that the first data signal …” is a contingent limitation. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. (see MPEP 2111.04)
In the claim, there is no explicit determining step. A suggested amendment would be the removal of the “in response to” in the limitation, thereby having a determining step that positively recites of the condition being met.
in response to receiving from the communication system a read request: forwarding the received read request to the first memory controller and the second memory controller, wherein the first memory controller generates the respective first data signal used to transmit the respective extracted memory address and receive the respective data associated with the respective extracted memory address and the second memory controller generates the respective second data signal used to transmit the respective extracted memory address and receive the respective data associated with the respective extracted memory address, and the first memory controller generates the respective response comprising the respective received data and the second memory controller generates the respective response comprising the respective received data;
“If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B” (Costa [0032] see Fig. 2A lockstep processor send read commands to memory controller 230)
“Each of the memory controllers 230A, 230B is configured to generate, from the decoded logical read addresses XPTO_A, XPTO_B, a physical address of the memory 140 and initiate a memory read cycle. The primary copy of the read data XY_A is read from the primary memory 240A and transmitted to the memory dispatcher 220 via the memory controller 230A, and the redundant copy of the read data XY_B is read from the redundant memory 240B and transmitted to the memory dispatcher 220 via the memory controller 230B” (Costa [0033])
in response to determining that the first memory controller transmits the extracted memory address via the first data signal, comparing the first data signal with the second data signal and, in response to determining that the first data signal does not correspond to the second data signal, asserting a second error signal; and
“The comparator 226 is configured to compare the primary and redundant copies of the read data XY_A, XY_B. The comparator 226 is also configured to compare the primary and redundant memory read addresses XPTO_A, XPTO_B” (Costa [0034])
The limitations “in response to determining that the first memory controller transmits …” and “in response to determining that the first data signal …” are contingent limitations. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. (see MPEP 2111.04)
In the claim, there are no explicit determining steps or transmitting steps. A suggested amendment would be the removal of the “in response to” in the limitation, thereby having a determining step that positively recites of the condition being met.
in response to determining that the first memory controller receives the respective data via the first data signal, connecting the first data signal to the second data signal, comparing a first response generated by the first memory controller with a second response generated by the second memory controller and, in response to determining that the first response does not correspond to the second response, asserting a third error signal.
The limitations “in response to determining that the first memory controller receives …” and “in response to determining that the first data signal …” are contingent limitations. The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. (see MPEP 2111.04)
In the claim, there are no explicit determining steps or receiving steps. A suggested amendment would be the removal of the “in response to” in the limitation, thereby having a determining step that positively recites of the condition being met.
Regarding Claim 12, Claim 11 recites that the method is in a first operating mode, and claim 12 recites steps of a second operating mode, these two modes of operations are mutually exclusive and therefore the limitations of claim 12 are contingent limitation based on the mode of operation.
Furthermore even if modes of operation are not mutually exclusive the limitations of the method recited in claim 12 are contingent limitations as all the limitations are contingent upon the receiving of a write or read request in a second mode which has not been recited in the claims.
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. (see MPEP 2111.04)
Suggested amendments includes positively reciting the changing of the mode of operation and the receiving of write and read requests in the second mode.
Regarding Claim 13, Costa further discloses wherein the first and the second response comprises respective first and second response control signals and wherein, in the first operating mode and/or the second operating mode, the method comprises comparing the first response control signals generated by the first memory controller with the second response control signals generated by the second memory controller and, in response to determining that the first response control signals do not correspond to the second response control signals, assertign a fifth error signal.
“The comparator 226 is configured to compare the primary and redundant copies of the read data XY_A, XY_B. The comparator 226 is also configured to compare the primary and redundant memory read addresses XPTO_A, XPTO_B. If the primary (XPTO_A) and redundant (XPTO_B) memory read addresses differ from what they should be, or the primary (XY_A) and redundant (XY_B) copies of the read data differ, the comparator 116 is configured to generate an error signal” (Costa [0034] the data itself can be the control signal to indicate that the data has been read)
Regarding Claim 14, Claim 11 recites that the method is in a first operating mode, claim 12 recites a second operation mode, and claim 14 recites steps of a third operating mode, these modes of operations are mutually exclusive and therefore the limitations of claim 14 are contingent limitation based on the mode of operation.
Furthermore even if modes of operation are not mutually exclusive the limitations of the method recited in claim 14 are contingent limitations as all the limitations are contingent upon the receiving of a write or read request in a third mode which has not been recited in the claims.
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. (see MPEP 2111.04)
Suggested amendments includes positively reciting the changing of the mode of operation and the receiving of write and read requests.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa (published October 01, 2020) as applied to claim 14 above in view of Tanaka et al. (US 2020/0076645) (hereinafter Tanaka) (published March 05, 2020).
Regarding Claim 15, Costa disclosed the method of claim 14, but does not explicitly state wherein the shared communication channel comprises a first chip-enable signal adapted to enable a first memory and a second chip-enable signal adapted to enable a second memory, and wherein the method comprises asserting the first chip-enable signal when transmitting or receiving data via the first data signal and the second memory controller asserts the second chip-enable signal when transmitting or receiving data via the second data signal.
Tanaka discloses wherein the shared communication channel comprises a first chip-enable signal adapted to enable a first memory and a second chip-enable signal adapted to enable a second memory, and wherein the method comprises asserting the first chip-enable signal when transmitting or receiving data via the first data signal and the second memory controller asserts the second chip-enable signal when transmitting or receiving data via the second data signal.
“The memory controller and the memory are connected by using a serial interface such as a Serial Peripheral Interface (SPI). Here, the memory controller operates as a master device, and the memory as a slave device to be controlled by the master device. According to the SPI standard, a master device can select a memory to communicate by asserting a chip select signal, and transmit signals to the selected memory for data read and write” (Tanaka [0003])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the SPI interface in Tanaka with the system in Costa. The motivation for doing so would be improve compatibility by using industry standards.
Regarding Claim 16, Tanaka further discloses wherein the shared communication channel is a Serial Peripheral Interface Bus or OctalSPI.
“The memory controller and the memory are connected by using a serial interface such as a Serial Peripheral Interface (SPI). Here, the memory controller operates as a master device, and the memory as a slave device to be controlled by the master device. According to the SPI standard, a master device can select a memory to communicate by asserting a chip select signal, and transmit signals to the selected memory for data read and write” (Tanaka [0003])
Claims 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa (published October 01, 2020) as applied to claim 14 above in view of Dudeck et al. (US 2011/0055660) (hereinafter Dudeck) (published March 03, 2011).
Regarding Claim 17, Costa disclosed the method of claim 14, but does not explicitly state wherein the memory controller subsystem comprises a first Error-Correction Code (ECC) circuit associated with the first memory controller and a second ECC circuit associated with the second memory controller, and the method comprises, by each of the first memory controller and the second memory controller: in response to receiving a write request: calculating via the respective first or second ECC circuit ECC bits, and transmitting the respective extracted memory address, the respective extracted data and the respective calculated ECC bits; and in response to receiving a read request: transmitting the respective extracted memory address and receive the respective data and respective ECC bits; calculating via the respective first or second ECC circuit further ECC bits, and comparing the further ECC bits with the received ECC bits and, in response to determining that the further ECC bits do not correspond to the received ECC bits, assert an ECC error signal.
Dudeck discloses wherein the memory controller subsystem comprises a first Error-Correction Code (ECC) circuit associated with the first memory controller and a second ECC circuit associated with the second memory controller, and the method comprises, by each of the first memory controller and the second memory controller:
“The memory circuit 100 further comprises a spare memory element block 120, an ECC block 130, or alternative error correction circuitry, a repair information memory 140 and a repair block 150, or an alternative control circuit” (Dudeck [0021] the two memories in Costa can each have an ECC block)
in response to receiving a write request: calculating via the respective first or second ECC circuit ECC bits, and
“With continued reference to FIG. 1, ECC block 130 is preferably operative to generate ECC information to be appended to the data written into a primary or spare memory element. In one embodiment, ECC block 130 presents the ECC information to the memory 110 for writing, along with the data, into the primary or the spare memory element” (Dudeck [0027])
transmitting the respective extracted memory address, the respective extracted data and the respective calculated ECC bits; and
“With continued reference to FIG. 1, ECC block 130 is preferably operative to generate ECC information to be appended to the data written into a primary or spare memory element. In one embodiment, ECC block 130 presents the ECC information to the memory 110 for writing, along with the data, into the primary or the spare memory element” (Dudeck [0027])
in response to receiving a read request: transmitting the respective extracted memory address and receive the respective data and respective ECC bits;
“ECC block 130 preferably also receives data and ECC read from a given primary or a spare memory element, calculates what the read ECC should be for the data read, and compares the predicted ECC to the ECC actually read from the corresponding memory element” (Dudeck [0027])
calculating via the respective first or second ECC circuit further ECC bits, and
“ECC block 130 preferably also receives data and ECC read from a given primary or a spare memory element, calculates what the read ECC should be for the data read, and compares the predicted ECC to the ECC actually read from the corresponding memory element” (Dudeck [0027])
comparing the further ECC bits with the received ECC bits and, in response to determining that the further ECC bits do not correspond to the received ECC bits, assert an ECC error signal.
“ECC block 130 preferably also receives data and ECC read from a given primary or a spare memory element, calculates what the read ECC should be for the data read, and compares the predicted ECC to the ECC actually read from the corresponding memory element. When the predicted ECC and the read ECC match, there is no error detected and no further action is taken by the ECC block 130 or by the repair block 150. Alternatively, when the predicted ECC and the read ECC do not match, this is indicative of an error, and the corresponding primary or spare memory element containing the erroneously read data is flagged as defective by the ECC block 130” (Dudeck [0027])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the ECC of Dudeck with the system of Costa. The motivation for doing so would be for a more robust system that is able to find and correct some errors.
Claim 17 recites contingent limitations as all the limitations are contingent upon the receiving of a write or read request which has not been recited in the claims (see 112(b) above) and also in the last limitation there is a contingency that is dependent on a determining step that was never stated in the claim.
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. (see MPEP 2111.04)
Regarding Claim 18, Dudeck further discloses wherein the first and second ECC circuits are error detection and correction circuits, and the method comprises generating corrected data, and wherein the first or second response comprises the respective corrected data.
“The memory circuit 100 further comprises a spare memory element block 120, an ECC block 130, or alternative error correction circuitry, a repair information memory 140 and a repair block 150, or an alternative control circuit” (Dudeck [0021])
“Hence, when an error is detected, the ECC block 130 corrects the data and passes the corrected data back to the memory 110 for outputting via output connection 118. In parallel with supplying the corrected data, the ECC block 130 preferably stores the location of the defective memory element for performing a replacement of the defective memory element with a spare memory element” (Dudeck [0027])
Claim 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa (published October 01, 2020) and Dudeck (published March 03, 2011) as applied to claim 17 above, and further in view of MOYER (US 2012/0066567) (hereinafter Moyer) (published March 15, 2012).
Regarding Claim 19, the combination of Costa and Dudeck disclosed the method of Claim 17, but does not explicitly state further comprising, by the first and second ECC circuits, calculating the respective ECC bits as a function of the respective extracted data or received data and the respective memory address.
Moyer discloses further comprising, by the first and second ECC circuits, calculating the respective ECC bits as a function of the respective extracted data or received data and the respective memory address.
“In response to the address and data inputs, multiplexer 50 selects one of the error coding functions dependent on address bit 29 and provides a checkbit value having 32-bit ECC granularity” (Moyer [0028])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of address and data in the calculation of ECC in Moyer. The motivation for doing so would be to improve error detection by preventing address aliasing when accessing the memory or stale memory reads.
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa (published October 01, 2020) as applied to claim 14 above in view of Gschwind et al. (US 2003/0046492) (hereinafter Gschwind) (published March 06, 2003).
Regarding Claim 20, Costa disclosed the method of Claim 14, but does not explicitly state wherein the memory controller subsystem comprises a control circuit, and the method comprises receiving, by the control circuit, configuration data and selecting one of the first, second or third operating mode as a function of the configuration data.
Gschwind discloses wherein the memory controller subsystem comprises a control circuit, and the method comprises receiving, by the control circuit, configuration data and selecting one of the first, second or third operating mode as a function of the configuration data.
“The memory configuration logic 420 includes an array address mapping module 425, a control module 430, mode selection logic 435, tag match logic 440, and multiplexers 445 and 450. The configuration of the memory array 410 is controlled by the mode selection logic 435, which generates all necessary control and configuration signals. The mode of operation can be selected by: control signals 428, which can, for example, be generated on the package (e.g., with programmable fuses), from the input pins or hardwired; from a configuration register, which may be configured either by at system boot time or by software through the use of a predefined interface; or be determined by control signals transmitted in conjunction with the memory address, or may be a function the memory address itself” (Gschwind [0040])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of configuration logic to select the mode of operation in Gschwind. The motivation for doing so would be to improve adaptability and efficiency by not needed to manually change code when changing modes and be able to change modes while the code remains immutable.
Allowable Subject Matter
Claims 1-10 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 recites “wherein the memory controller subsystem comprises a first memory controller and a second memory controller, wherein each of the first memory controller and the second memory controller is configured to: receive a write or read request comprising data indicating a memory address and, for the write request, respective data to be stored; in response to receiving the write request: extract a respective memory address and the respective data to be stored from the write request, and generate a respective first or second communication for storing the respective extracted data to the respective extracted memory address by generating a respective first or second data signal used to transmit the respective extracted memory address and the respective extracted data; in response to receiving a read request: extract a respective memory address from the read request, generate the respective first or second communication for receiving data associated with the extracted memory address by generating the respective first or second data signal in order to transmit the respective extracted memory address and receive the respective data associated with the extracted memory address, and generate a respective first or second response comprising the respective received data; wherein, in a first operating mode, the first communication of the first memory controller is connected to the communication channel, wherein the first data signal corresponds to the data signal, and the memory controller subsystem is configured to: in response to receiving from the communication system the write request: forward the received write request to the first memory controller and the second memory controller, wherein the first memory controller generates the respective first data signal used to transmit the respective extracted memory address and the respective extracted data and the second memory controller generates the respective second data signal used to transmit the respective extracted memory address and the respective extracted data, and compare the first data signal with the second data signal and, in response to determining that the first data signal does not correspond to the second data signal, assert a first error signal; in response to receiving from the communication system the read request: forward the received read request to the first memory controller and the second memory controller, wherein the first memory controller generates the respective first data signal used to transmit the respective extracted memory address and receive the respective data associated with the respective extracted memory address and the second memory controller generates the respective second data signal used to transmit the respective extracted memory address and receive the respective data associated with the respective extracted memory address, and the first memory controller generates the respective response comprising the respective received data and the second memory controller generates the respective response comprising the respective received data; in response to determining that the first memory controller transmits the extracted memory address via the first data signal, compare the first data signal with the second data signal and, in response to determining that the first data signal does not correspond to the second data signal, assert a second error signal; and in response to determining that the first memory controller receives the respective data via the first data signal, connect the first data signal to the second data signal, compare the first response generated by the first memory controller with the second response generated by the second memory controller and, in response to determining that the first response does not correspond to the second response, assert a third error signal”. These limitations describes a controller that is able to perform the different combinations of specific steps with respect to receiving write and read requests in different modes of operations.
The limitations above are not taught or rendered obvious in view of the prior art of record, particularly in combination with the other limitations within the claims. Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action, and claims 2-10 are dependent on claim 1 and would also be allowable for at least the same reasons as its respective independent claim if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jung (US 2014/0108896) discloses multiple controllers that processes data and comparing the data to detect errors
Borgonovo et al. (US 2022/0180959) discloses the use of lock step processors where read and write requests are directed towards multiple controllers and the comparing of read and write requests.
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137