DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-2, 4-5, 12, 16-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Benisty et al. (Pub. No. US20230244614)
As per claim 1, Benisty discloses a method of operating a storage device (fig.1, storage device 106) comprising a first storage controller (fig.1, controller 108) and a controller manager (paragraph 47, a scheduler), the method comprising:
receiving a first command from a first host (fig.1, host 104) through a first port (fig.2, host bus adapter (HBA) 204A) connected to the first storage controller configured to store data of the first host (paragraph 31, the controller 108 initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command);
receiving first information associated with the first command from the first host through a second port (Fig. 2, second HBA 206A) connected to the controller manager configured to manage the first storage controller (paragraph 48, receive a command from a host device on a first/second port); determining a priority of the first command among a plurality of commands (paragraph 42, monitored parameters throughput for each port, the link speed/gen of each link, and the priority and QoS requirements of the current data transfer); and
executing the first command based on the priority (paragraph 8, Based upon an analysis of one or more of the factors (e.g., link workload, idle time for each port, link power state, throughput for each port, speed of each link, priority of data transfer, and quality of service (QoS)), the port scheduler can transfer data on a port.)
As per claim 12, Benistry discloses a method of operating a host (fig.1, host 104) configured to store data in a storage device (paragraph 31, the controller 108 initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command), the method comprising:
writing a first command into a submission queue (fig.1, a write buffer 116);
transmitting the first command to the storage device through a first port paragraph 31, the controller 108 initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command);
transmitting first information associated with the first command to the storage device through a second port (paragraph 48, receive a command from a host device on a first/second port);
receiving a first execution result of the first command from the storage device(paragraph 42, monitored parameters throughput for each port, the link speed/gen of each link, and the priority and QoS requirements of the current data transfer);
receiving second information associated with the first execution result from the storage device through the second port (paragraph 42, monitored parameters throughput for each port, the link speed/gen of each link, and the priority and QoS requirements of the current data transfer); and
processing the first execution result based on the second information, wherein the second port is connected to a controller manager configured to manage at least one storage controller in the storage device(paragraph 8, Based upon an analysis of one or more of the factors (e.g., link workload, idle time for each port, link power state, throughput for each port, speed of each link, priority of data transfer, and quality of service (QoS)), the port scheduler can transfer data on a port.)
As per claim 17, Benisty discloses a storage device (fig.1, storage device 106) configured to store data of at least one host (fig.1, host 104), the storage device comprising:
at least one non-volatile memory device (fig.1, NVM 110 ) configured to store data;
at least one storage controller (fig.1, controller 108) configured to control the at least one non-volatile memory device and receive a first command (paragraph 31, the controller 108 initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command) and data from a first host through a first port (fig.2, host bus adapter (HBA) 204A); and
a controller manager (paragraph 47, a scheduler) configured to manage the storage controller and receive first information associated with the first command (paragraph 48, receive a command from a host device on a first/second port) through a second port (Fig. 2, second HBA 206A).
As per claims 2 and 16, Benisty wherein the first host is connected to the first storage controller through a first interface, and wherein the controller manager is connected to the first host through a second interface (paragraph 35, The controller 406 includes a host interface module (HIM) 408 that implements the dual port feature (i.e., PCIe endpoints or ports 410A, 410B) while having two NVMe logics 412A, 412).
As per claim 4, Benisty discloses wherein the plurality of commands are fetched by the first storage controller (paragraph 26, NVM 110 may be configured to store and/or retrieve data), and the priority is determined by the first storage controller (paragraph 8, Based upon an analysis of one or more of the factors (e.g., priority of data transfer), the port scheduler can transfer data on a port.)
As per claim 5, Benisty discloses wherein the plurality of commands are fetched to an internal buffer block of the first storage controller (paragraph 31, the controller 108 temporarily stores the data associated with the write command in the internal memory or write buffer 116 before sending the data to the NVM 110), and wherein the priority of the plurality of commands is determined based on the first information by a command management block configured to manage the priority of the plurality of commands(paragraph 8, Based upon an analysis of one or more of the factors (e.g., priority of data transfer), the port scheduler can transfer data on a port.)
As per claim 18, Benisty discloses wherein the storage controller is configured to determine a priority of execution between a plurality of commands including the first command based on the first information (paragraph 8, Based upon an analysis of one or more of the factors (e.g., priority of data transfer), the port scheduler can transfer data on a port).
As per claim 19, Benisty discloses wherein the storage controller includes: function blocks configured to execute the first command (paragraph 53, a command that was paused prior to being deferred to defer queue 112 begins execution from the saved state--that is the state prior to the pause); a host interface (fig.1, interface 114) block configured to communicate with the at least one host; and
a command management block (paragraph 47, a scheduler) configured to determine a priority of a plurality of commands comprising the first command based on the first information received from the controller manager(paragraph 8, Based upon an analysis of one or more of the factors (e.g., priority of data transfer), the port scheduler can transfer data on a port).
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 3, 6-11, 13-15, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty et al. (Pub. No. US20230244614) in view of Roberts et al. (Pub. No. US2015/0095605)
As per claims 3,13, and 20, Benisty discloses wherein the first information comprises a command ID of the first command (paragraph 37, the token indication dedicated resources/ports.)
Benisty discloses all the limitations as the above but does not explicitly disclose the first information comprises a latency limitation of the first command. However, Roberts discloses this (paragraph 49, the control module 114 calculates the predicted latency of each pending command)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Roberts with the teaching of Benistry so as to prevent bottlenecks and versus network congestion so as to make system more efficient so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 6, Benisty discloses wherein the command management block comprises: a command control circuit configured to determine the priority of the plurality of commands based on the first information (paragraph 8, Based upon an analysis of one or more of the factors (e.g., priority of data transfer), the port scheduler can transfer data on a port); and
Benisty discloses all the limitations as the above but does not explicitly disclose “a latency calculation circuit configured to calculate remaining latency of the plurality of commands.” However, Roberts discloses this (paragraph 49, the control module 114 calculates the predicted latency of each pending commands)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Roberts with the teaching of Benistry so as to prevent bottlenecks and versus network congestion so as to make system more efficient so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 7, Roberts discloses the method further comprising calculating a remaining latency of the first command while the first command is executed (paragraph 49, calculating the predicted latency of each pending command, channel control module 114 takes into account the value of data that is written or read from the memory region.)
As per claim 8, Roberts discloses the method further comprising: transmitting second information comprising the remaining latency of the first command to the first host (paragraph 49, calculating the predicted latency of each pending command, channel control module 114 takes into account the value of data that is written or read from the memory region.); and transmitting an execution result of the first command to the first host, wherein the second information further comprises controller status information of the first storage controller (paragraph 53, When channel control module 114 reinstates the command back to command queue either due to a slot opening or the maximum time constraint, channel control module 114 also reinstates the state of the command.)
As per claim 9, Benisty discloses wherein the controller status information comprises power consumption amount of the first storage controller, performance of the first storage controller, and a status of the first storage controller (paragraph 29, the power supply 111 may include one or more power storage components configured to provide power to the one or more components when operating in a shutdown mode.)
As per claim 10, Benisty discloses wherein the execution result of the first command is transmitted to the first host through the first port, and wherein the second information is transmitted to the first host through the second port (paragraph 10-11, a port scheduler configured to determine over which port of a plurality of ports data will transfer.)
As per claim 11, Benisty discloses wherein the first information is received based on a non-volatile memory express-management interface (NVMe-MI) standard, and wherein the second information is transmitted based on the NVMe-MI standard (paragraph 22, host device 104 may utilize a non-volatile memory (NVM) 110 included in data storage device 106 to store and retrieve data.)
As per claim 14, Roberts discloses wherein a processing time of the first execution result is determined based on the remaining latency (paragraph 49, calculating the predicted latency of each pending command, channel control module 114 takes into account the value of data that is written or read from the memory region.)
As per claim 15, Roberts discloses wherein the first execution result is written to a completion queue included in the host, and wherein the first execution result is processed to comply with the latency limitation of the first command, based on the remaining latency (paragraph 49, calculating the predicted latency of each pending command, channel control module 114 takes into account the value of data that is written or read from the memory region.)
5. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Agarwal et al. [Pub. No. US2022/0113905] discloses The controller then executes the commands in the memory or zone resources according to the priority order.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184