DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
As per claim 1,
Line 8 – 9, “a software update unit configured to perform update processing of the first software and the second software;”
Line 10 – 14, “a software abnormality recognition unit configured to recognize presence or absence of an abnormality in the first software …”
Line 15 – 23, “a software abnormality handling unit configured to cause either the first processor or the second processor to perform abnormality handling processing of operating a target …”
Claim 2, line 9 – 12, “the software abnormality recognition unit recognizes that either the first software”
Claim 3, line 13 – 24, “in a case where the software abnormality recognition unit recognizes that either the first software … the software abnormality handling unit causes the first processor to execute the old version of the first software stored in the first memory, …”
Claim 4, “wherein in a case where the software abnormality recognition unit recognizes that the secure boot … the software abnormality handling unit performs processing of prohibiting the first processor …”
Claim 5, “wherein the software abnormality handling unit causes a notification unit provided …”
Claim 6, line 13 – 27, “where the software abnormality recognition unit recognizes that either the secure boot of the new version of the first software … the software abnormality handling unit causes the first processor to execute the old version of the first software …”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The “software update unit”, “software abnormality handling unit”, “a software abnormality handling unit” are described as implemented by the first processor and the second processor.
(Specification, [par. 0044], “ The first processor 11 executes the program of the boot processing stored in the area 12c of the first memory 12, and the second processor 21 executes the program of the boot processing stored in the area 22c of the second memory 22, thereby each functioning as a software update unit, a software abnormality recognition unit, and a software abnormality handling unit in the present disclosure”)
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 7 – 8 are rejected under 35 U.S.C. 103 as being unpatentable over Paffen et al. (Publication No. US 20200110372 A1; hereinafter Paffen) in view of Goto, Fumihide (Publication No. US 20220171613 A1; hereinafter Goto).
Regarding to claim 1, Paffen teaches
A moving body control device (fig. 1. “control device 11”) comprising:
a first processor; ([Par. 0042], “The control device 11 may include a first processor unit 13 and a second processor unit 14, which are designated here by name as compute node 1 and as compute node 2.”)
a [[first]] memory in which first software to be used by the first processor is stored; ([Par. 0044 – 0045], “A memory unit 16 with at least one data memory 17, for example an SSD memory (SSD—solid state disk), can be provided. [0045] In order to interconnect the processor units 13, 14 with the peripheral units 15 and the memory unit 16 for data exchange, data lines 18 may be provided between them. The data lines 18 are designated in the figures with the designations Link1 to Link15. Each may be, for example, multiple conductor paths or multiple wires.” This implies that both of the first processor and the second processor are linked to the memory unit 16 for executing instruction stored in the memory unit 16.)
a second processor; ([Par. 0042], “The control device 11 may include a first processor unit 13 and a second processor unit 14, which are designated here by name as compute node 1 and as compute node 2.”)
a [[second]] memory in which second software to be used by the second processor is stored; ([Par. 0044 – 0045], “A memory unit 16 with at least one data memory 17, for example an SSD memory (SSD—solid state disk), can be provided. [0045] In order to interconnect the processor units 13, 14 with the peripheral units 15 and the memory unit 16 for data exchange, data lines 18 may be provided between them. The data lines 18 are designated in the figures with the designations Link1 to Link15. Each may be, for example, multiple conductor paths or multiple wires.” This implies that both of the first processor and the second processor are linked to the memory unit 16 for executing instruction stored in the memory unit 16.)
a software update unit configured to perform update processing of the first software and the second software; ([Par. 0029], “in the second operating mode, that is to say while the second processor unit is executing the operating function, provision is made in particular for the control device to keep the first processor unit coupled to a memory unit with at least one data memory by means of the first switching unit. In this case, for example, software or an operating program for the first processor unit can be transferred from the memory unit to the first processor unit and, as a result, the first processor unit can be maintained or provided with an update.”; [Par. 0060], “In the third operating mode, the first processor unit 13 is operated normally while the second processor unit 14 is being serviced or restarted. This may be because a faulty behavior of the second processor unit 14 has been detected or because a software/firmware update has to be performed at the second processor unit 13. Thus, the second processor unit 13 is either restarted or turned off. For the third operating mode, the second processor unit 14 is coupled via the second switching unit 20 exclusively to the memory unit 16.” This is understood as the first processor and the second processor are updated via software update received from the memory.)
a software abnormality handling unit configured to cause either the first processor or the second processor to perform abnormality handling processing of operating a target moving body to be controlled by the moving body control device in a predetermined abnormality handling mode, in a case where the software abnormality recognition unit recognizes the abnormality of either the first software stored in the first memory or the second software stored in the second memory. ([Par. 0060], “In the third operating mode, the first processor unit 13 is operated normally while the second processor unit 14 is being serviced or restarted. This may be because a faulty behavior of the second processor unit 14 has been detected or because a software/firmware update has to be performed at the second processor unit 14. Thus, the second processor unit 14 is either restarted or turned off. For the third operating mode, the second processor unit 14 is coupled via the second switching unit 20 exclusively to the memory unit 16.”; [Par. 0061], “[0061] The first processor unit 13 takes over the limited auxiliary function 24’ for execution. Thus, the first processor unit 13 for the auxiliary function 24′ must be coupled or interconnected with the peripheral units 15 used by the auxiliary function 24′ via the Link2”
this is interpreted as if the second processor is determined to be faulty, the first processor takes over control of auxiliary function for execution.)
Paffen teaches handling the abnormality of the software update of the first and second processor as described above, but does not explicitly disclose to have distinct first and second memory for storing software used by the first and second processors; a software abnormality recognition unit configured to recognize presence or absence of an abnormality in the first software stored in the first memory and the second software stored in the second memory, after the update processing is performed;
However, Goto teaches to have distinct first and second memory for storing software used by the first and second processors;
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(see fig. 1, the first virtual storage 134 and first update portion 133 is associated with the first virtual machine 130. Similarly, the second virtual storage 152 and the second update portion 151 is associated with the second virtual machine 150, and so on.)
a software abnormality recognition unit configured to recognize presence or absence of an abnormality in the first software stored in the first memory and the second software stored in the second memory, after the update processing is performed; ([Par. 0091 – 0092], “After the process to update the virtual machine software starts, the update management portion132 may be found to be incapable of communicating with the update portion. In this case, the entire update process may be considered to malfunction and may be retried. [0092] According to the present embodiment, the update management portion 132 determines the availability of the communication with the update portion before starting a series of processes related to the software update. It is possible to prevent an error from being determined to occur on the entire update process and eventually prevent the entire update process from being retried. Moreover, the transfer and separation processes are performed on only the necessary update files.”; [Par. 0120], “Suppose the communication availability determination portion 135 determines a failed communication between the update management portion 132 and the update portion 161. Then, the restart request portion 141 requests a vehicle user to restart the vehicle. The restart request may be notified visually or audibly.”)
A person of ordinary skill in the art would have found it obvious to implement Paffen’s redundant dual-processor vehicle control device using Goto’s well-known software storage architecture, such that first software used by the first processor is stored in a first memory and second software used by the second processor is stored in a second memory, as recited in the claim. Doing so would have been a predictable design choice to enable independent software updating, fault isolation, and safe fallback operation in a moving-body control device.
Examiner Note:
The mapping is understood as Paffen discloses a control device including a first processor and a second processor and describes processor-specific operation modes, Paffen does not expressly describe separate memories in which respective software for each processor is stored, instead describing a shared memory unit accessible by the processors (Paffen, e.g., [0044], [0057], [0060]). Goto remedies this deficiency by expressly disclosing an electronic control unit architecture in which software is stored in distinct memory areas associated with different execution entities, and in which software updates are performed on those stored software images. Specifically, Goto discloses that a real storage includes multiple storage areas, including a software storage area that stores software executed by individual virtual machines, and that update processing is performed on software stored in those memory areas (Goto, e.g., [0039] – [0040], [0143]–[0145]). Each virtual machine executes its own software stored in a corresponding storage area, thereby teaching that different software programs are stored in different memory regions and used by different processors or processing entities.
Claim 7 recites a method with substantially similar scope as claim 1 above, thus being rejected for the same basis as claim 1 above.
Claim 8 recites a non-transitory recording medium with substantially similar scope as claim 1, thus being rejected for the same basis as claim 1 above.
Allowable Subject Matter
Claims 2 – 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/STEVEN VU NGUYEN/Examiner, Art Unit 3668