DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9-12 and 14-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Etter (US 2013/0044873 A1).
Regarding claim 9, Etter anticipates:
“A method comprising: causing a first audio device to output an analog form of a pilot signal at a first frequency” by teaching a method that causes a loudspeaker to output an inserted tone, where the loudspeaker is associated with a sampling clock (fSL) controlling a D/A converter (see Etter, figure 3, units 335, 344, and 400, and ¶ 0022 and 0025-0026);
“receiving, from a second audio device, a digital form of the pilot signal, wherein the digital form of the pilot signal comprises a second frequency associated with a sampling rate” by teaching a microphone and A/D converter that is associated with a sampling clock (fSM) controlling the A/D converter, and the A/D converter converts the analog signal with the inserted tone into a digital signal (see Etter, figure 3, units 340 and 348, and ¶ 0022 and 0026);
“determining a difference between the first frequency and the second frequency” by teaching that a frequency computation block determines a frequency offset between the D/A converter sampling clock (fSL) and the A/D converter sampling clock (fSM) using the frequency of the inserted tone (fTone) (see Etter, figure 3, units 350, 355, and 360, and ¶ 0026);
“determining, based on the difference between the first frequency and the second frequency, a clock error” by teaching the determined frequency offset between the D/A converter sampling clock (fSL) and the A/D converter sampling clock (fSM) using the frequency of the inserted tone (fTone) (see Etter, figure 3, units 350, 355, and 360, and ¶ 0026); and
“updating, based on the clock error, the sampling rate” by teaching that a re-sampling block re-samples the digital signal received by the microphone and D/A converter such that the resulting sampling frequency (f͂SM) equals the first clock (fSL) (see Etter, figure 3, unit 385 and ¶ 0026-0027).
Regarding claim 10, see the preceding rejection with respect to claim 9 above. Etter anticipates the “method of claim 9, wherein the pilot signal comprises one or more of: an audible frequency or an inaudible frequency” by teaching that the pilot signal, or inserted tone, has a frequency (fTone) that is a humanly audible signal masked by speech frequencies and/or the frequency is an inaudible frequency (see Etter, ¶ 0026, 0036, and 0039).
Regarding claim 11, see the preceding rejection with respect to claim 9 above. Etter anticipates the “method of claim 9, wherein the first audio device comprises a speaker and is associated with a speaker clock and wherein the second audio device comprises a microphone and is associated with a microphone clock” by teaching that the first audio device comprises a loudspeaker and the second audio device comprises a microphone, where they are each associated with a different clock (fSL and fSM, respectively) (see Etter, figure 3, units 344 and 348, and ¶ 0026).
Regarding claim 12, see the preceding rejection with respect to claim 9 above. Etter anticipates the “method of claim 9, wherein determining the clock error is based on a zero-cross frequency estimate” by teaching that the method determines a zero-crossing frequency estimate (see Etter, ¶ 0027).
Regarding claim 14, see the preceding rejection with respect to claim 9 above. Etter anticipates the “method of claim 9, further comprising performing echo cancellation based on the adjusted sampling rate” by teaching the acoustic echo cancellation process using the synchronized signals (see Etter, figure 3, units 305, 388, and 390, and ¶ 0025 and 0033).
Regarding claim 15, Etter anticipates:
“A method comprising: causing a first audio device to output an analog form of a pilot signal at a first frequency” by teaching a method that causes a loudspeaker to output an inserted tone, where the loudspeaker is associated with a sampling clock (fSL) controlling a D/A converter (see Etter, figure 3, units 335, 344, and 400, and ¶ 0022 and 0025-0026);
“receiving, from a second audio device, a digital form of the pilot signal, wherein the digital form of the pilot signal comprises a second frequency associated with a sampling rate” by teaching a microphone and A/D converter that is associated with a sampling clock (fSM) controlling the A/D converter, and the A/D converter converts the analog signal with the inserted tone into a digital signal (see Etter, figure 3, units 340 and 348, and ¶ 0022 and 0026);
“determining, based on a difference between the first frequency and the second frequency, a clock error” by teaching that a frequency computation block determines a frequency offset between the D/A converter sampling clock (fSL) and the A/D converter sampling clock (fSM) using the frequency of the inserted tone (fTone) (see Etter, figure 3, units 350, 355, and 360, and ¶ 0026);
“receiving, from the second audio device, one or more samples of audio output by the first audio device” by teaching a receiving buffer, where the buffer receives the digital signal, which represents the audio output from the first device, or D/A converter and loudspeaker (see Etter, figure 1, unit 130, 140, 148, and 180, figure 2, units 200, 230, 240, 248, and 285, and figure 3, units 300, 340, 348, and 385, and ¶ 0020, 0022-0023, and 0025-0026); and
“buffering, based on the clock error, the one or more samples of audio” by teaching that a re-sampling block re-samples the digital signal received by the microphone and D/A converter such that the resulting sampling frequency (f͂SM) equals the first clock (fSL), and the re-sampling block reads on buffering the samples based on the clock error (see Etter, figure 3, unit 385 and ¶ 0026-0027).
Regarding claim 16, see the preceding rejection with respect to claim 15 above. Etter anticipates the “method of claim 15, wherein the pilot signal comprises one or more of: an audible frequency or an inaudible frequency” by teaching that the pilot signal, or inserted tone, has a frequency (fTone) that is a humanly audible signal masked by speech frequencies and/or the frequency is an inaudible frequency (see Etter, ¶ 0026, 0036, and 0039).
Regarding claim 17, see the preceding rejection with respect to claim 15 above. Etter anticipates the “method of claim 15, wherein the first audio device comprises a speaker and is associated with a speaker clock and wherein the second audio device comprises a microphone and is associated with a microphone clock” by teaching that the first audio device comprises a loudspeaker and the second audio device comprises a microphone, where they are each associated with a different clock (fSL and fSM, respectively) (see Etter, figure 3, units 344 and 348, and ¶ 0026).
Regarding claim 18, see the preceding rejection with respect to claim 15 above. Etter anticipates the “method of claim 15, wherein the clock error is associated with the second audio device” by teaching that the digital signal from the second device is resampled due to the clock error or offset of the second device (see Etter, ¶ 0026-0027).
Regarding claim 19, see the preceding rejection with respect to claim 15 above. Etter anticipates the “method of claim 15, wherein determining the clock error is based on a zero-cross frequency estimate” by teaching that the method determines a zero-crossing frequency estimate (see Etter, ¶ 0027).
Regarding claim 20, see the preceding rejection with respect to claim 15 above. Etter anticipates the “method of claim 15, further comprising performing echo cancellation” by teaching the acoustic echo cancellation process using the synchronized signals (see Etter, figure 3, units 305, 388, and 390, and ¶ 0025 and 0033).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Etter (US 2013/0044873 A1) in view of Moore (US 2013/0394602 A1).
Regarding claim 1, Etter teaches a method for compensation of clock skew in acoustic echo cancellers using inaudible tones (see Etter, abstract), and Etter teaches:
“A method comprising: causing a first audio device to output an analog form of a pilot signal, wherein the first audio device is associated with a first clock” by teaching a method that causes a loudspeaker to output an inserted tone, where the loudspeaker is associated with a sampling clock (fSL) controlling a D/A converter (see Etter, figure 3, units 335, 344, and 400, and ¶ 0022 and 0025-0026);
“causing a second audio device to convert the analog form of the pilot signal to a detected pilot signal, wherein the second audio device is associated with a second clock” by teaching a microphone and A/D converter that is associated with a sampling clock (fSM) controlling the A/D converter, and the A/D converter converts the analog signal with the inserted tone into a digital signal (see Etter, figure 3, units 340 and 348, and ¶ 0022 and 0026);
“receiving, from the second audio device, the detected pilot signal” by teaching a bandpass filter that receives the digital signal comprising the inserted tone (see Etter, figure 3, units 340 and 350, and ¶ 0026); and
“determining, based on a digital form of the pilot signal and the detected pilot signal, a clock error” by teaching that a frequency computation block determines a frequency offset between the D/A converter sampling clock (fSL) and the A/D converter sampling clock (fSM) using the frequency of the inserted tone (fTone) (see Etter, figure 3, units 350, 355, and 360, and ¶ 0026).
Herein, Etter teaches a re-sampling block re-samples the digital signal received by the microphone and D/A converter such that the resulting sampling frequency (f͂SM) equals the first clock (fSL) (see Etter, figure 3, unit 385 and ¶ 0026-0027). However, Etter does not teach that the first clock and the second clock are synchronized based on the clock error.
Moore teaches active room shaping and noise control using multiple electronic devices (see Moore, figure 1 and abstract). Herein, Moore teaches that the multiple electronic devices, such as speakers, need to be synchronized for high quality audio (see Moore, ¶ 0075 and figure 1, units 118-1 - 118-3). Moore teaches that the different devices have separate clocks and that the clocks are synchronized based on a calculated clock drift (see Moore, ¶ 0076-0078). It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to modify Etter with the teachings of Moore for the purpose of providing improved acoustic echo cancellation and high quality audio (see Etter, ¶ 0007 in view of Moore, ¶ 0075).
Therefore, the combination of Etter and Moore makes obvious the features for “synchronizing, based on the clock error, the first clock and the second clock” because Etter teaches that a re-sampling block re-samples the digital signal received by the microphone and D/A converter such that the resulting sampling frequency (f͂SM) equals the first clock (fSL) (see Etter, figure 3, unit 385 and ¶ 0026-0027), and Moore teaches a similar process by determining a clock error, or clock drift, and adjusting a frequency-locked-loop (FLL) circuit to synchronize a second clock with the first clock (see Moore, ¶ 0075-0077).
Regarding claim 2, see the preceding rejection with respect to claim 1 above. The combination makes obvious the “method of claim 1, wherein the pilot signal comprises one or more of an audible frequency, or an inaudible frequency, and wherein the first audio device comprises a speaker and the second audio device comprises a microphone” by teaching that the pilot signal, or inserted tone, has a frequency (fTone) that is a humanly audible signal masked by speech frequencies and/or the frequency is an inaudible frequency (see Etter, ¶ 0026, 0036, and 0039), and further teaches that the first audio device comprises a loudspeaker and the second audio device comprises a microphone (see Etter, figure 3, units 344 and 348, and ¶ 0026).
Regarding claim 3, see the preceding rejection with respect to claim 1 above. The combination makes obvious the “method of claim 1, wherein the first clock is driven at the same frequency as the second clock, the method further comprising determining a phase trajectory difference between the digital form of the pilot signal and the detected pilot signal” because Moore makes obvious the use of the FLL to synchronize a second clock with the first clock, where the FLL corrects the phase between the two clocks, and this makes obvious the determination of the phase trajectory difference, such that the FLL can correct the phase between the clocks (see Moore, ¶ 0075-0077).
Regarding claim 4, see the preceding rejection with respect to claim 1 above. The combination makes obvious the “method of claim 1, wherein determining the clock error is based on one or more of a zero-cross frequency estimate or a phase trajectory offset estimate” by teaching that the method determines a zero-crossing frequency estimate (see Etter, ¶ 0027).
Regarding claim 5, see the preceding rejection with respect to claim 1 above. The combination makes obvious the “method of claim 1, wherein the first clock is associated with a first sample rate, wherein the second clock is associated with a second sample rate, and wherein the clock error indicates a difference between the first sampling rate and the second sampling rate” by teaching the different sampling frequencies, where the loudspeaker is associated with the sampling clock (fSL) controlling the D/A converter and the microphone is associated with the sampling clock (fSM) controlling the A/D converter, and the clock error is the frequency offset for determining the resampling ratio (see Etter, figure 3, units 335, 340, 344, and 348, and ¶ 0026-0027).
Regarding claim 6, see the preceding rejection with respect to claim 1 above. The combination makes obvious the “method of claim 1, wherein synchronizing the first clock and the second clock comprises resampling one or more of the first clock or the second clock based on the clock error” by teaching the resampling of the second clock so that it matches the first clock (see Etter, figure 3, units 340, 350, 360, and 385, and ¶ 0027).
Regarding claim 7, see the preceding rejection with respect to claim 1 above. The combination makes obvious the “method of claim 1, further comprising: sending, to a first audio device, a digital form of the pilot signal” by teaching the tone insertion block that sends a digital tone for the loudspeaker to output (see Etter, figure 3, units 305, 307, 335, 344, and 400, and ¶ 0026); and
“causing the first audio device to convert the digital form of the pilot signal to the analog form of the pilot signal” by teaching the D/A converter that converts the digital audio signal with the inserted tone to an analog signal for the loudspeaker to output (see Etter, figure 3, units 335 and 344 and ¶ 0026).
Regarding claim 8, see the preceding rejection with respect to claim 1 above. The combination makes obvious the “method of claim 1, further comprising performing echo cancellation based synchronizing the first clock and the second clock” by teaching the acoustic echo cancellation process using the synchronized signals (see Etter, figure 3, units 305, 388, and 390, and ¶ 0025 and 0033).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Etter as applied to claim 9 above, and further in view of Moore.
Regarding claim 13, see the preceding rejection with respect to claim 9 above. Etter anticipates the method of claim 9, but does not appear to teach the features for “determining the clock error is based on a phase trajectory offset estimate” .
Moore teaches active room shaping and noise control using multiple electronic devices (see Moore, figure 1 and abstract). Herein, Moore teaches that the multiple electronic devices, such as speakers, need to be synchronized for high quality audio (see Moore, ¶ 0075 and figure 1, units 118-1 - 118-3). Moore teaches that the different devices have separate clocks and that the clocks are synchronized based on a calculated clock drift (see Moore, ¶ 0076-0078). It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to modify Etter with the teachings of Moore for the purpose of providing improved acoustic echo cancellation and high quality audio (see Etter, ¶ 0007 in view of Moore, ¶ 0075).
Therefore, the combination of Etter and Moore makes obvious the features for “method of claim 9, wherein determining the clock error is based on a phase trajectory offset estimate” because Etter teaches a frequency computation block determines a frequency offset, or clock error, between the D/A converter sampling clock (fSL) and the A/D converter sampling clock (fSM) using the frequency of the inserted tone (fTone) (see Etter, figure 3, units 350, 355, and 360, and ¶ 0026), and Moore teaches a similar process by determining a clock error, or clock drift, and adjusting a frequency-locked-loop (FLL) circuit to synchronize a second clock with the first clock, where the FLL corrects the phase between the two clocks, and this makes obvious the determination of the phase trajectory difference, such that the FLL can correct the phase between the clocks (see Moore, ¶ 0075-0077).
Conclusion
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/Daniel R Sellers/Primary Examiner, Art Unit 2694
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