Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
The drawings filed 11-05-24 have been accepted by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Applicant's election with traverse of Species A, B, and C (corresponding to Fig. 5, 6, and 7), and Species H (Fig. 8) in the reply filed on 5-8-26 is acknowledged. The traversal is on the grounds that Species A, B, and C should be combined into a single Species, that Species D, E, and G should be combined into a single Species, and that Species I and J should be combined into a single Species. This is not found persuasive because each of the Species still includes mutually exclusive characteristics, and the applicant has not yet stated on the record that the different species are obvious variations. As an example, Species A (Fig. 5) discloses wherein a shift register 4_1 includes a single buffer, a nand, and latch, in that order from left to right, while Species B (Fig. 6) discloses wherein a shift register 4_1 includes a single buffer, a nand, and latch, in the opposite direction, from right to left, and Species C (Fig. 7) discloses wherein a shift register includes four buffers, in that order, and so are not a single species. Similarly, Species D (Fig. 9) discloses wherein a shift register 4_1 includes a buffer, a nand, and latch, in that order, while Species E (Fig. 10) discloses wherein a shift register 4_2k-1 includes a 4 buffers, a nand, and latch, in that order, while Species G (Fig. 12) discloses a shift register 4_1 that receives three clock signals (5), and so are not a single species. Species I (Fig. 15) discloses wherein a shift register is divided into at least 3 subunits, while Species J (Fig. 16) discloses wherein a shift register is divided into only 2 subunits (“divided into two subunits 27 at most” discussed in applicant’s [0101]), and so are not a single species.
The requirement is still deemed proper and is therefore made FINAL.
On page 1 of the remarks, claims 7-11 and 13-15 have been withdrawn. However, claim 16 is dependent upon claim 14, and so it has also been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5-8-26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 12, 17, 18, and 20 are rejected under 35 U.S.C. 102a1 as being anticipated by Chen et al. (US 2017/0117341).
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Regarding claim 1, Chen (Fig. 1-3, with Fig. 2 shown above modified with additional labels) discloses a display panel having a display area (100), the display area comprising:
subpixels (105) located in the display area (as seen in Fig. 2); and
a shift register (comprising the elements 210) comprising a plurality of stages of shift units that are cascaded (“plurality of cascaded shift register units 210” discussed in [0024]), each of the plurality of stages of shift units being electrically connected to one control signal line of a plurality of control signal lines (each shift register stage is connected to control lines such as CLK via M2, eg. as seen in Fig. 3) and at least one of the subpixels (eg. via lines 102), wherein each of the plurality of stages of shift units is configured to output a driving signal (called a “scanning signal” in [0043]) to the at least one of the subpixels in response to a control signal (eg. “outputted to the N-th gate line” as discussed in [0041], in response to the inputs signal on CLK and the other input gate lines, which controls the shift register output as seen in Fig. 3), wherein the shift register is located in the display area (as seen in Fig. 2, 210 is part of the display area), and at least one control signal line of the plurality of control signal lines is located in the display area (as seen in Fig. 3, eg. CLK is in between pixel circuits 105);
wherein the display panel further comprises data lines (103) located in the display area (as seen in Fig. 2), wherein the data lines are electrically connected to the subpixels (eg. to control “light emitted” for image display, see also [0029]), and wherein the plurality of control signal lines and the data lines are arranged in a same layer (“signal lines and the data lines 103 are provided in a same layer” discussed in [0033]);
wherein at least one of the subpixels comprises a pixel circuit (“pixel circuit” discussed in [0030]) and a light-emitting diode (eg. a “top luminous organic light emitting diode” as discussed in [0029]), wherein the pixel circuit is electrically connected to the light-emitting diode (eg. “a pixel circuit 105 for driving the organic electroluminescent device” discussed in [0030]) and one of the plurality of stages of shift units (eg. via the gate line 102);
wherein the shift register comprises:
at least one scanning shift register (corresponding 210) electrically connected to at least one of the subpixels through a scanning signal line (eg. each 210 connected to a pixel 105 through a gate line 102, see also the “plurality of shift register units and the rows of pixel units have one-to-one correspondence therebetween” discussed in [0024]);
and/or at least one emission shift register electrically connected to at least one of the subpixels through a light-emitting signal line (this limitation is not being examined due to the alternative language “and/or”).
Regarding claim 20, Chen (Fig. 1-3) discloses a display apparatus, comprising a display panel having a display area (100), wherein the display panel comprises:
subpixels (105) located in the display area (as seen in Fig. 2); and
a shift register (comprising the elements 210) comprising a plurality of stages of shift units that are cascaded (“plurality of cascaded shift register units 210” discussed in [0024]), each of the plurality of stages of shift units being electrically connected to one control signal line of a plurality of control signal lines (each shift register stage is connected to control lines such as CLK via M2, eg. as seen in Fig. 3) and at least one of the subpixels (eg. via lines 102), and being configured to output a driving signal (called a “scanning signal” in [0043]) to the at least one of the subpixels in response to a control signal (eg. “outputted to the N-th gate line” as discussed in [0041], in response to the inputs signal on CLK and the other input gate lines, which controls the shift register output as seen in Fig. 3), wherein the shift register is located in the display area (as seen in Fig. 2, 210 is part of the display area), and at least one control signal line of the plurality of control signal lines is located in the display area (as seen in Fig. 3, eg. CLK is in between pixel circuits 105);
wherein the display panel further comprises data lines (103) located in the display area (as seen in Fig. 2) and electrically connected to the subpixels (eg. to control “light emitted” for image display, see also [0029]), and the plurality of control signal lines and the data lines are arranged in a same layer (“signal lines and the data lines 103 are provided in a same layer” discussed in [0033]);
wherein at least one of the subpixels each comprises a pixel circuit (“pixel circuit” discussed in [0030]) and a light-emitting diode (eg. a “top luminous organic light emitting diode” as discussed in [0029]), and the pixel circuit is electrically connected to the light-emitting diode (eg. “a pixel circuit 105 for driving the organic electroluminescent device” discussed in [0030]) and one of the plurality of stages of shift units (eg. via the gate line 102);
wherein the shift register comprises:
at least one scanning shift register (corresponding 210) electrically connected to at least one of the subpixels through a scanning signal line (eg. each 210 connected to a pixel 105 through a gate line 102, see also the “plurality of shift register units and the rows of pixel units have one-to-one correspondence therebetween” discussed in [0024]);
and/or at least one emission shift register electrically connected to at least one of the subpixels through a light-emitting signal line (this limitation is not being examined due to the alternative language “and/or”).
Regarding claim 2, Chen discloses a display panel as discussed above, wherein the display area comprises a register arranging area (eg. corresponding to the top portion of each 104), the shift register is located in the register arranging area (as seen in Fig. 2, each 210 is in the top portion of 104), and the at least one control signal line of the plurality of control signal lines is located in the register arranging area (as seen in Fig. 3, CLK is in the same area as 210, and so will also be in the claimed “register arranging area”).
Regarding claim 3, Chen discloses a display panel as discussed above, wherein the subpixels define pixels (101, seen in Fig. 1), the pixels define a plurality of pixel columns of the display panel (eg. columns of 101 shown vertically in Fig. 1 and 2), and the plurality of pixel columns and a plurality of spacing areas (eg. the spaces in between columns of pixels containing lines 103) are alternately arranged along a second direction (eg. in the horizontal direction, with 105 and 103 shown alternating in Fig. 2 from left to right), wherein each of the plurality of pixel columns comprises at least two of the pixels arranged along a first direction (eg. there are three pixels in each vertical column as seen in Fig. 2), and the first direction intersects with the second direction (the first direction is vertical while the second direction is horizontal, as discussed above); and
the at least one control signal line of the plurality of control signal lines is located in one of the plurality of spacing areas (as seen in Fig. 3, the control signal line CLK is in a spacing area between pixel columns 105).
Regarding claim 12, Chen discloses a display panel as discussed above, wherein the subpixels define a plurality of pixel rows of the display panel arranged along a first direction (eg. Row1 and Row2 are arranged vertically, one above the other, as seen in the modified Fig. 2 above), wherein each of the plurality of pixel rows comprises at least two of the subpixels arranged along a second direction (eg. corresponding to two subpixels 105a and 105b, both in Row1 as seen in the modified Fig. 2 above, ie. arranged in a horizontal direction) intersecting with the first direction (the first direction is horizontal while the second direction is vertical, as discussed above); and
one of the plurality of stages of shift units comprises a plurality of subunits (210), wherein one of the plurality of subunits is located at a side of one of the subpixels (eg. 210a is on the bottom side of the subpixel 105a, as seen in Fig. 2); and
the plurality of subunits in the one of the plurality of stages of shift units (corresponding to 210) is located at sides of at least two of the subpixels in one of the plurality of pixel rows in the second direction (eg. in the vertical direction, the element 210a is located at the bottom side of subpixel 105a and the top side of subpixel 105c), or the plurality of subunits in the one of the plurality of stages of shift units is located at sides of at least two of the subpixels in one of the plurality of pixel rows in the first direction, respectively (this claim limitation is not being examined due to the alternative language “or”).
Regarding claim 17, Chen discloses a display panel as discussed above, wherein the data lines and the plurality of control signal lines are parallel (as seen in Fig. 3, data lines 103 and control signal lines CLK are both vertical and parallel).
Regarding claim 18, Chen discloses a display panel as discussed above, herein the subpixels define a plurality of pixel rows of the display panel arranged along a first direction (eg. Row1 and Row2 are arranged vertically, one above the other, as seen in the modified Fig. 2 above), wherein each of the plurality of pixel rows comprises at least two of the subpixels arranged along a second direction (eg. corresponding to two subpixels 105a and 105b, both in Row1 as seen in the modified Fig. 2 above, ie. arranged in a horizontal direction) intersecting with the first direction (the first direction is horizontal while the second direction is vertical, as discussed above); and
wherein two stages of shift units (eg. 210a and 210b) that are cascaded are provided between two adjacent pixel rows of the plurality of pixel rows (eg. in between Row1 and Row2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Liu et al. (US 2021/0167094) and Huang et al. (US 2022/0366848).
Regarding claim 4, Chen discloses a display panel as discussed above, wherein at least two of the plurality of stages of shift units in the shift register are arranged in a first direction to form a first unit column (eg. the elements 210 in the left column of Fig. 2), at least another two of the plurality of stages of shift units are arranged in the first direction to form a second unit column (eg. the elements 210 in the middle left column of Fig. 2), the first unit column and the second unit column are arranged in a second direction (arranged next to each other horizontally), and the first direction intersects with the second direction (the first direction is vertical while the second direction is horizontal, as discussed above).
However, while Chen discloses a clock line (CLK), Chen fails to teach or suggest “a first positive clock line, a first negative clock line, a second positive clock line, and a second negative clock line.”
Liu (Fig. 9) discloses a display panel wherein at least two of a plurality of stages of shift units in the shift register are arranged in a first direction to form a first unit column (eg. the left column of SR, seen in Fig. 3), at least another two of the plurality of stages of shift units are arranged in the first direction to form a second unit column (eg. the middle column of SR, seen in Fig. 3), the first unit column and the second unit column are arranged in a second direction (horizontally, ie. they are arranged side by side), and the first direction intersects with the second direction (the first direction is vertical while the second direction is horizontal, as discussed above);
the plurality of control signal lines comprises a first positive clock line (part of the left most signal lines C connected to the first column of shift register stages as seen in Fig. 3, carrying “CLK”), a first negative clock line (part of the left most signal lines C connected to the first column of shift register stages as seen in Fig. 3, carrying “CLKB,” see “a CLK signal and a CLKB signal that are complementary” discussed in [0083]), a second positive clock line (part of the middle signal lines C connected to the middle column of shift register stages as seen in Fig. 3, carrying another CLK signal, see “each group of clock signals corresponds to a group of shift register circuits” discussed in [0083]), and a second negative clock line (part of the middle signal lines C connected to the middle column of shift register stages as seen in Fig. 3, carrying another CLKB signal, similarly to as discussed above, see also “each group of clock signals corresponds to a group of shift register circuits” discussed in [0083]); and
the at least two of the plurality of stages of shift units in the first unit column are electrically connected to the first positive clock line and the first negative clock line, and the at least another two of the plurality of stages of shift units in the second unit column are electrically connected to the second positive clock line and the second negative clock line (as discussed in [0083], “each group of clock signals includes a CLK signal and a CLKB signal that are complementary” and “each group of clock signals corresponds to a group of shift register circuits” and so will receive their corresponding signals through the C lines shown in Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to include a first positive clock line, a first negative clock line, a second positive clock line, and a second negative clock line as taught by Liu so “the distribution of RC loading in each scanning signal line G may be more uniform” (discussed in [0059]).
However, while Liu further discloses the shift registers in each column output the same signal to the same gate line (“a same scanning signal line G is coupled to at least two shift register circuits SR” discussed in [0050]), Chen and Liu fail to teach or suggest wherein, a signal provided by the first positive clock line and a signal provided by the second positive clock line are the same, and a signal provided by the first negative clock line and a signal provided by the second negative clock line are the same.
Huang (Fig. 1 and 5) discloses a display panel wherein at least two of a plurality of stages of shift units in the shift register are arranged in a first direction to form a first unit column (as seen in Fig. 5, corresponding to 30 on the left of Fig. 1), at least another two of the plurality of stages of shift units are arranged in the first direction to form a second unit column (similarly to as discussed above, but corresponding to the right side 30, see also “redundant second shift registers having the same structure as the second shift register” discussed in [0064]);
the plurality of control signal lines comprises a first positive clock line (attached to CLK’ of G_1 in Fig. 5, receiving CK1), a first negative clock line (attached to CLKB’ of G_1 in Fig. 5, receiving CK2).
Additionally, the combination of Chen, Liu, and Huang would provide wherein the plurality of control signal lines comprises a first positive clock line (eg. CLK of Liu provided to the left column C in Fig. 3, corresponding to CK1 on the left side 30 of Huang), a first negative clock line (eg. CLKB of Liu provided to the left column C in Fig. 3, corresponding to CK2 on the left side 30 of Huang), a second positive clock line (eg. CLK of Liu provided to the middle column C in Fig. 3, corresponding to CK1 on the right side 30 of Huang), and a second negative clock line (eg. CLKB of Liu provided to the middle column C in Fig. 3, corresponding to CK2 on the right side 30 of Huang), wherein, a signal provided by the first positive clock line and a signal provided by the second positive clock line are the same (Liu discloses the shift registers provide the same signal to the same gate lines, eg. to reduce RC loading as discussed in [0059], while Huang more specifically teaches the left and right side columns of shift registers 30 have the “same structure” in [0064], and so both left and right side shift registers 30 with the same structure, outputting the same signals, will receive a same first and third clock signals as control signals, see also the similarly duplicated STV11 seen on the left and right sides of Fig. 10, provided to the left and right 30), and a signal provided by the first negative clock line and a signal provided by the second negative clock line are the same (similarly, the left and right side shift registers will receive a same second and third clock signals as control signals).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen and Liu so a signal provided by the first positive clock line and a signal provided by the second positive clock line are the same, and a signal provided by the first negative clock line and a signal provided by the second negative clock line are the same as taught by Huang because this allows “both the first end and the second end of each gate line are coupled to the gate driving circuit 30” (discussed in [0047]) which allows for redundancy, and reduced RC loading (similarly to as discussed in Liu).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Liu, and Huang as applied to claim 4 above, and further in view of Im et al. (US 2022/0093036).
Regarding claim 5, Chen, Liu, and Huang disclose a display panel as discussed above, and Chen further discloses wherein the subpixels define pixels (101, seen in Fig. 1), the pixels define a plurality of pixel columns of the display panel (eg. columns of 101 shown vertically in Fig. 1 and 2), and the plurality of pixel columns and a plurality of spacing areas (eg. the spaces in between columns of pixels containing lines 103) are alternately arranged along a second direction (eg. in the horizontal direction, with 105 and 103 shown alternating in Fig. 2 from left to right), wherein each of the plurality of pixel columns comprises at least two of the pixels arranged along a first direction (eg. there are three pixels in each vertical column as seen in Fig. 2), and the first direction intersects with the second direction (the first direction is vertical while the second direction is horizontal, as discussed above);
the plurality of spacing areas comprises a first spacing area (eg. the spaces in between columns of pixels containing lines 103), and the first unit column and the second unit column are respectively located at two sides of the first spacing area in the second direction (eg. on the left and right, respectively, of the spacing area located in between them);
at least one of the first positive clock line and the first negative clock line is located in the first spacing area (as seen in Fig. 3, CLK is in the spacing area).
However, Chen, Liu, and Huang fail to teach or suggest wherein at least one of the second positive clock line and the second negative clock line is located in the first spacing area.
Im (Fig. 9) discloses a display panel wherein the subpixels define pixels (PXL, seen in Fig. 9), the pixels define a plurality of pixel columns of the display panel (eg. columns of PXL shown vertically in Fig. 9), and the plurality of pixel columns and a plurality of spacing areas (eg. the spaces in between columns of pixels) are alternately arranged along a second direction (eg. in the horizontal direction, with PXL and empty spaces shown alternating in Fig. 9 from left to right), wherein each of the plurality of pixel columns comprises at least two of the pixels arranged along a first direction (eg. there are multiple pixels in each vertical column as seen in Fig. 9), and the first direction intersects with the second direction (the first direction is vertical while the second direction is horizontal, as discussed above);
the plurality of spacing areas comprises a first spacing area (eg. the space in between two PXL columns shown directly to the right of ST1), and a first unit column and the second unit column are respectively located at two sides of the first spacing area in the second direction (eg. on the left and right, respectively, of the spacing area located in between them, the spacing area containing line such as CR_CLK1 and CR_CLK5);
the plurality of control signal lines comprises a plurality of clock lines (eg. a first clock line SC_CLK1, another clock line SR_CLK1, a second clock line SC_CLK5, a second another clock line CR_CLK5, etc.).
Therefore, the combination of Chen, Liu, Huang, and Im would provide a display panel wherein at least one of the first positive clock line and the first negative clock line is located in the first spacing area (eg. the CLKB of Liu, corresponding to CR_CLK1 of Im, seen in the spacing to the right of ST1), and at least one of the second positive clock line and the second negative clock line is located in the first spacing area (eg. another CLKB signal of Liu, corresponding to CR_CLK5 of Im, seen in the same spacing area to the right of ST1 in Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen, Liu, and Huang so multiple clock lines are in the same spacing area as taught by Im because this prevents pixel noise from the clock lines (see [0142]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Liu, and Huang as applied to claim 4 above, and further in view of Yuan et al. (US 2022/0398982).
Regarding claim 6, Chen, Liu, and Huang disclose a display panel as discussed above, and Chen further discloses wherein the subpixels define pixels (101, seen in Fig. 1), the pixels define a plurality of pixel columns of the display panel (eg. columns of 101 shown vertically in Fig. 1 and 2), and the plurality of pixel columns and a plurality of spacing areas (eg. the spaces in between columns of pixels containing lines 103) are alternately arranged along a second direction (eg. in the horizontal direction, with 105 and 103 shown alternating in Fig. 2 from left to right), wherein each of the plurality of pixel columns comprises at least two of the pixels arranged along a first direction (eg. there are three pixels in each vertical column as seen in Fig. 2), and the first direction intersects with the second direction (the first direction is vertical while the second direction is horizontal, as discussed above).
However, Chen, Liu, and Huang fail to teach or suggest wherein the plurality of spacing areas comprises a second spacing area, the first unit column is located at least at both sides of the second spacing area in the second direction, and at least one of the first positive clock line and the first negative clock line is located in the second spacing area;
or the plurality of spacing areas comprises a third spacing area, the second unit column is located at least at both sides of the third spacing area in the second direction, and at least one of the second positive clock line and the second negative clock line is located in the third spacing area (this claim limitation is not being examined due to the alternative language “or”);
or the plurality of spacing areas comprises both a second spacing area and a third spacing area, the first unit column is located at least at both sides of the second spacing area in the second direction and the second unit column is located at least at both sides of the third spacing area in the second direction, at least one of the first positive clock line and the first negative clock line is located in the second spacing area and at least one of the second positive clock line and the second negative clock line is located in the third spacing area (this claim limitation is not being examined due to the alternative language “or”).
Yuan (Fig. 3) discloses a display panel wherein the subpixels define pixels (A11, seen in Fig. 3), the pixels define a plurality of pixel columns of the display panel (eg. columns of A11 shown vertically in Fig. 3), and the plurality of pixel columns and a plurality of spacing areas (eg. the spaces in between columns of pixels) are alternately arranged along a second direction (eg. in the horizontal direction, with the pixels and empty spaces shown alternating in Fig. 3 from left to right), wherein each of the plurality of pixel columns comprises at least two of the pixels arranged along a first direction (eg. there are multiple pixels in each vertical column as seen in Fig. 3), and the first direction intersects with the second direction (the first direction is vertical while the second direction is horizontal, as discussed above);
the plurality of spacing areas comprises a second spacing area (eg. in the location of 322, seen in Fig. 3), the first unit column is located at least at both sides of the second spacing area in the second direction (as seen in Fig. 3, one of the pixels A11 is on both sides of 322, eg. R is on the left and G, and B are both on the right), and at least one of the first positive clock line and the first negative clock line is located in the second spacing area (322 is a clock line, eg. connected to “clock signal line 3” as discussed in [0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen, Liu, and Huang fail so the plurality of spacing areas comprises a second spacing area, the first unit column is located at least at both sides of the second spacing area in the second direction, and at least one of the first positive clock line and the first negative clock line is located in the second spacing area as taught by Yuan because this allows “waveforms of clock signals received by the shift registers 21 connected to the ends of the branch transmission sections 32 are the same or substantially the same” (discussed in [0077]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Dai et al. (US 2021/0375197).
Regarding claim 19, Chen discloses a display panel as discussed above, wherein the subpixels define pixels (101, seen in Fig. 1), the pixels define a plurality of pixel columns of the display panel (eg. columns of 101 shown vertically in Fig. 1 and 2), and the plurality of pixel columns and a plurality of spacing areas (eg. the spaces in between columns of pixels containing lines 103) are alternately arranged along a second direction (eg. in the horizontal direction, with 105 and 103 shown alternating in Fig. 2 from left to right).
However, Chen fails to teach or suggest wherein a width of one of the plurality of spacing areas is greater than a width of a spacing between two adjacent columns of subpixels in a same pixel column.
Dai (Fig. 23) discloses a display panel wherein the subpixels define pixels (3), the pixels define a plurality of pixel columns of the display panel (eg. columns of 3 shown vertically in Fig. 23), and the plurality of pixel columns and a plurality of spacing areas (eg. the spaces in between columns of pixels containing lines 6 or “DATA”) are alternately arranged along a second direction (eg. in the horizontal direction, with the lines shown alternating with the pixels in Fig. 23 from left to right);
wherein a width of one of the plurality of spacing areas is greater than a width of a spacing between two adjacent columns of subpixels in a same pixel column (as seen in Fig. 23, the spacing between pixels 3 where the control lines 6 are located is greater than the spacing between pixels 3 where the data line “DATA” is located).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen so a width of one of the plurality of spacing areas is greater than a width of a spacing between two adjacent columns of subpixels in a same pixel column as taught by Dai because this allows room for a larger number of signal lines.
Conclusion
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/JONATHAN M BLANCHA/ Primary Examiner, Art Unit 2623
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