DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Topaloglu (US Publication 2009/0097186).
In re claim 1, Topaloglu discloses a capacitor device comprising:
a substrate (102 – Figure 1, ¶19);
a first lower wiring layer (bottom 118 of 114 – Figure 1, ¶20) and a second lower wiring layer (bottom 118 of 116 – Figure 1, ¶20) on the substrate (102 – Figure 1);
a plurality of first electrodes (120 of bottom 114 – Figure 1, ¶20) on the substrate (Figure 1);
a plurality of second electrodes (120 of bottom 116 – Figure 1, ¶20) on the substrate and alternately arranged with the plurality of first electrodes (Figure 1); and
a first upper wiring layer (118 of middle 114 – Figure 1) and a second upper wiring layer (118 of middle 116 – Figure 1) at a vertical level that is different from a vertical level of the first lower wiring layer and the second lower wiring layer (Figure 1; The two wiring layers are at different positions on the ‘Z’ axis.),
wherein the first lower wiring layer (118 of bottom 114 – Figure 1) is electrically connected to the first upper wiring layer (118 of middle 114 – Figure 1) via the plurality of first electrodes (120 of lower 114 – Figure 1),
wherein the second lower wiring layer (118 of bottom 116 – Figure 1) is electrically connected to the second upper wiring layer (118 of middle 116 – Figure 1) via the plurality of second electrodes (120 of bottom 116 – Figure 1), and
wherein the first lower wiring layer (118 of bottom 114 – Figure 1) faces the second lower wiring layer (118 of bottom 116 – Figure 1) with the plurality of first electrodes (120 of bottom 114 – Figure 1) and the plurality of second electrodes (120 of bottom 116 – Figure 1) between the first lower wiring layer and the second lower wiring layer (Figure 1).
In re claim 2, Topaloglu discloses the capacitor device of claim 1, as explained above. Topaloglu further discloses wherein the first lower wiring layer (118 of bottom 114 – Figure 1), the second lower wiring layer (118 of bottom 116 – Figure 1), the first upper wiring layer (118 of middle 114 – Figure 1), and the second upper wiring layer (118 of middle 116 – Figure 1) extend in a direction (Figure 1), and wherein the plurality of first electrodes (120 of bottom 114 – Figure 1) and the plurality of second electrodes (120 of bottom 116 – Figure 1) are spaced apart from each other in the direction (Figure 1).
In re claim 3, Topaloglu discloses the capacitor device of claim 1, as explained above. Topaloglu further discloses wherein the plurality of first electrodes (combination of 120 of bottom 114 and 128 attached to 120 of bottom 114 – Figure 1, ¶21) are arranged between the first lower wiring layer (118 of bottom 114 – Figure 1) and the first upper wiring layer (118 of middle 114 – Figure 1), and wherein the plurality of second electrodes (combination of 120 of bottom 116 and 128 attached to 120 of bottom 116 – Figure 1) are arranged between the second lower wiring layer (118 of bottom 116 – Figure 1) and the second upper wiring layer (118 of middle 116 – Figure 1). Note that the Examiner is using a combination of elements 120 and 128 to be the electrodes. Furthermore, note that these electrodes are between the wiring layers are consistent with the depiction shown in the Figures of the Instant Application.
In re claim 4, Topaloglu discloses the capacitor device of claim 1, as explained above. Topaloglu further discloses wherein the plurality of first electrodes (120 of bottom 114 – Figure 1), the plurality of second electrodes (120 of bottom 116 – Figure 1), the first lower wiring layer (118 of bottom 114 – Figure 1), the second lower wiring layer (118 of bottom 116 – Figure 1), the first upper wiring layer (118 of middle or upper 114 – Figure 1), and the second upper wiring layer (118 of middle or upper 114 – Figure 1) define a closed loop (See Figure 1).
In re claim 5, Topaloglu discloses the capacitor device of claim 1, as explained above. Topaloglu further discloses wherein each of the plurality of first electrodes includes:
a first base portion (120 and bottom 128 of bottom 114– Figure 1, ¶21) between the first lower wiring layer and the second lower wiring layer (118 of bottom 114, 116 – Figure 1), the first base portion extending in a vertical direction (‘Z’ direction – Figure 1); and
a first pad portion (120 of middle 114 – Figure 1) extending from the first base portion and in contact with the first upper wiring layer (118 of middle 114 – Figure 1).
In re claim 6, Topaloglu discloses the capacitor device of claim 1, as explained above. Topaloglu further discloses wherein each of the plurality of first electrodes includes:
a first base portion (128 connected to bottom 114 and portion of 120 within 132 – Figure 1, Figure 2, ¶21) between the first lower wiring layer and the second lower wiring layer (118 of bottom 114, 116 – Figure 1, Figure 2), the first base portion extending in a vertical direction (Figure 1, Figure 2); and
a first pad portion (portion of 120 extending from region 132 to 118 of bottom 114 – Figure 1, Figure 2) extending from the first base portion and in contact with the first lower wiring layer (118 of bottom 114 – Figure 1).
In re claim 7, Topaloglu discloses the capacitor device of claim 6, as explained above. Topaloglu further discloses wherein the first upper wiring layer (118 of middle 114 – Figure 1) is in contact with the first base portion (combination of 128 of connected to bottom 114, portion of 120 of bottom 114 within 132, and 120 of middle 114 – Figure 1, Figure 2, ¶21), and wherein the second upper wiring layer (118 of middle 116 – Figure 1) is separated from the first base portion (Figure 1).
In re claim 8, Topaloglu discloses the capacitor device of claim 1, as explained above. Topaloglu further discloses wherein each of the plurality of first electrodes includes:
a first base portion (128 attached to bottom 120 of 114 – Figure 1) between the first lower wiring layer (118 of bottom 114 – Figure 1) and the second lower wiring layer (118 of middle 114 – Figure 1), the first based portion extending in a vertical direction (Figure 1); and
a plurality of first pad portions (120 of bottom 114, 120 of middle 114 – Figure 1) extending from the first base portion (128 – Figure 1) and respectively in contact with the first lower wiring layer (118 of lower 114 – Figure 1) and the first upper wiring layer (118 of middle 114 – Figure 1).
In re claim 9, Topaloglu discloses the capacitor device of claim 8, as explained above. Topaloglu further discloses wherein each of the plurality of first electrodes includes:
a first base portion (combination of 128 connected to bottom 114, portion of 120 of bottom 114 within 132 – Figure 1, Figure 2, ¶21) between the first lower wiring layer (118 of botom 114 – Figure 1) and the second lower wiring layer (118 of bottom 116 – Figure 1), the first based portion extending in a vertical direction (Figure 1); and
a plurality of first pad portions (portion of 120 of bottom 114 extending from region 132 to 118, 120 of middle 114 – Figure 1, Figure 2) extending from the first base portion (combination of 128 connected to bottom 114, portion of 120 of bottom 114 within 132 – Figure 1, Figure 2) and respectively in contact with the first lower wiring layer (118 of bottom 114 – Figure 1) and the first upper wiring layer (118 of middle 114 – Figure 1).
In re claim 11, Topaloglu discloses a capacitor device comprising:
a first lower wiring layer (118 of bottom 114 – Figure 1) and a second lower wiring layer (118 of bottom 116 – Figure 1), each extending in a first direction (Figure 1);
a first upper wiring layer (118 of middle 114 – Figure 1) and a second upper wiring layer (118 of middle 116 – Figure 1) respectively spaced apart from the first lower wiring layer and the second lower wiring layer in a vertical direction (Figure 1);
a plurality of first electrodes, each including a first base portion (combination of portion of 120 within 132 of bottom 114, 128 attached to bottom 114, portion of 120 within 132 of middle 114 – Figure 1, Figure 2) and a first pad portion (portion of 120 extending from bottom 132 towards 118 of bottom 114 and/or portion of 120 extending from middle 132 towards 118 of middle 114 – Figure 1, Figure 2), the first base portion being between the first lower wiring layer (118 of bottom 114 – Figure 1) and the second lower wiring layer (118 of bottom 116 – Figure 1) and extending in the vertical direction (Figure 1), and the first pad portion (portion of 120 extending from bottom 132 towards 118 of bottom 114 and/or portion of 120 extending from middle 132 towards 118 of middle 114 – Figure 1, Figure 2) protruding from the first base portion toward the first upper wiring layer (118 of middle 114 – Figure 1); and
a plurality of second electrodes, each including a second base portion (combination of portion of 120 within 132 of bottom 116, 128 attached to bottom 116, portion of 120 within 132 of middle 116 – Figure 1, Figure 2) and a second pad portion (portion of 120 extending from bottom 132 towards 118 of bottom 116 and/or portion of 120 extending from middle 132 towards 118 of middle 116 – Figure 1, Figure 2), the second base portion being between the first lower wiring layer (118 of bottom 114 – Figure 1) and the second lower wiring layer (118 of bottom 116 – Figure 1) and extending in the vertical direction, and the second pad portion (portion of 120 extending from bottom 132 towards 118 of bottom 116 and/or portion of 120 extending from middle 132 towards 118 of middle 116 – Figure 1, Figure 2) protruding from the second base portion toward the second upper wiring layer (118 of middle 116 – Figure 1),
wherein the first lower wiring layer (118 of bottom 114 – Figure 1) is electrically connected to the first upper wiring layer (118 of middle 114 – Figure 1) via the plurality of first electrodes between the first lower wiring layer and the first upper wiring layer (Figure 1), and
wherein the second lower wiring layer (118 of bottom 116 – Figure 1) is electrically connected to the second upper wiring layer (118 of middle 116 – Figure 1) via the plurality of second electrodes between the second lower wiring layer and the second upper wiring layer (Figure 1).
In re claim 12, Topaloglu discloses the capacitor device of claim 11, as explained above. Topaloglu further discloses wherein the first lower wiring layer (118 of bottom 114 – Figure 1) is in contact with the first base portion (combination of portion of 120 within 132 of bottom 114, 128 attached to bottom 114, portion of 120 within 132 of middle 114 – Figure 1, Figure 2), wherein the first upper wiring layer (118 of middle 114 – Figure 1) is in contact with the first pad portion (portion of 120 extending from bottom 132 towards 118 of bottom 114 and/or portion of 120 extending from middle 132 towards 118 of middle 114 – Figure 1, Figure 2), wherein the second lower wiring layer (118 of bottom 116 – Figure 1) is in contact with the second base portion (combination of portion of 120 within 132 of bottom 116, 128 attached to bottom 116, portion of 120 within 132 of middle 116 – Figure 1, Figure 2), and wherein the second upper wiring layer (118 of middle 114 – Figure 1) is in contact with the second pad portion (portion of 120 extending from bottom 132 towards 118 of bottom 116 and/or portion of 120 extending from middle 132 towards 118 of middle 116 – Figure 1, Figure 2).
In re claim 13, Topaloglu discloses the capacitor device of claim 11, as explained above. Topaloglu further discloses wherein the first lower wiring layer (118 of bottom 114 – Figure 1) is in contact with the first pad portion (portion of 120 extending from bottom 132 towards 118 of bottom 114 and/or portion of 120 extending from middle 132 towards 118 of middle 114 – Figure 1, Figure 2), wherein the first upper wiring layer (118 of middle 114 – Figure 1) is in contact with the first base portion (combination of portion of 120 within 132 of bottom 114, 128 attached to bottom 114, portion of 120 within 132 of middle 114 – Figure 1, Figure 2), wherein the second lower wiring layer (118 of lower 116 – Figure 1) is in contact with the second pad portion (portion of 120 extending from bottom 132 towards 118 of bottom 116 and/or portion of 120 extending from middle 132 towards 118 of middle 116 – Figure 1, Figure 2), and wherein the second upper wiring layer (118 of middle 116 – Figure 1) is in contact with the second base portion (combination of portion of 120 within 132 of bottom 116, 128 attached to bottom 116, portion of 120 within 132 of middle 116 – Figure 1, Figure 2).
In re claim 14, Topaloglu discloses the capacitor device of claim 11, as explained above. Topaloglu further discloses wherein the first pad portion includes a plurality of first pad portions (portion of 120 extending from bottom 132 towards 118 of bottom 114 and portion of 120 extending from middle 132 towards 118 of middle 114 – Figure 1, Figure 2) spaced apart from each other in the vertical direction (Figure 1, Figure 2), wherein the second pad portion includes a plurality of second pad portions (portion of 120 extending from bottom 132 towards 118 of bottom 116 and portion of 120 extending from middle 132 towards 118 of middle 116 – Figure 1, Figure 2) spaced apart from each other in the vertical direction (Figure 1, Figure 2), wherein the first lower wiring layer (118 of bottom 114 – Figure 1) and the first upper wiring layer (118 of middle 114 – Figure 1) are respectively in contact with the plurality of first pad portions (Figure 1), and wherein the second lower wiring layer (118 of bottom 116 – Figure 1) and the second upper wiring layer (118 of middle 116 – Figure 1) are respectively in contact with the plurality of second pad portions (Figure 1).
In re claim 15, Topaloglu discloses the capacitor device of claim 11, as explained above. Topaloglu further discloses wherein each of the plurality of first electrodes has a first sidewall (end of 120 facing 122 of bottom 114 – Figure 1, Figure 2, ¶20) and a second sidewall (end of 120 facing 122 of middle 114 – Figure 1, Figure 2) opposite the first sidewall (Figure 1, Figure 2), wherein the first lower wiring layer (118 of bottom 114 – Figure 1, Figure 2) faces the first sidewall of each of the plurality of first electrodes (Figure 1, Figure 2), and wherein the first upper wiring layer (118 of middle 114 – Figure 1, Figure 2) faces the second sidewall of each of the plurality of first electrodes (Figure 1, Figure 2).
In re claim 16, Topaloglu discloses a capacitor device comprising:
a lower capacitor structure including a first lower wiring layer (118 of bottom 114 – Figure 1) and a second lower wiring layer (118 of bottom 116 – Figure 1) spaced apart from each other and extending in a direction (Figure 1);
a first upper wiring layer (118 of middle 114 – Figure 1) and a second upper wiring layer (118 of middle 116 – Figure 1) respectively spaced apart from the first lower wiring layer and the second lower wiring layer in a vertical direction (Figure 1), the first upper wiring layer and the second upper wiring layer being spaced apart from each other and extending in the direction (Figure 1);
a plurality of first electrodes (combination of 120 of bottom and middle 114 and 128 between bottom and middle 114 – Figure 1) electrically connected to the first lower wiring layer and the first upper wiring layer (Figure 1);
a plurality of second electrodes (combination of 120 of bottom and middle 116 and 128 between bottom and middle 116 – Figure 1) electrically connected to the second lower wiring layer and the second upper wiring layer (Figure 1), and alternately arranged with the plurality of first electrodes in the direction (Figure 1);
an upper capacitor structure including a first lower interlayer wiring layer (118 of top 114 – Figure 1) and a second lower interlayer wiring layer (118 of top 116 – Figure 1) spaced apart from each other (Figure 1), and extending in the direction on the lower capacitor structure (Figure 1);
a first upper interlayer wiring layer and a second upper interlayer wiring layer respectively spaced apart from the first lower interlayer wiring layer and the second lower interlayer wiring layer in the vertical direction, the first upper interlayer wiring layer and the second upper interlayer wiring layer being spaced apart from each other and extending in the direction (¶19; “…it will be appreciated that capacitor 100 may comprise two interconnect layers or more than three interconnect layers depending on the desired performance and functionality of capacitor 100.” Note that Topaloglu discloses more than three interconnect layers, and, therefore, discloses an upper capacitor structure with a first and second upper interlayer wiring layer that has an identical structure as the first and second upper interlayer wiring layers of the lower capacitor structure.);
a plurality of third electrodes (120 of top 114 – Figure 1) electrically connected to the first lower interlayer wiring layer (118 of top 114 – Figure 1) and the first upper interlayer wiring layer (¶19; Topaloglu discloses more than three interconnect layers, and therefore, discloses a plurality of third electrodes having an identical structure as the plurality of first electrodes.);
a plurality of fourth electrodes (120 of top 116 – Figure 1) electrically connected to the second lower interlayer wiring layer (118 of top 116 – Figure 1) and the second upper interlayer wiring layer, and alternately arranged with the plurality of third electrodes in the direction (¶19; Topaloglu discloses more than three interconnect layers, and therefore, discloses a plurality of fourth electrodes having an identical structure as the plurality of second electrodes.); and
an interlayer insulating film (112 – Figure 1, ¶19) between the lower capacitor structure and the upper capacitor structure (Figure 1, ¶19), wherein each of the plurality of first electrodes (combination of 120 of bottom and middle 114 and 128 between bottom and middle 114 – Figure 1) has a first sidewall (end of 120 facing 122 of bottom 114 – Figure 2, Figure 1) and a second sidewall (end of 120 facing 122 of middle 114 – Figure 2, Figure 1) opposite the first sidewall, wherein the first lower wiring (118 of lower 114 – Figure 2, Figure 1) layer faces the first sidewall of each of the plurality of first electrodes (Figure 2, Figure 1) , and wherein the first upper wiring layer (118 of middle 114 – Figure 2, Figure 1) faces the second sidewall of each of the plurality of first electrodes (Figure 2, Figure 1).
In re claim 17, Topaloglu discloses the capacitor device of claim 16, as explained above. Topaloglu further discloses wherein each of the plurality of first electrodes includes:
a first base portion (combination of 120 within 132 of bottom 114 and 128 attached to bottom 114 – Figure 2, Figure 1) between the first lower wiring layer (118 of bottom 114 – Figure 1) and the second lower wiring layer (118 of bottom 116 – Figure 1), and extending in a vertical direction (Figure 1, Figure 2); and
a first pad portion (portion of 120 of bottom 114 extending from 132 towards 118 – Figure 2) protruding from a sidewall of the first base portion (Figure 1, Figure 2), and
wherein each of the plurality of third electrodes includes:
a third base portion (combination of 120 within 132 of top 114 and 128 attached to top 114 – Figure 2, Figure 1) between the first lower interlayer wiring layer (118 of top 114 – Figure 1, Figure 2) and the second lower interlayer wiring layer (118 of top 116 – Figure 1, Figure 2), and extending in the vertical direction (Figure 1, Figure 2); and
a third pad portion (portion of 120 of top 114 extending from 132 towards 118 – Figure 2, Figure 1) protruding from a sidewall of the third base portion (Figure 2, Figure 1).
In re claim 18, Topaloglu discloses the capacitor device of claim 17, as explained above. Topaloglu further discloses wherein the first pad portion (portion of 120 of bottom 114 extending from 132 towards 118 – Figure 2) overlaps at least a part of the third pad portion (portion of 120 of top 114 extending from 132 towards 118 – Figure 2, Figure 1) in the vertical direction (Figure 1, Figure 2).
In re claim 19, Topaloglu discloses the capacitor device of claim 17, as explained above. Topaloglu further discloses wherein the first pad portion (portion of 120 of bottom 114 extending from 132 towards 118 – Figure 2) does not overlap the third pad portion (portion of 120 of top 114 extending from 132 away from 118 – Figure 2, Figure 1) in the vertical direction. Note that the Examiner is taking the third pad portion to extend away from 118.
In re claim 20, Topaloglu discloses the capacitor device of claim 16, as explained above. Topaloglu further discloses wherein each of the plurality of third electrodes (120 of top 114 – Figure 1) has a first sidewall (end of 120 facing 122 of top 114 – Figure 2, Figure 1) and a second sidewall opposite the first sidewall (¶19, Topaloglu discloses more than three interconnect layers, and therefore, discloses a plurality of third electrodes having an identical structure as the plurality of first electrodes. Thus, Topaloglu discloses third electrodes having a second sidewall opposite a first sidewall.),
wherein the first lower interlayer wiring layer (118 of top 114 – Figure 1, Figure 2) faces the first sidewall of each of the plurality of third electrodes (Figure 2, Figure 1), and wherein the first upper interlayer wiring layer faces the second sidewall of each of the plurality of third electrodes (¶19, Topaloglu discloses more than three interconnect layers, and therefore, discloses a plurality of third electrodes having an identical structure as the plurality of first electrodes. Thus, Topaloglu discloses the first upper interlayer wiring layer faces the second sidewall.).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the first pad portion overlaps one of the second lower wiring layer and the second upper wiring layer in the vertical direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tsai et al. (US Patent 6,819,542) Figure 8
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/ARUN RAMASWAMY/ Primary Examiner, Art Unit 2847
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