DETAILED ACTION
This Office Action is in response to Application filed on 05 November 2024.
Claims 1-20 are pending. The claims have been considered and examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 4, 8, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the multiple reads" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the sub-shards" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the sub-shards" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Every limitation of claim 17 is already present in claim 11 from which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 7, 11-14, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khakifirooz et al., U.S. Patent App. Pub. 2021/0294698, hereinafter referred to as “Khakifirooz”, in view of Kirkpatrick et al., U.S. Patent App. Pub. 2019/0391872, hereinafter referred to as “Kirkpatrick”.
Referring to claim 1, Khakifirooz discloses methods for memory (See Khakifirooz, abstract). - A method, comprising:
Khakifirooz discloses a first error correction is unsuccessful for a read (See Khakifirooz, paragraph 0020). Khakifirooz discloses a maximum bit error rate for a target uncorrected bit error rate (See Khakifirooz, paragraph 0018). - determining that a number of data having an unrecoverable error correction code (UECC) error exceeds a number of failed allowable under a redundancy level;
Khakifirooz discloses soft-bit information indicating low confidence bits from the read with the unsuccessful first error correction (See Khakifirooz, paragraph 0019 and 0025). - identifying, in a portion of data in a data having the UECC error, a plurality of low-confidence bits; and
Khakifirooz discloses a second error correction is performed using the additional soft-bit information, the low-confidence bit information (See Khakifirooz, paragraph 0034). - correcting the portion of data by assigning corrected values to one or more low-confidence bits.
Khakifirooz does not disclose “data shards” and “data stripes”. However, Khakifirooz discloses the method is error correction in reads of memory (See Khakifirooz, paragraphs 0015 and 0020).
Kirkpatrick disclose memory and data storage that involves writing data in stripes and breaking up the data into shards (See Kirkpatrick, paragraph 0079).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the use of low-confidence bits to correct uncorrectable errors of Khakifirooz with the use of shards and stripes of Kirkpatrick. This would have been obvious to do because breaking the data into shards allows data segments to be protected from memory and other failures (See Kirkpatrick, paragraph 0081).
Referring to claim 2, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 1) including Khakifirooz discloses the use of LDPC (See Khakifirooz, paragraph 0018). - The method of claim 1, wherein the UECC comprises a low-density parity check (LDPC) code and the data shard has the UECC error based on the LDPC code failing to match an expected value calculated as a function of the portion of data.
Referring to claim 3, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 1) including Khakifirooz discloses read pages of NAND flash memory (See Khakifirooz, paragraphs 0015 and 0016). - The method of claim 1, wherein the portion of data comprises a page of NAND flash memory.
Referring to claim 4, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 1) including Khakifirooz discloses performing additional read operations and modulating the voltage (See Khakifirooz, paragraphs 0018 and 0026). - The method of claim 1, wherein performing the multiple reads of the portion of data comprises performing the multiple reads of the portion of data using different voltages.
Referring to claim 6, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 1) including Kirkpatrick disclose shards and stirpes as segments and distributed along with parity information (See Kirkpatrick paragraph 0079 and 0081). - The method of claim 1, wherein data stripe is a sub-stripe of a larger stripe, and wherein the portion of data and parity information for the sub-stripe are sub-shards of the sub-stripe.
Referring to claim 7, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 1) including Khakifirooz discloses performing additional read operations (See Khakifirooz, paragraphs 0018). - The method of claim 1, wherein identifying the plurality of low-confidence bits comprises: performing multiple reads of the portion of data; and
Khakifirooz discloses with a low confidence bit that a transition has taken place with respect to the bit in question, meaning the bit had different values (See Khakifirooz, paragraph 0019). - identifying, as the plurality of low-confidence bits, a plurality of bits having values differing across the multiple reads.
Referring to claim 11, Khakifirooz discloses systems for memory (See Khakifirooz, abstract). - A system comprising:
Khakifirooz discloses a memory device (See Khakifirooz, paragraph 0039). - a memory; and
Khakifirooz discloses device controller coupled to the NAND memory (See Khakifirooz, paragraph 0039). - a processing device, operatively coupled to the memory, the processing device configured to:
Khakifirooz discloses a first error correction is unsuccessful for a read (See Khakifirooz, paragraph 0020). Khakifirooz discloses a maximum bit error rate for a target uncorrected bit error rate (See Khakifirooz, paragraph 0018). - determine that a number of data having an unrecoverable error correction code (UECC) error exceeds a number of failed allowable under a redundancy level;
Khakifirooz discloses soft-bit information indicating low confidence bits from the read with the unsuccessful first error correction (See Khakifirooz, paragraph 0019 and 0025). - identify, in a portion of data in a data having the UECC error, a plurality of low-confidence bits,
Khakifirooz discloses performing additional read operations (See Khakifirooz, paragraphs 0018). - wherein, to identify the plurality of low-confidence bits, the processing device is further configured to: perform multiple reads of the portion of data;
Khakifirooz discloses with a low confidence bit that a transition has taken place with respect to the bit in question, meaning the bit had different values (See Khakifirooz, paragraph 0019). - identify, as the plurality of low-confidence bits, a plurality of bits having values differing across the multiple reads; and
Khakifirooz discloses a second error correction is performed using the additional soft-bit information, the low-confidence bit information (See Khakifirooz, paragraph 0034). - correct the portion of data based on the one or more low-confidence bits that were identified.
Khakifirooz does not disclose “data shards” and “data stripes”. However, Khakifirooz discloses the method is error correction in reads of memory (See Khakifirooz, paragraphs 0015 and 0020).
Kirkpatrick disclose memory and data storage that involves writing data in stripes and breaking up the data into shards (See Kirkpatrick, paragraph 0079).
It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to combine the use of low-confidence bits to correct uncorrectable errors of Khakifirooz with the use of shards and stripes of Kirkpatrick. This would have been obvious to do because breaking the data into shards allows data segments to be protected from memory and other failures (See Kirkpatrick, paragraph 0081).
Referring to claim 12, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 11) including Khakifirooz discloses the use of LDPC (See Khakifirooz, paragraph 0018). - The system of claim 11, wherein the UECC comprises a low-density parity check (LDPC) code and the data shard has the UECC error based on the LDPC code failing to match an expected value calculated as a function of the portion of data.
Referring to claim 13, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 11) including Khakifirooz discloses read pages of NAND flash memory (See Khakifirooz, paragraphs 0015 and 0016). -The system of claim 11, wherein the portion of data comprises a page of NAND flash memory.
Referring to claim 14, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 11) including Khakifirooz discloses performing additional read operations and modulating the voltage (See Khakifirooz, paragraphs 0018 and 0026). - The system of claim 11, wherein, to perform the multiple reads of the portion of data, the processing device is further configured to perform the multiple reads of the portion of data using different voltages.
Referring to claim 16, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 11) including Kirkpatrick disclose shards and stirpes as segments and distributed along with parity information (See Kirkpatrick paragraph 0079 and 0081). - The system of claim 11, wherein data stripe is a sub-stripe of a larger stripe, and wherein the portion of data and parity information for the sub-stripe are sub-shards of the sub-stripe.
Referring to claim 17, Khakifirooz and Kirkpatrick disclose all the limitations (See rejection of claim 11) including Khakifirooz discloses performing additional read operations (See Khakifirooz, paragraphs 0018). - The system of claim 11, wherein, to identify the plurality of low-confidence bits, the processing device is further configured to: perform multiple reads of the portion of data; and
Khakifirooz discloses with a low confidence bit that a transition has taken place with respect to the bit in question, meaning the bit had different values (See Khakifirooz, paragraph 0019). - identify, as the plurality of low-confidence bits, a plurality of bits having values differing across the multiple reads.
Allowable Subject Matter
Claims 5, 8-10, 15, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable, over the prior art, if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if any above 112 rejections are also overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent App. Pub. 2022/0139481 to Rayaprolu et al.
- Adjusting reliability scan threshold in memory
U.S. Patent App. Pub. 2011/0078496 to Jeddeloh
- Stripe based memory operation
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/JOSEPH D MANOSKEY/Primary Examiner, Art Unit 2113 February 5, 2026