DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-5, in the reply filed on 06/18/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 5-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/29/2023.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by BAINS; Kuljit S. et al. (US 20200278906 A1, hereafter referred to as BAINS).
Rejection of claim 1:
BAINS teaches A memory device, comprising: a memory cell array comprising a normal region in which first data is stored and a parity region in which a parity bit for the first data is stored (Figure 1 in BAINS teaches A memory device 130, comprising: a memory cell array 140 comprising a normal DATA region in which first data is stored and a ECC parity region in which a ECC parity bit for the first data is stored); and an error correction code (ECC) engine configured to determine whether there is an error in the first data, based on the first data and the parity bit (Figures 1 and 6; and, paragraphs bracket 0086]-0091] on page 7 in BAINS teaches an error correction code ECC engine 134 configured to determine whether there is an error in the first data in Steps 608 and 610 whenever a normal read command determined in Step 600, based on the first data and the ECC parity bit), wherein the ECC engine is further configured to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected (Figures 1 and 6; and, paragraphs bracket 0086]-0091] on page 7 in BAINS teaches wherein the ECC engine 134 is further configured to output in Step 612, in response to receiving an uncorrected read/retry command from a memory controller 120 in Step 602, second raw reread data in a state in which the error correction Steps 608 and 610 are bypassed so that an error bit in the first data is not corrected: Note: paragraphs [0021]-[0023] teaches that a read retry command is generated in response to a detectable uncorrectable error, i.e. a DUE; hence, a read retry command is an uncorrected read command whereby the read retry command is generated in response to an uncorrectable error that could not be corrected and for which error correction was bypassed).
The Examiner would like to point out that Paragraphs [0034]-[0036 bracket page 3 BAINS clearly suggests the I/O hardware interface includes pins. Hence, Figure 1 in BAINS clearly suggests a plurality of pins in hardware I/O units 128 and 138 connected to the memory controller 120; and a command decoder 132 configured to separately receive a normal read command and the uncorrected/retry read command based on at least one of the plurality of pins. In addition, paragraph [0025] on page 2 of BAINS teaches that read retry command could be included in a command protocol with other commands such as read, write, refresh or other commands, clearly pointing out an obvious variation where the read retry command would need to be different from other commands in the command protocol. If the read retry command is different from the read command in the command protocol, the read retry command must be different at some logic level of the plurality of pins, otherwise; they would be the same commands.
Allowable Subject Matter
Claims 1-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Citations
US 20230176985 A1 is directed to a serial peripheral interface for controlling command information to disable error correction operations; and, is a good teaching reference.
US 20200278906 A1 is directed to a system in which a hole selectively provides retry commands in which on memory ECC is disabled; and, was used in a 102 rejection, above.
US 10289482 B2 is directed to a memory device that provides an operation to disable on memory error correction whenever error correction is performed in a host device; and, is a good teaching reference.
US 20190130991 A1 is directed to a method and apparatus for operating semiconductor memory devices that include commands to disable and/or enable error correction operations; and, is a good teaching reference.
US 20170308433 A1 is directed to a memory control circuit that includes commands to enable or disable error correction functions; and, is a good 102 and/or 103 reference for possible use in a future office action.
US 20170132075 A1 is directed to a memory control circuit that includes commands to enable or disable error correction functions; and, is a good 102 and/or 103 reference for possible use in a future office action.
US 20110191648 A1 is directed to an apparatus that includes an inversion disable command prevent an error correction circuit from inverting; and, is a good teaching reference.
US 20010042230 A1 is directed to a controller that commands for disabling an error correction function; and, is a good teaching reference.
US 5677802 A is directed to a controller for an error correction engine that includes a command for disabling an error correction function; and, is a good teaching reference.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached on 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112
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