DETAILED ACTION
This action is in response to the request for continued examination filed 06/24/2026 and the claims filed 05/19/2026. Claims 1-20 are pending and have been fully examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 19 May 2026 has been previously entered with the Advisory Action dated 2 June 2026.
Status of the Claims
Claims 1-20 are rejected under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-10, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable by Koinuma et al. (U.S. Patent No. 9065706) in view of Krishnani et al. (U.S. PGPub No. 20230036117).
Regarding Claims 1, 8, and 15, Koinuma teaches a method [Col. 5, lines 65-67], a device including a management unit [Col. 7, lines 54-64] and a memory [Col. 4, lines 33-34], and a system [Fig. 2] including an integrated circuit [Col. 20, lines 51-59], which includes,
receiving a virtual address associated with an execution mode (a logical/virtual address is delivered [Col. 23, lines 21-22; also see Fig. 20, step 304; also see Fig. 21, step 401] ]; where the process of Fig. 21 is performed in response to a shared request; the examiner notes that therefore, the virtual address is associated with an execution mode);
detecting a first condition associated with a search of the virtual address in a translation lookaside buffer (TLB) (a first condition of a TLB miss is detected [Col. 23, line 31; also see Fig. 21, step 402]);
starting a timer based on said detecting the first condition (where a TLB miss leads to an access error [Col. 23 line 65- Col. 24, line 4]; where confirmed access error leads to setting entry of virtual address to physical address to TLB [Col. 25, lines 31-36; also see Fig. 21, step 403]; in response to access error and setting entry, starting a timer [Col, 25, lines 45-46; also see Fig. 27, step 1003]);
detecting a fault exception associated with a translation operation of the virtual address (when a response is not received before timer-end, proceeding to generating a trap [Col. 25, lines 54-59]; where the examiner notes that response not received is indicative of error in physical address (a fault associated with translation) [Also see Fig. 27, steps 1004-1007]);
determining that a second condition is satisfied, wherein the second condition is associated with the execution mode (during access processing (see Fig. 27 for clarity), the system determines whether the access target is a shared or local area based on the physical address [Col. 30, lines 31-38]; where the process of Fig. 27 is performed in response to a shared request; the examiner notes that therefore, a second condition of execution mode is satisfied);
… the timer started based on said detecting the first condition… (where a TLB miss leads to an access error [Col. 23 line 65- Col. 24, line 4]; where confirmed access error leads to setting entry of virtual address to physical address to TLB [Col. 25, lines 31-36; also see Fig. 21, step 403]; in response to access error and setting entry, starting a timer [Col, 25, lines 45-46; also see Fig. 27, step 1003]);
Koinuma does not appear to disclose and Krishnani teaches,
and delivering the fault exception upon expiration of the timer … to delay delivery of the fault exception (where upon receipt by an internal system (SI; 110 of Fig. 4) of a (fault) aggregator signal (Step 582), a fault timer is started (Step 586) to introduce a delay, and the aggregator signal is not delivered to an external system until the timer is expired ("YES" following Step 588 leading to Step 584) [0094&0096; Fig. 5D]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify TLB miss detection and reporting system of Koinuma to include the feature of timer-based delay to deliver the fault of Krishnani. The resulting combination allows time for the system to attempt to perform corrective actions before involving external systems [Krishnani; 0094].
Regarding Claims 2, 9, and 16, Koinuma teaches,
detecting a TLB miss; or detecting a TLB hit (a first condition of a TLB miss is detected [Col. 23, line 31; also see Fig. 21, step 402]).
Regarding Claims 3, 10, and 17, Koinuma teaches,
wherein a value of the timer is programmable (the timer is exemplary programmable [Col. 4, lines 56-57]).
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Koinuma in view of Krishnani, further in view of Ryu et al. (U.S. PGPub No. 20180157553).
Regarding Claim 4, 11, and 18, Koinuma teaches the use of an undisclosed type of timer ((91) and (81) [Fig. 4]), but does not appear to disclose and Ryu teaches,
wherein a value of the timer is contained in a register (a special function register (422) may be used as a timer [0081]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a timer contained in a register as taught by Ryu as the timer as taught by Koinuma in view of Krishnani because a timer contained in a register of a computer system provides an art recognized suitable feature for providing the predictable result of supplying a timer function to the processes requiring a timer function performed by computer.
Claims 5-7, 12-14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Koinuma in view of Krishnani , further in view of Ike (U.S. PGPub No. 20110113291).
Regarding Claims 5, 12, and 20, Koinuma discloses a timer [fig. 4], but does not appear to disclose and Ike teaches,
wherein the timer is based on a global high-resolution timer or a cycle counter (the timer operates based on cycles of the chip it is on ("cycle counter") [0067]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a timer based on a cycle counter as taught by Ike as the timer as taught by Koinuma and Krishnani because a timer based on a cycle counter provides an art recognized suitable feature for providing the predictable result of supplying a timer function to the processes requiring a timer function performed by computer.
Regarding Claims 6-7, 13-14, and 19, Koinuma discloses a timer [fig. 4], but does not appear to disclose and Ike teaches,
determining that adding a random value to a value of the timer is allowed (where the timer is configured with a random number generator to modify the time period [0068]);
and adding the random value to the value of the timer (where the random number generated by the timer unit is added to the value of the timer [0068]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a timer including random variation to the time as taught by Ike as the timer as taught by Koinuma because a timer based on a random variation in time provides an art recognized suitable feature for providing the predictable result of supplying a timer function to the processes requiring a timer function performed by computer.
Response to Arguments
Applicant’s arguments filed 05/19/2026 have been fully considered and are not persuasive. While a response to the arguments filed 05/19/2026 has been provided by the Examiner 06/02/2026 with the Advisory Action entering the claims, the response is reproduced below for clarity of the record.
In response to applicant's argument that the Examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). The secondary reference is relied upon to teach this reasoning with knowledge found from Krishnani, par. 0094.
The Examiner does not find that the first reference, Koinuma, is used to determine whether a fault has occurred as a first condition. The first reference teaches starting a timer upon detection of a first condition [Koinuma; Col. 23, lines 31-35: “when the TLB miss occurs... the CPU performs the trap processing...” an “access error”; Col. 25, lines 45-46: in response to an access error, a timer is started] but does not teach the expiration of said timer to introduce delay. Koinuma's trap setting is performed after expiration of the timer that is started upon detecting of the first condition, as claimed. The second reference, Krishnani, is relied upon to teach a reasoning for delaying delivery of an exception until a timer reaches expiration.
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.E.W./Examiner, Art Unit 2113
/MARC DUNCAN/Primary Examiner, Art Unit 2113
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