DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/12/2026 has been entered.
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
3. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,645,218. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant application is anticipated by patent claim 1 in that claim 1 of the patent contains all the limitations of claim 1 of the instant application. Please see comparison table as below. See In re Goodman(CA FC) 29 USPQ2d 2010(12/3/1993)
And the limitations of the remaining claims 2-20 are found, with minor variations in the recitation of Patent claims 2-20.
Patent (U.S. Patent No. 11,645,218)
Instant Application (18/938,153)
A network architecture, comprising:
A rack assembly, comprising:
a streaming array including a plurality of compute sleds, wherein each compute sled of the plurality of compute sleds includes one or more compute nodes;
a plurality of storage servers comprising a first storage server and a second storage server; a first plurality of compute sleds configured as a first plurality of streaming arrays, wherein each compute sled in the first plurality of compute sleds includes a first plurality of compute nodes;
a network storage of the streaming array; and
A second plurality of compute sleds configured as a second plurality of streaming arrays, wherein each compute sled in the second plurality of compute sleds includes a second plurality of compute nodes; and
a first Peripheral Component Interconnect Express (PCIe) fabric of the streaming array configured to provide direct access to the network storage from a plurality of compute nodes of the streaming array, the first PCIe fabric including one or more array-level PCIe switches directly coupling each of the plurality of compute nodes in the streaming array to the network storage;
a first PCI Express (PCIe) fabric providing direct access from one or more of the first plurality of compute nodes in the first plurality of streaming arrays to the storage plurality of storage servers; and
an array management server (AMS) configured for management of the plurality of compute sleds; and
a second PCIe fabric of the streaming array configured to provide control communication between the AMS and the plurality of compute sleds of the streaming array, wherein the network storage is shared by the plurality of compute nodes of the streaming array, wherein the plurality of compute sleds provides a first plurality of lanes to the one or more array level PCIe switches, wherein the one or more array-level PCIe switches provide a second plurality of lanes to the network storage, wherein the second plurality of lanes is less than the first plurality of lanes.
A second PCIe fabric providing direct access from one or more of the second plurality of compute nodes in the second plurality of streaming arrays to the second storage server in the plurality of storage servers.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights