Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
1. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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2. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,645,218. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant application is anticipated by patent claim 1 in that claim 1 of the patent contains all the limitations of claim 1 of the instant application. Please see comparison table as below. See In re Goodman(CA FC) 29 USPQ2d 2010(12/3/1993)
And the limitations of the remaining claims 2-20 are found, with minor variations in the recitation of Patent claims 2-20.
Patent (U.S. Patent No. 11,645,218)
Instant Application (18/938,153)
A network architecture, comprising:
A rack assembly, comprising:
a streaming array including a plurality of compute sleds, wherein each compute sled of the plurality of compute sleds includes one or more compute nodes;
a plurality of storage servers; a plurality of compute sleds configured as a plurality of streaming arrays, wherein each compute sled in the plurality of compute sleds includes one or more compute nodes;
a network storage of the streaming array; and
a first Peripheral Component Interconnect Express (PCIe) fabric of the streaming array configured to provide direct access to the network storage from a plurality of compute nodes of the streaming array, the first PCIe fabric including one or more array-level PCIe switches directly coupling each of the plurality of compute nodes in the streaming array to the network storage;
a PCI Express (PCIe) fabric providing direct access from a plurality of compute nodes in the plurality of streaming arrays to the plurality of storage servers;
an array management server (AMS) configured for management of the plurality of compute sleds; and
wherein each of the plurality of streaming arrays accesses a dedicated storage server.
a second PCIe fabric of the streaming array configured to provide control communication between the AMS and the plurality of compute sleds of the streaming array, wherein the network storage is shared by the plurality of compute nodes of the streaming array, wherein the plurality of compute sleds provides a first plurality of lanes to the one or more array level PCIe switches, wherein the one or more array-level PCIe switches provide a second plurality of lanes to the network storage, wherein the second plurality of lanes is less than the first plurality of lanes.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over over Faw et al. (Pub. No. US2017/0102510) in view of Regula et al. (Pub. No. US2015/0281126)
As per claim 1, Faw discloses a rack assembly (fig.1, rack assembly 100), comprising:
a plurality of storage servers (fig.8, servers/computes 810 with storages Mems);
a plurality of compute sleds (fig.1, a plurality of sleds such as a sled 142) configured as a plurality of streaming arrays, wherein each compute sled in the plurality of compute sleds includes one or more compute nodes (fig. 1, compute nodes 110);
a PCI Express (PCIe) fabric (fig.7, switch 704) providing direct access from a plurality of compute nodes (fig.9, compute node 900) in the plurality of streaming arrays (paragraph 46, an array of Solid State Disk Drives (SSDs) 716.) to the plurality of storage servers (paragraphs 22-26, The compute nodes 110 provide a compute, storage, networking function, or a combination thereof, for the data center);
wherein each of the plurality of streaming arrays accesses a corresponding dedicated storage server in the plurality of storage servers (paragraph 47, lines 6-7, switch 802 (e.g., integrated in a switch chip) may be configured to support aggregation of data streams and communications between compute nodes 110).
Faw discloses all the limitations as the above but does not explicitly disclose the PCIe fabric including PCIe Switch directly coupling each of the compute nodes in the stream array to the network storage. However, Regula discloses this. (paragraph 5, a method of transferring data over a switch fabric with at least one switch with an embedded network class endpoint device is provided to the respective compute node.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Regula with the teaching of Faw to directly connecting is to maximizing throughput, minimizing latency among others and to enhance the system performance.
As per claims 9 and 17, Faw discloses a network architecture, comprising:
a cluster switch (fig.1, switch 122);
a plurality of storage servers (fig.8, servers/computes 810 with storages Mems);
a plurality of compute sleds (fig.1, a plurality of sleds such as a sled 142) configured as a plurality of streaming arrays (paragraph 46, an array of Solid State Disk Drives (SSDs) 716.), wherein each compute sled in the plurality of compute sleds includes one or more compute nodes (fig. 1, compute nodes 110);
a PCI Express (PCIe) fabric (fig.7, switch 704) providing direct access from a plurality of compute nodes (fig.9, compute node 900) in the plurality of streaming arrays to the plurality of storage servers (paragraph 22, lines 2-3, a data center or a system of servers), wherein each of the plurality of streaming arrays accesses a dedicated storage server; (paragraph 47, lines 6-7, switch 802 configured to support aggregation of data streams and communications between compute nodes 110 included in the sled 142 on tray 102 and other components of the data center or a system of servers that managed by one or more networking elements 112 as further cites in paragraph 22-26). and
Faw discloses all the limitations as the above but does not explicitly disclose a plurality of network switches coupled to a plurality of compute nodes of the plurality of streaming arrays, wherein each network switch is configured to provide communications from compute nodes of a corresponding streaming array to the cluster switch. However, Regula discloses this. (paragraph 5, a method of transferring data over a switch fabric with at least one switch with an embedded network class endpoint device is provided to the respective compute node.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Regula with the teaching of Faw to directly connecting is to maximizing throughput, minimizing latency among others and to enhance the system performance.
As per claims 2, 10 and 18, Faw discloses wherein the PCIe fabric includes: one or more array-level PCIe switches, wherein each array-level PCIe switch is communicatively coupled to one or more compute nodes of a corresponding streaming array and to a corresponding storage server. (paragraphs 22-26, communications between compute nodes 110 included in the sled 142 on tray 102 and other components of the data center that managed by one or more networking elements 112)
As per claims 3, 11 and 19, Faw discloses wherein a streaming array in the plurality of streaming arrays includes: a corresponding array management server configured for managing a plurality of compute sleds in a corresponding streaming array (paragraphs 22-26, Communications may be aggregated between the trays 702 to a switch 704 which configured to provide communications interconnections for the compute nodes in the sled 142 and other devices.); and
a corresponding network switch configured for providing communications from the plurality of compute sleds to a corresponding storage server via the corresponding array management server over an Ethernet fabric for purposes of streaming compute sled and compute node management information. (paragraphs 22-26, Communications may be aggregated between the trays 702 to a switch 704 which configured to provide communications interconnections for the compute nodes in the sled 142 and other devices.)
As per claim 4, Faw discloses wherein the network switch is configured for providing communications over the Ethernet fabric (fig.7, switch 704) to a cluster switch (fig.1, switch 122) providing network communications external to the rack assembly.
As per claim 5, Faw discloses wherein at least one compute node is configured for executing one or more instances of a plurality of video games. (paragraph 50, device 904 that stores instructions that are executable by the host CPU)
As per claims 6 and 14, Faw discloses wherein at least one network storage stores read-only game content of a video game, such that the read-only game content may be shared between compute instances executing the video game on a plurality of compute nodes in the plurality of compute sleds. (paragraph 50, device 904 that stores instructions that are executable by the host CPU)
As per claims 7, 15 and 20, Faw discloses wherein each of the plurality of compute sleds includes: a sled-level PCIe switch communicatively coupled to corresponding compute nodes and a corresponding array-level PCIe switch, wherein the sled-level PCIe switch is configured to provide communications between the corresponding compute nodes and a corresponding network storage through the PCIe fabric via the corresponding array-level PCIe switch. (paragraphs 22-26, communications between compute nodes 110 included in the sled 142 on tray 102 and other components of the data center that managed by one or more networking elements 112)
As per claims 8 and 16, Faw discloses wherein each of the plurality of compute sleds includes: a board management controller (BMC) (fig.1, 112) configured for controlling one or more components on a corresponding sled. (paragraph 54, a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system)
As per claim 12, Faw discloses the network architecture further comprising: a plurality of rack assemblies, wherein each rack assembly includes one or more streaming arrays, wherein each of the one or more streaming arrays being independently operable and includes a corresponding dedicated storage server and a corresponding network switch. (paragraph 22-26, the rack assembly included one or more set of trays which include a plurality of sled 142 each sled having one or more compute nodes that provide a compute, storage, networking function, for the data center having the rack assembly.)
As per claim 13, Faw discloses wherein the cluster switch is communicatively coupled to a communications network to provide network communications that are external to the network architecture. (paragraph 28, matching the network with application workload demands, and may be updated over time separately from the compute nodes 110 comprising the rack assembly 100.)
Response to Amendment
5. Applicant's amendment filed on 1/02/2026 have been fully considered but does not place the application in condition for allowance.
a. With respect to claim 1, Applicant argues that Faw does not teach a rack assembly comprising a plurality of storage servers. Examiner respectfully disagrees. As Faw notes at (paragraph 22, lines 2-3, Examiner further cited for clarification) a data center or a system of servers.)
6. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Panda et al. [Pub. No. US2018/034931] discloses a collection of highly capable compute platforms may be aggregated into a blade chassis or a compute sled, and that chassis may then consume one or more slots in a rack chassis.
Conclusion
7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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