DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 06 November 2024.
Claims 1-20 are pending and have been presented for examination.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities:
Claim 1 contains the limitation “… data being to be written…” in lines 10 and 14.
Claim 11 contains the limitation “… data being to be written…” in lines 7 and 11.
These phrases are not grammatically correct. The Examiner recommends amending the phrases to read “… data being written…” or “… data to be written…”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 10 of U.S. Patent No. 12,175,109. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of the ‘394 patent as shown below.
12,175,109
18/938,394
1. A memory system connectable to a host, the memory system comprising:
(A) a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation;
(B) and a controller configured to manage a first set of blocks and a second set of blocks among the plurality of blocks,
(C) write data to a block included in the first set of blocks in units of a first minimum write size
(D) and write data to a block included in the second set of blocks in units of a second minimum write size smaller than the first minimum write size, wherein the controller is configured to: when a first block included in the first set of blocks is opened as a write destination block, allocate a second block included in the second set of blocks to the first block; write data having the first minimum write size to a plurality of memory cells included in the first block using a first write mode in which two or more bits is written in each of the plurality of memory cells of the first block; write data having the second minimum write size to a plurality of memory cells included in the second block using a second write mode in which one bit is written in each of the plurality of memory cells of the second block;
(F) in response to receiving one or more write commands specifying the first block from the host,
(E) write data having the second minimum write size to the second block when a total size of data associated with the one or more received write commands reaches the second minimum write size;
(G) when a total size of data written to the second block reaches the first minimum write size,
(H) read data having the first minimum write size from the second block, and write the read data to the first block;
and when the first block is filled with data that has been written to the first block, deallocate the second block from the first block.
1. A memory system connectable to a host, the memory system comprising:
(A) a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation;
(B) and a controller electrically connected to the nonvolatile memory and configured to: manage a plurality of block groups, each of the plurality of block groups including one or more first blocks among the plurality of blocks,
(C) data being to be written to each of the one or more first blocks in units of a first minimum write size;
(D) manage at least one second block among the plurality of blocks, data being to be written to the second block in units of a second minimum write size smaller than the first minimum write size;
(E) upon a total size of first data associated with one or more first write commands reaching the second minimum write size,
(F) each of the one or more first write commands being received from the host and specifying an identifier corresponding to a first block group among the plurality of block groups,
(E) write, to the second block, second data which is at least part of the first data and has a size of the second minimum write size;
(G) upon a total size of one or more pieces of the second data written to the second block reaching the first minimum write size,
(H) read, from the second block, third data which includes the one or more pieces of the second data and has a size of the first minimum write size; and write the third data to one of the one or more first blocks included in the first block group.
10. A method of controlling a nonvolatile memory of a memory system,
(A) the nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, the method comprising:
(B) managing a first set of blocks and a second set of blocks among the plurality of blocks;
(C) writing data to a block included in the first set of blocks in units of a first minimum write size,
(D) and writing data to a block included in the second set of blocks in units of a second minimum write size smaller than the first minimum write size;
when a first block included in the first set of blocks is opened as a write destination block, allocating a second block included in the second set of blocks to the first block; writing data having the first minimum write size to a plurality of memory cells included in the first block using a first write mode in which two or more bits is written in each of the plurality of memory cells of the first block; writing data having the second minimum write size to a plurality of memory cells included in the second block using a second write mode in which one bit is written in each of the plurality of memory cells of the second block;
(F) in response to receiving one or more write commands specifying the first block from a host,
(E) writing data having the second minimum write size to the second block when a total size of data associated with the one or more received write commands reaches the second minimum write size;
(G) when a total size of data written to the second block reaches the first minimum write size,
(H) reading data having the first minimum write size from the second block, and writing the read data to the first block; and when the first block is filled with data that has been written to the first block, deallocating the second block from the first block.
11. A method of controlling a nonvolatile memory,
(A) the nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, the method comprising:
(B) managing a plurality of block groups, each of the plurality of block groups including one or more first blocks among the plurality of blocks,
(C) data being to be written to each of the one or more first blocks in units of a first minimum write size;
(D) managing at least one second block among the plurality of blocks, data being to be written to the second block in units of a second minimum write size smaller than the first minimum write size;
(E) determining that a total size of first data associated with one or more first write commands reaches the second minimum write size,
(F) each of the one or more first write commands being received from a host and specifying an identifier corresponding to a first block group among the plurality of block groups;
(E) in response to determining that the total size of first data reaches the second minimum write size, writing, to the second block, second data which is at least part of the first data and has a size of the second minimum write size;
(G) determining that a total size of one or more pieces of the second data written to the second block reaches the first minimum write size; in response to determining that the total size of the one or more pieces of the second data reaches the first minimum write size,
(H) reading, from the second block, third data which includes the one or more pieces of the second data and has a size of the first minimum write size; and writing the third data to one of the one or more first blocks included in the first block group.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 6, 11-13, 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHIN-674 (U.S. Patent Application Publication #2021/0263674) in view of BENISTY (U.S. Patent Application Publication #2021/0409038).
1. SHIN-674 discloses A memory system connectable to a host (see [0082]-[0083]: host 102 operably coupled with memory system 110), the memory system comprising: a nonvolatile memory including a plurality of blocks (see [0099]: memory device includes a plurality of dies including non-volatile memory cells; [0102]: plurality of memory blocks), each of the plurality of blocks being a unit for a data erase operation (see [0101]: memory block is a group of cells erased together); and a controller electrically connected to the nonvolatile memory (see [0085]: controller) and configured to: manage a plurality of block groups, each of the plurality of block groups including one or more first blocks among the plurality of blocks, data being to be written to each of the one or more first blocks in units of a first minimum write size (see [0102]: MLC blocks); manage at least one second block among the plurality of blocks, data being to be written to the second block in units of a second minimum write size smaller than the first minimum write size (see [0102]: SLC blocks); upon a total size of first data associated with one or more first write commands reaching the second minimum write size (see BENISTY below), each of the one or more first write commands being received from the host and specifying an identifier corresponding to a first block group among the plurality of block groups, write, to the second block, second data which is at least part of the first data and has a size of the second minimum write size (see [0106]: write request from host for a zone is received, data is temporarily stored in the SLC buffer; [0065]-[0070]: zones are mapped to the memory, for example TLC blocks, therefore write data from the host is directed to the identified zone, but temporarily stored in SLC; [0065]: host provides a program command with program data and identification information regarding a zone); upon a total size of one or more pieces of the second data written to the second block reaching the first minimum write size (see [0070]: data is accumulated in SLC until reaching the program size for TLC blocks), read, from the second block, third data which includes the one or more pieces of the second data and has a size of the first minimum write size; and write the third data to one of the one or more first blocks included in the first block group (see [0109]: read data from SLC buffer, configure unit of data to be programmed and then programs the memory unit).
BENISTY discloses the following limitations that are not disclosed by SHIN-674: upon a total size of first data associated with one or more first write commands reaching the second minimum write size write, to the second block, second data (see [0033]: data is accumulated to reach the data transfer size before performing write commands to the flash memory). Waiting until the aggregate data meets the minimum transfer size allows the system to take advantage of NAND parallelism (see [0033]). A combination of SHIN-674 and BENISTY would result in SHIN-674 waiting to accumulate a transfer size of data before writing to the second block.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SHIN-674 to perform a write upon a total size of data reaching the second minimum write size, as disclosed by BENISTY. One of ordinary skill in the art would have been motivated to make such a modification to take advantage of NAND parallelism, as taught by BENISTY. SHIN-674 and BENISTY are analogous/in the same field of endeavor as both references are directed to writing to flash memory.
2. The memory system according to claim 1, wherein the controller is further configured to: manage a namespace that is divided into a plurality of zones (see SHIN-674 [0063]: namespace divided into a plurality of zones); and assign the first block group to a first zone among the plurality of zones (see SHIN-674 [0064]: memory blocks are assigned to a zone), and each of the one or more first write commands specifies an identifier of the first zone as the identifier corresponding to the first block group (see SHIN-674 [0065]: host provides a program command with program data and identification information regarding a zone).
3. The memory system according to claim 1, wherein each of the plurality of block groups includes only one first block (see SHIN-674 [0064]: the size of the zone would dictate how many blocks are allocated, for a small zone, the number of blocks allocated could be one).
5. The memory system according to claim1, wherein the controller is further configured to: upon the first block group being assigned as a write destination, allocate the second block from the plurality of blocks dedicatedly to the first block group (see SHIN-674 [0078]-[0080]: write buffer is divided into regions, each regions corresponding to an open zone, the size of the region is equal to the amount of data programmed at once, multiple zones can be open at the same time, a first block group could be zone 1); upon a second block group among the plurality of block groups being assigned as a write destination, allocate at least one third block from the plurality of blocks dedicatedly to the second block group (see SHIN-674 [0078]-[0080]: write buffer is divided into regions, each regions corresponding to an open zone, the size of the region is equal to the amount of data programmed at once; multiple zones can be open at the same time, a second block group could be zone 2), data being to be written to the third block in units of the second minimum write size (see SHIN-674 [0106]: data being temporarily stored in SLC); and upon a total size of fourth data associated with one or more second write commands reaching the second minimum write size (see BENISTY [0033]: accumulation of a transfer size of data), each of the one or more second write commands being received from the host and specifying an identifier corresponding to the second block group, write, to the third block, fifth data which is at least part of the fourth data and has a size of the second minimum write size (see SHIN-674 [0106]: write request from host for a zone is received, data is temporarily stored in the SLC buffer; [0065]-[0070]: zones are mapped to the memory, for example TLC blocks, therefore write data from the host is directed to the identified zone, but temporarily stored in SLC; [0065]: host provides a program command with program data and identification information regarding a zone).
6. The memory system according to claim 1, wherein each of the plurality of blocks includes a plurality of memory cells, and the controller is configured to: write N-bits data to each of the plurality of memory cells included in the one of the one or more first blocks included in the first block group (see SHIN-674 [0102]: TLC cells); and write M-bits data to each of the plurality of memory cells included in the second block, M being smaller than N (see SHIN-674 [0102]: SLC cells, 1 bit is less than 3).
11. SHIN-674 discloses A method of controlling a nonvolatile memory, the nonvolatile memory including a plurality of blocks (see [0099]: memory device includes a plurality of dies including non-volatile memory cells; [0102]: plurality of memory blocks), each of the plurality of blocks being a unit for a data erase operation (see [0101]: memory block is a group of cells erased together), the method comprising: managing a plurality of block groups, each of the plurality of block groups including one or more first blocks among the plurality of blocks, data being to be written to each of the one or more first blocks in units of a first minimum write size (see [0102]: MLC blocks); managing at least one second block among the plurality of blocks, data being to be written to the second block in units of a second minimum write size smaller than the first minimum write size (see [0102]: SLC blocks); determining that a total size of first data associated with one or more first write commands reaches the second minimum write size (see BENISTY below), each of the one or more first write commands being received from a host and specifying an identifier corresponding to a first block group among the plurality of block groups; in response to determining that the total size of first data reaches the second minimum write size, writing, to the second block, second data which is at least part of the first data and has a size of the second minimum write size (see [0106]: write request from host for a zone is received, data is temporarily stored in the SLC buffer; [0065]-[0070]: zones are mapped to the memory, for example TLC blocks, therefore write data from the host is directed to the identified zone, but temporarily stored in SLC; [0065]: host provides a program command with program data and identification information regarding a zone); determining that a total size of one or more pieces of the second data written to the second block reaches the first minimum write size; in response to determining that the total size of the one or more pieces of the second data reaches the first minimum write size (see [0070]: data is accumulated in SLC until reaching the program size for TLC blocks), reading, from the second block, third data which includes the one or more pieces of the second data and has a size of the first minimum write size; and writing the third data to one of the one or more first blocks included in the first block group (see [0109]: read data from SLC buffer, configure unit of data to be programmed and then programs the memory unit).
BENISTY discloses the following limitations that are not disclosed by SHIN-674: upon a total size of first data associated with one or more first write commands reaching the second minimum write size write, to the second block, second data (see [0033]: data is accumulated to reach the data transfer size before performing write commands to the flash memory). Waiting until the aggregate data meets the minimum transfer size allows the system to take advantage of NAND parallelism (see [0033]). A combination of SHIN-674 and BENISTY would result in SHIN-674 waiting to accumulate a transfer size of data before writing to the second block.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SHIN-674 to perform a write upon a total size of data reaching the second minimum write size, as disclosed by BENISTY. One of ordinary skill in the art would have been motivated to make such a modification to take advantage of NAND parallelism, as taught by BENISTY. SHIN-674 and BENISTY are analogous/in the same field of endeavor as both references are directed to writing to flash memory.
12. The method according to claim 11, further comprising: managing a namespace that is divided into a plurality of zones (see SHIN-674 [0063]: namespace divided into a plurality of zones); and assigning the first block group to a first zone among the plurality of zones (see SHIN-674 [0064]: memory blocks are assigned to a zone), wherein each of the one or more first write commands specifies an identifier of the first zone as the identifier corresponding to the first block group (see SHIN-674 [0065]: host provides a program command with program data and identification information regarding a zone).
13. The method according to claim 11, wherein each of the plurality of block groups includes only one first block (see SHIN-674 [0064]: the size of the zone would dictate how many blocks are allocated, for a small zone, the number of blocks allocated could be one).
15. The method according to claim 11, further comprising: assigning the first block group as a write destination (see SHIN-674 [0065]: assign one or more blocks to a zone, such as zone 1); upon the first block group being assigned as a write destination, allocating the second block from the plurality of blocks dedicatedly to the first block group (see SHIN-674 [0078]-[0080]: write buffer is divided into regions, each regions corresponding to an open zone, the size of the region is equal to the amount of data programmed at once, multiple zones can be open at the same time, a first block group could be zone 1); assigning a second block group among the plurality of groups a write destination (see SHIN-674 [0065]: assign one or more blocks to a zone, such as zone 2); upon the second block group among the plurality of block groups being assigned as a write destination, allocating at least one third block from the plurality of blocks dedicatedly to the second block group (see SHIN-674 [0078]-[0080]: write buffer is divided into regions, each regions corresponding to an open zone, the size of the region is equal to the amount of data programmed at once; multiple zones can be open at the same time, a second block group could be zone 2), data being to be written to the third block in units of the second minimum write size (see SHIN-674 [0106]: data being temporarily stored in SLC); determining that a total size of fourth data associated with one or more second write commands reaches the second minimum write size (see BENISTY [0033]: accumulation of a transfer size of data), and in response to determining that the total size of fourth data reaches the second minimum write size, writing, to the third block, fifth data which is at least part of the fourth data and has a size of the second minimum write size (see SHIN-674 [0106]: write request from host for a zone is received, data is temporarily stored in the SLC buffer; [0065]-[0070]: zones are mapped to the memory, for example TLC blocks, therefore write data from the host is directed to the identified zone, but temporarily stored in SLC; [0065]: host provides a program command with program data and identification information regarding a zone).
16. The method according to claim 11, wherein each of the plurality of blocks includes a plurality of memory cells (see SHIN-674 [0101]: memory block includes a plurality of memory cells), N-bits data is written to each of the plurality of memory cells included in the one of the one or more first blocks included in the first block group, and M-bits data is written to each of the plurality of memory cells included in the second block, M being smaller than N (see SHIN-674 [0102]: SLC cells, 1 bit is less than 3).
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHIN-674 (U.S. Patent Application Publication #2021/0263674) and BENISTY (U.S. Patent Application Publication #2021/0409038) as applied to claims 1-3, 5, 6, 11-13, 15 and 16 above, and further in view of SIMIONESCU (U.S. Patent Application Publication #2020/0387449).
4. The memory system according to claim 1 (see SHIN-674 above), wherein the controller is further configured to: in response to receiving, from the host, a first read command that specifies the identifier corresponding to the first block group and requests to read at least part of the first data after the part of the first data is written to the second block and before the part of the first data is written to the one of the one or more first blocks included in the first block group, read the part of the first data from the second block (see SIMIONESCU below).
SIMIONESCU discloses the following limitations that are not disclosed by SHIN-674: in response to receiving, from the host, a first read command that specifies the identifier corresponding to the first block group and requests to read at least part of the first data after the part of the first data is written to the second block and before the part of the first data is written to the one of the one or more first blocks included in the first block group, read the part of the first data from the second block (see [0029]: if a read operation targets data that is part of an in-flight write operation, the data is fetched from the write buffer). SHIN-674 discloses storing data to an SLC buffer (the second block) before ultimately writing the data to TLC blocks. This data in the SLC buffer would be considered an in-flight write operation since the write data has not yet reached the final destination specified by the host (zone associated with the TLC blocks). A combination of SHIN-674 and SIMIONESCU would result in the system detecting the write data in the SLC cache as overlapping with a read request, and provide data from the SLC cache to satisfy the read operation. Managing storage commands out of order in this manner can improve the performance of the memory system (see [0019]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SHIN-674 to provide the read data from the second blocks, as disclosed by SIMIONESCU. One of ordinary skill in the art would have been motivated to make such a modification to improve performance of the memory system, as taught by SIMIONESCU. SHIN-674 and SIMIONESCU are analogous/in the same field of endeavor as both references are directed to buffering data and processing read/write commands.
14. The method according to claim 11 (see SHIN-674 above), further comprising: receiving, from the host, a first read command that specifies the identifier corresponding to the first block group and requests to read at least part of the first data after the part of the first data is written to the second block and before the part of the first data is written to the one of the one or more first blocks included in the first block group; and in response to the first read command, reading the part of the first data from the second block (see SIMIONESCU below).
SIMIONESCU discloses the following limitations that are not disclosed by SHIN-674: receiving, from the host, a first read command that specifies the identifier corresponding to the first block group and requests to read at least part of the first data after the part of the first data is written to the second block and before the part of the first data is written to the one of the one or more first blocks included in the first block group, read the part of the first data from the second block (see [0029]: if a read operation targets data that is part of an in-flight write operation, the data is fetched from the write buffer). SHIN-674 discloses storing data to an SLC buffer (the second block) before ultimately writing the data to TLC blocks. This data in the SLC buffer would be considered an in-flight write operation since the write data has not yet reached the final destination specified by the host (zone associated with the TLC blocks). A combination of SHIN-674 and SIMIONESCU would result in the system detecting the write data in the SLC cache as overlapping with a read request, and provide data from the SLC cache to satisfy the read operation. Managing storage commands out of order in this manner can improve the performance of the memory system (see [0019]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SHIN-674 to provide the read data from the second blocks, as disclosed by SIMIONESCU. One of ordinary skill in the art would have been motivated to make such a modification to improve performance of the memory system, as taught by SIMIONESCU. SHIN-674 and SIMIONESCU are analogous/in the same field of endeavor as both references are directed to buffering data and processing read/write commands.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHIN-674 (U.S. Patent Application Publication #2021/0263674) and BENISTY (U.S. Patent Application Publication #2021/0409038) as applied to claims 1-3, 5, 6, 11-13, 15 and 16 above, and further in view of SHIN-202 (U.S. Patent Application Publication #2021/0365202).
7. The memory system according to claim 1 (see SHIN-674 above), wherein the controller is further configured to: in response to completion of the writing of the second data to the second block, transmit, to the host, at least one completion response indicating completion of at least one of the one or more first write commands (see SHIN-202 below).
SHIN-202 discloses the following limitations that are not disclosed by SHIN-674: in response to completion of the writing of the second data to the second block, transmit, to the host, at least one completion response indicating completion of at least one of the one or more first write commands (see [0042]: upon completion of programming in the SLC buffer, the system can return a program complete response to the host). SHIN-674 already discloses a program operation can be considered complete when data is stored in the SLC buffer. But SHIN-674 does not mention transmitting a response to the host. SHIN-202 notifies the host that programming is complete when data has been programmed in the SLC buffer. This allows the host to provide another request and increase overall program operation speed (see [0042]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SHIN-674 to send a response to the host, as disclosed by SHIN-202. One of ordinary skill in the art would have been motivated to make such a modification to increase overall program operation speed, as taught by SHIN-202. SHIN-674 and SHIN-202 are analogous/in the same field of endeavor as both references are directed to flash memory systems.
17. The method according to claim 11 (see SHIN-674 above), further comprising: in response to completion of the writing of the second data to the second block, transmitting, to the host, at least one completion response indicating completion of at least one of the one or more first write commands (see SHIN-202 below).
SHIN-202 discloses the following limitations that are not disclosed by SHIN-674: in response to completion of the writing of the second data to the second block, transmit, to the host, at least one completion response indicating completion of at least one of the one or more first write commands (see [0042]: upon completion of programming in the SLC buffer, the system can return a program complete response to the host). SHIN-674 already discloses a program operation can be considered complete when data is stored in the SLC buffer. But SHIN-674 does not mention transmitting a response to the host. SHIN-202 notifies the host that programming is complete when data has been programmed in the SLC buffer. This allows the host to provide another request and increase overall program operation speed (see [0042]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SHIN-674 to send a response to the host, as disclosed by SHIN-202. One of ordinary skill in the art would have been motivated to make such a modification to increase overall program operation speed, as taught by SHIN-202. SHIN-674 and SHIN-202 are analogous/in the same field of endeavor as both references are directed to flash memory systems.
Claim(s) 8-10 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SHIN-674 (U.S. Patent Application Publication #2021/0263674) and BENISTY (U.S. Patent Application Publication #2021/0409038) as applied to claims 1-3, 5, 6, 11-13, 15 and 16 above, and further in view of SHARMA (U.S. Patent Application Publication #2022/0342585) and BARNDT (U.S. Patent Application Publication #2020/0194064).
8. The memory system according to claim 1 (see SHIN-674 above), wherein the controller is configured to: write the third data, which has been read from the second block, to the one of the one or more first blocks included in the first block group by a first- step write operation, the first-step write operation being one step of a multi-step write operation that includes at least the first-step write operation and a second-step write operation, the first-step write operation including writing the third data to the one of the one or more first blocks included in the first block group, the second- step write operation including writing the third data again to the one of the one or more first blocks included in the first block group (see SHARMA and BARNDT below).
SHARMA discloses the following limitations that are not disclosed by SHIN-674: write the third data, which has been read from the second block, to the one of the one or more first blocks included in the first block group by a first- step write operation (see [0061]: sense data from SLC and perform a foggy program operation to a QLC block), the first-step write operation being one step of a multi-step write operation that includes at least the first-step write operation and a second-step write operation (see [0061]: foggy-fine programming is a two-step programming operation), the first-step write operation including writing the third data to the one of the one or more first blocks included in the first block group (see [0061]: foggy programing to the QLC blocks), the second- step write operation including writing the third data again to the one of the one or more first blocks included in the first block group (see [0061]: fine programming to the QLC block). SHIN-674 already discloses migrating data from SLC to either TLC or QLC blocks. Therefore, the foggy-fine programming operation disclosed by SHARMA would be compatible with the system disclosed by SHIN-674. Foggy-fine programming can produce the best end result for bit error rate after fine programming (see BARNDT [0012]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SHIN-674 to perform a two-step programming operation, as disclosed by SHARMA. One of ordinary skill in the art would have been motivated to make such a modification to produce a best end result, as taught by BARNDT. SHIN-674, SHARMA and BARNDT are analogous/in the same field of endeavor as both references are directed to storing data in flash memory systems.
9. The memory system according to claim 8, wherein the controller is further configured to: in executing the second-step write operation for the third data, read the third data again from the second block, and write the third data, which has been read again from the second block, again to the one of the one or more first blocks included in the first block group by the second-step write operation (see SHARMA [0061]: during the foggy operation data is sensed from the SLC, and during the fine operation data is again sensed from the SLC).
10. The memory system according to claim 8, further comprising a buffer, wherein the controller is further configured to: store the third data, which has been read from the second block, in the buffer (see SHARMA [0069]: determine if the data is stored in the SLC block or RAM); and in executing the second-step write operation for the third data, read the third data from the buffer without reading the third data again from the second block, and write the third data, which has been read from the buffer, again to the one of the one or more first blocks included in the first block group by the second-step write operation (see SHARMA [0071]: toggle operation to read the data from either the SLC block or the RAM to perform the foggy and fine operations).
18. The method according to claim 11 (see SHIN-674 above), wherein the third data, which has been read from the second block, is written to the one of the one or more first blocks included in the first block group by a first-step write operation, the first-step write operation being one step of a multi-step write operation that includes at least the first-step write operation and a second-step write operation, the first-step write operation including writing the third data to the one of the one or more first blocks included in the first block group, the second-step write operation including writing the third data again to the one of the one or more first blocks included in the first block group (see SHARMA and BARNDT below).
SHARMA discloses the following limitations that are not disclosed by SHIN-674: write the third data, which has been read from the second block, to the one of the one or more first blocks included in the first block group by a first- step write operation (see [0061]: sense data from SLC and perform a foggy program operation to a QLC block), the first-step write operation being one step of a multi-step write operation that includes at least the first-step write operation and a second-step write operation (see [0061]: foggy-fine programming is a two-step programming operation), the first-step write operation including writing the third data to the one of the one or more first blocks included in the first block group (see [0061]: foggy programing to the QLC blocks), the second- step write operation including writing the third data again to the one of the one or more first blocks included in the first block group (see [0061]: fine programming to the QLC block). SHIN-674 already discloses migrating data from SLC to either TLC or QLC blocks. Therefore, the foggy-fine programming operation disclosed by SHARMA would be compatible with the system disclosed by SHIN-674. Foggy-fine programming can produce the best end result for bit error rate after fine programming (see BARNDT [0012]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SHIN-674 to perform a two-step programming operation, as disclosed by SHARMA. One of ordinary skill in the art would have been motivated to make such a modification to produce a best end result, as taught by BARNDT. SHIN-674, SHARMA and BARNDT are analogous/in the same field of endeavor as both references are directed to storing data in flash memory systems.
19. The method according to claim 18, further comprising: in executing the second-step write operation for the third data, reading the third data again from the second block, and writing the third data, which has been read again from the second block, again to the one of the one or more first blocks included in the first block group by the second-step write operation (see SHARMA [0061]: during the foggy operation data is sensed from the SLC, and during the fine operation data is again sensed from the SLC).
20. The method according to claim 18, further comprising: storing the third data, which has been read from the second block, in a buffer (see SHARMA [0069]: determine if the data is stored in the SLC block or RAM); and in executing the second-step write operation for the third data, reading the third data from the buffer without reading the third data again from the second block, and writing the third data, which has been read from the buffer, again to the one of the one or more first blocks included in the first block group by the second-step write operation (see SHARMA [0071]: toggle operation to read the data from either the SLC block or the RAM to perform the foggy and fine operations).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KIM – 2023/0147477 – discloses pinning data to a turbo write buffer to improve read performance. See [0168]
NATARAJAN – 2019/0361614 – discloses copying data from SLC to a buffer and then from the buffer to QLC. See [0014]
KANNO – 2019/0332316 – discloses a multi-step write operation for flash memory. See [0078]-[0080]
LIU – 2019/0179698 – discloses using SLC as a write cache to prevent data loss due to a power failure. See [0087]
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2136