DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE WITH COMMANDS ISSUED TO BRIDGE CHIP.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the first command" in lines 16-17, 18 and 19. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the examiner is considering this as referring to the first signal of the claim.
Claim 7 recites the limitation "the first command" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the examiner is considering this as referring to the first signal of claim 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, US PGPub 2021/0132856, in view of McVay, US PGPub 2017/0116139.
With respect to claim 1, Chen teaches a host device comprising:
a plurality of terminals commonly connectable to a plurality of bridge chips via a plurality of signal lines (fig. 3, the NVM Command and Address bus, which is shown as a line in fig. 1, connecting the Bridge Controller 159 to the NVM I/F Bridge chips 150, 152, 154, 156 and 158. See pars. 45-49), the plurality of signal lines including data signal lines (pars. 45-46, the lines of the command/address bus may be considered data signal lines), each of the bridge chips being connectable to a plurality of chips (par. 48 and fig. 1, each of the NVM I/F Bridge chips connected a plurality of nonvolatile memory chips, shown as NVM 170-178); and
a controller configured to issue a first command and transmit the first command via the data signal lines to the plurality of bridge chips, the first command including first address information that designates one of the plurality of bridge chips (par. 65, the command/address bus transaction that generates a Chip Select for an interface bridge chip, the command/address bus transaction being the first part of the claimed first command) and second address information that designates one of the plurality of chips connected to the designated one of the bridge chips (par. 66, the NVM command/address bus transaction for accessing the NVM device, the NVM command/address bus transaction being the second part of the claimed first command. Par. 55 discloses the high order bits of the NVM address are used as chip selects for the NAND flash chip access).
Chen fails to teach wherein the controller is configured to swap an order in which the information contained in the first command is issued.
McVay teaches:
wherein the controller is configured to swap an order in which the information contained in the first command is issued (par. 29, the received command packets are rearranged into the correct order to form the command).
It would have been obvious to one of ordinary skill in the art, having the teachings of Chen and McVay before him before the earliest effective filing date, to modify the memory access system of Chen with the memory access system of McVay, in order to provide the added flexibility and control provided by the command packet structure, which allows the host to manipulate the apparatus at levels that the NVM protocol may not allow, as taught by McVay in par. 29.
With respect to claim 2, Chen and McVay teach the limitations of the parent claim. Chen further teaches the host device according to claim 1, wherein the controller issues the second address information after issuing the first address information (pars. 65-66, the NVM command/address bus transaction is issued by the controller following the command/address bus transaction).
With respect to claim 3, Chen and McVay teach the limitations of the parent claim. Chen further teaches the host device according to claim 2, wherein the first address information transmitted via the data signal lines causes the controller to issue the second address information and then causes the controller to generate a second command (par. 66, the second command is the latched NVM command for NVM access).
With respect to claim 4, Chen and McVay teach the limitations of the parent claim. Chen further teaches the host device according to claim 3, wherein the first address information transmitted via the data signal lines causes the controller to transmit the second command to one of the plurality of the memory chips (par. 66, the NVM command is sent to the NVM).
With respect to claim 5, Chen and McVay teach the limitations of the parent claim. Chen further teaches the host device according to claim 2, wherein the first address information transmitted via the data signal lines causes the designated one of the bridge chips to enable signal transmission to the plurality of chips connected thereto, and non-designated bridge chips to disable signal transmission to the plurality of chips connected thereto (pars. 45-49, the read/write control is used to subsequently issue the command and address to the applicable bridge chip with the NVM associated with the address).
With respect to claim 6, Chen teaches a bridge chip comprising:
a controller that controls a bridge chip (par. 35 and fig. 1, bridge controller 159);
a first plurality of terminals connected to a host (par. 28 and fig. 1, command/address bus 119); and
a second plurality of terminals connected to a plurality of chips (pars. 66-67 and fig. 1, the connection between the NVM I/F bridge chips 150-158 and the NVMs 170-178), wherein
the first plurality of terminals connected to the host includes a first terminal that receives a first signal (par. 65 and fig. 1, the controller 159 is attached to the host through the command/address bus 119 and receives the command/address transaction, corresponding to the first signal),
the controller enables signal transmission to at least one of the plurality of chips when the controller receives the first signal that designates the bridge chip (pars. 45-49, the read/write control is used to subsequently issue the command and address to the applicable bridge chip with the NVM associated with the address),
the controller disables signal transmission to the plurality of chips when the controller receives the first signal that does not designate the bridge chip (pars. 45-49, the read/write control is used to subsequently issue the command and address only to the applicable bridge chip with the NVM associated with the address),
Chen fails to teach that the controller generates a second command by rearranging the order of the information contained in the first command and sends the second command to one of the plurality of chips designated in the first command when the controller receives the first command.
McVay teaches:
the controller generates a second command by rearranging the order of the information contained in the first command and sends the second command to one of the plurality of chips designated in the first command when the controller receives the first command (par. 29, the received command packets are rearranged into the correct order before the command is performed at one of the flash memories).
It would have been obvious to one of ordinary skill in the art, having the teachings of Chen and McVay before him before the earliest effective filing date, to modify the memory access system of Chen with the memory access system of McVay, in order to provide the added flexibility and control provided by the command packet structure, which allows the host to manipulate the apparatus at levels that the NVM protocol may not allow, as taught by McVay in par. 29.
With respect to claim 7, Chen and McVay teach the limitations of the parent claim. Chen further teaches the bridge chip according to claim 6,
wherein the first command includes first address information specifying one of the plurality of bridge chips followed by second address information specifying one of the plurality of chips connected to the specified one of the bridge chips (pars. 65-66, the command/address bus transaction that generates a Chip Select for an interface bridge chip, corresponding to the first address information, followed by the NVM command/address bus transaction for accessing the NVM device, corresponding to the second address information. Par. 55 discloses the high order bits of the NVM address are used as chip selects for the NAND flash chip access),
McVay further teaches:
the second command includes the second address information followed by the first address information (pars. 24-25, the CCIDX byte contained in each respective command packet comprising the second and first address information).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. European Patent application EP 3511814 A1 discloses rearranging the write order in a set of data corresponding to a merged write command, similar to the swapping/rearranging the order of information in a command, as claimed in claims 1 and 6 of the present application. Keeler et al., US PGPub 2009/0094389 discloses using a chip select signal to choose a bridge chip. WO 2012058151 A1 discloses a storage system using SATA bridge chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Prosecution Insights