DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on 12/12/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it is unclear what is meant by “incrementing the port's address register by a port's stride register”, and “checking to see if the increment count is greater than or equal to a port's length register” because it is unclear how to increment one register, which is a physical device, by another register, which is another physical device; and checking an increment count, i.e., a value, being greater than a register, which is a physical device. In addition, it is unclear how to check whether the increment count is greater than or equal to a port’s length register because port’s length register is not a value.
The following art rejection is based on the best understanding In view of 112(b) issues as set forth above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara et al. (US 5,590,353, hereinafter Sakakibara) in view of Simmons (US 2009/0132751 A1).
Regarding claim 1, Sakakibara discloses a method as shown in figure 5 comprising: (a) checking for a read port start signal and when received setting an increment count to zero (col. 15 line 63 through col. 16 line 10, initial value of this counter 191-3 is zero upon every reception of the set of the store data); (b) initiating a memory read using a port's address register, and setting the increment count to increment count + 1 (col. 16 lines 10-11, content of this counter 191-3 is incremented by one every time the access request REQ is issued); (c) incrementing the port's address register by a port's stride register (col. 16 lines 15-18, the desired address ADDji can be calculated in accordance with the previously mentioned expression (4) through cooperation of the multipliers 191-5, 191-7 and the adders 191-6, 191-8). Sakakibara differs from the claimed invention in not specifically disclosing (d) checking to see if the increment count is greater than or equal to a port's length register and when not so proceeding to (b); and (e) checking to see if the increment count is greater than or equal to a port's length register and when so proceeding to (a). However, Simmons teaches a controller having an address register being coupled with a controllable auto-increment unit incrementing the address in register after an access to register bank has been completed and including wrap around function which resets the address in register to zero once the end address of register bank has been reached ([0020]) in order to set increment count is set to increment count + 1 in the register when the end address of register bank has not been reached and to reset the address in register to zero when the end address is reached. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakakibara in having (d) checking to see if the increment count is greater than or equal to a port's length register and when not so proceeding to (b); and (e) checking to see if the increment count is greater than or equal to a port's length register and when so proceeding to (a), as per teaching of Simmons, to provide fast read and write access.
Regarding claim 2, Simmons teaches resetting the port's address register to an original value ([0020], resets the address in register 240 to 0x0000) in order to provide fast read and write access.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Aimoto et al. (US 6,870,854 A1) discloses a value greater than the quotient of division of the capacity of the whole common buffer memory by the number of ports can be set as the set value of the FIFO buffer length threshold register corresponding to the used quantity of the buffer for each port in the case of the FIFO buffer length counter (col. 12 line 30 through col. 13 line 58).
Beard et al. (US 5,598,547) discloses an operation of the VVC registers and logic to control access to the register unit to read data from the vector registers element-by-element during instruction execution (col. 16 lines 1-28).
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/ZHUO H LI/ Primary Examiner, Art Unit 2133