Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 13 and 14 are objected to because of the following informalities: the limitation "The clock signal detection circuit" in line 1 appears to be “The electronic device”. Appropriate correction is required.
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jing (US 2008/0238508 A1, hereinafter referred to as Jing).
Regarding claim 1, Jing discloses a clock signal (input clock) detection circuit (title; abstract; Figs. 2-3), comprising:
a first input configured to receive an always-on clock signal (internal PLL clock signal C from the VCO/NCO 142, divided by first frequency divider 140 to produce signal B; para 0010; the internal PLL clock signal C continues to run independently and serves as the sampling/reference clock);
a second input configured to receive an activatable clock signal (input clock signal 100 / INCLK supplied to the PLL, whose loss/absence is to be detected; abstract; para 0011, 0016-0018);
an output configured to produce a clock detection signal (signal F indicating loss of INCLK, asserted high when the input clock is absent; paras 0011-0018);
a detection flip-flop circuit (first delay flip-flop with reset function DFFR 162 in the cascade of digital logic circuits 160; paras 0011-0016) having:
a data input terminal configured to receive an always-high logic signal (logic input connected to Vdd / logic 1; paras 0011, 0013);
a clock terminal configured to receive the always-on clock signal (clock input connected to signal B from the frequency divider 140 of the internal PLL clock; para 0010]);
a reset terminal configured to receive a reset signal (reset input /R connected to first time-delayed signal A derived from INCLK; paras 0012-0016);
a data output terminal configured to produce an asynchronous clock detection signal (Q output of DFFR 162, which becomes high when INCLK is absent; para 0011).
The reset signal (A) is asserted (driven low, active-low reset) to reset the detection flip-flop circuit in response to the activatable clock signal (INCLK) being asserted/present (producing low pulses on A via the time-delay circuit 110, forcing all DFFR outputs low; para 0015).
The reset signal is de-asserted (driven/stays high, inactive) to prevent reset of the detection flip-flop circuit in response to the activatable clock signal being de-asserted/absent (no transitions on INCLK 100 A remains constantly high - no clearing; para 0014).
When the activatable clock is absent, the asynchronous clock detection signal (Q of the first DFFR 162, or propagated through the chain) is passed to the output to provide the clock detection signal which is asserted (high) when the activatable clock signal is absent (exactly as described in operation: after the first positive edge of B when A is high, Q goes high and indicates loss; paras 0011, 0014).
Regarding claim 5, Jing discloses a first synchronization flip-flop circuit (second DFFR 164 in the cascade) having:
data input terminal configured to receive the asynchronous clock detection signal (D input connected to Q output of the preceding/first DFFR 162; paras 0012, 0015);
clock terminal configured to receive the always-on clock signal (same signal B; internal PLL clock signal C from the VCO/NCO 142, divided by first frequency divider 140 to produce signal B; para 0010);
a data output terminal configured to produce a first synchronous clock detection signal (its Q output).
This first synchronous signal is passed toward the final output (signal F) as the clock detection signal (paras 0011, 0012, 0018).
Regarding claim 7, Jing discloses a first synchronization flip-flop circuit (second DFFR 164 in the cascade) having:
a data input terminal configured to receive the asynchronous clock detection signal (D input connected to Q output of the preceding/first DFFR 162; paras 0012, 0015);
a clock terminal configured to receive the always-on clock signal (same signal B; internal PLL clock signal C from the VCO/NCO 142, divided by first frequency divider 140 to produce signal B; para 0010);
a data output terminal configured to produce a first synchronous clock detection signal (its Q output).
The reference discloses a second synchronization flip-flop circuit (third/Nth DFFR 166 in the cascade) having: a data input terminal configured to receive the first synchronous clock detection signal (from the preceding DFFR); a clock terminal configured to receive the always-on clock signal (same B); a data output terminal configured to produce a second synchronous clock detection signal (its Q output).
The second (final) synchronous clock detection signal is passed to the output to provide the clock detection signal (signal F from the Nth DFFR; paras 0011, 0012, 0018).
Method claim 15 is essentially the same in scope as apparatus claims as discussed above and is rejected similarly.
Allowable Subject Matter
Claims 9-14 are allowed. The following is a statement of reasons for the indication of allowable subject matter: the best prior art of record, Jing, taken alone or in combination of other references, does not teach or fairly suggest an electronic device comprising, among other things: a first logic circuit clocked by an always-on clock signal; a second logic circuit clocked by an activatable clock signal; a communication interface coupled to said first logic circuit and to said second logic circuit and configured to pass a request signal from the first logic circuit towards the second logic circuit and to pass an acknowledge signal from the second logic circuit towards the first logic circuit, as set forth in the claims.
Claims 2-4, 6, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Holden (US 2005/0140398 A1) discloses clock failure monitor circuit employing counter pair to indicate clock failure within two pulses. Daijo (US 2005/0140398 A1) discloses clock switching circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 5712728048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL D CHANG/Primary Examiner, Art Unit 2844