DETAILED ACTION
This Office action is in response to the amendment of 1/22/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Blott et al. (US 2016/0217835 A1) hereinafter Blott et al. in view of Li et al. (US 2018/0267706 A1) hereinafter Li et al.
Regarding claim 1, Blott et al. teaches a system, comprising:
a host (an application having a plurality of processing elements 404-412, Paragraphs [0030]-[0031]); and
a memory system coupled to the host, the memory system comprising: a plurality of memory devices (a plurality of available memories 207 for reading or writing data Paragraph [0031]) … including a second memory device that is a non-volatile memory device (memory devices can include SSDs, which are non-volatile memory Paragraph [0040]); and
a controller coupled to the plurality of memory devices (memory control circuit 203 is coupled to the memory devices where the first and second types of memory can be NAND and SSD memories, see Fig. 2), wherein the host is configured to:
determine a type of characteristic set of each of a plurality of memory objects to be written to one of the plurality of memory devices, wherein the type of characteristic set indicates one of a key or a value associated with each of the plurality of memory objects; and send each of the plurality of memory objects to the memory system to be stored in one of the plurality of memory devices based on the determined type of characteristic set (the data accessed or stored in a key-value store is divided into 2 portions, where the value portion that consists of multiple page sizes is stored in the SSD while the remaining key portion is stored in DRAM Paragraphs [0058]-[0060]).
Blott et al. does not appear to explicitly teach, however, Li et al. teaches wherein the plurality of memory devices including a first memory device that is an emerging memory device (the first memory device may be comprised of a byte-addressable write-in-place memory such as a three-dimensional (3D) Xpoint (crosspoint) memory Paragraph [0034]); and wherein an address space corresponding to the emerging memory device and the non-volatile memory device, and to which each of the plurality of memory objects is to be written, is a contiguous address space across the emerging memory device and the non-volatile memory device (the hybrid storage device comprised of the first and second memory devices are presented as a single contiguous logical address storage space to the file system Paragraph [0024]).
The disclosures of Blott et al. and Li et al., hereinafter BL, are analogous art to the claimed invention because they are in the same field of reading/writing data in a hybrid memory system. Because both BL teach the use of utilizing different types of memory (e.g., SSDs or DRAMs of Blott et al.), it would have been obvious to one skilled in the art to substitute one type of memory for another to achieve the predictable result of availability of key data stored in the particular type of memory contiguous with the second non-volatile memory device as disclosed by Li et al., in this case, 3D crosspoint memory which is contiguous with the second non-volatile memory device (KSR, MPEP 2143).
Regarding claim 2, BL teaches all of the features with respect to claim 1, as outlined above.
Blott et al. further teaches wherein the controller is configured to store, in the first memory device, a first memory object of the plurality of memory objects that is associated with a first type of characteristic set that indicates the key (the data accessed or stored in a key-value store is divided into 2 portions, where the remaining key portion is stored in DRAM Paragraphs [0058]-[0060]), and Li et al. teaches wherein the first memory device is a three-dimensional (3-D) cross-point memory device (the first memory device may be comprised of a byte-addressable write-in-place memory such as a three-dimensional (3D) Xpoint (crosspoint) memory Paragraph [0034]).
Regarding claim 3, BL teaches all of the features with respect to claim 1, as outlined above.
Blott et al. further teaches wherein the controller is configured to store, in the second memory device, a memory object of the plurality of memory objects that is associated with a type of characteristic set that indicates a value, wherein the second memory device is a NAND memory device (the data accessed or stored in a key-value store is divided into 2 portions, where the value portion that consists of multiple page sizes is stored in the SSD Paragraphs [0058]-[0060], wherein the SSD is a NAND-based flash device Paragraph [0034]).
Regarding claim 6, BL teaches all of the features with respect to claim 1, as outlined above.
Blott et al. further teaches wherein the plurality of memory objects sent to the memory system to be stored in one of the plurality of memory devices based on the determined type of characteristic are sent using a particular protocol (various interfaces are used for receiving and outputting data, for example, SSDs can utilize a high speed interface such as SARA, SAS or PCIe Paragraphs [0055]-[0056]).
Claim(s 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over BL in further view of Kwon et al. (US 2018/0075236 A1) hereinafter Kwon et al.
Regarding claim 7, BL teaches all of the features with respect to claim 6, as outlined above.
BL does not appear to explicitly teach, however, Kwon et al. teaches wherein those memory objects that are sent to the first type of memory device are sent using a double-data rate (DDR) protocol (non-volatile memory may input and output data based on the DDR-T interface Paragraph [0115]).
The disclosures of BL and Kwon et al., hereinafter BLK, are analogous art to the claimed invention because they are in the same field of reading/writing data in a hybrid memory system. Because both BL teach the use of utilizing different types of communication protocols (e.g., SCSI or SATA of Blott et al.), it would have been obvious to one skilled in the art to substitute one type of memory for another to achieve the predictable result of availability of data stored using a particular type of protocol as disclosed by Kwon et al., in this case, DDR protocol (KSR, MPEP 2143).
Regarding claim 8, BLK teaches all of the features with respect to claim 7, as outlined above.
Kwon et al. further teaches wherein those memory objects that are sent to the second memory device are sent using a non-volatile memory express (NVME) protocol (data may be sent to the storage devices using a first communication protocol which may be an NVMe protocol Paragraphs [0096], [0107]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over BL in further view of Lim et al. (US 2013/0290462 A1) hereinafter Lim et al.
Regarding claim 9, BL teaches all of the features with respect to claim 1, as outlined above.
BL does not appear to explicitly teach, however, Lim et al. teaches wherein the memory system is within a cloud database (the memory system is communicatively coupled to a database, such as a cloud database that runs as a server Paragraphs [0010]-[0012]).
The disclosures of BL and Lim et al., hereinafter BLL, are analogous art to the claimed invention because they are in the same field of data storage in a hybrid memory and/or managing a key-value store.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of BLL before them, to modify the teachings of BL to include the teachings of Lim et al. since both BLL teach storing different data portions to different types of memory. Therefore it is applying a known technique (the memory system is within a cloud database [0010]-[0012] of Lim et al.) to a known device (diverting memory writes to different memory types based on a characteristic [0048]-[0049] of Blott et al.) ready for improvement to yield predictable results (the memory system is part of a cloud database system), KSR, MPEP 2143.
Claim(s) 10, 12 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2020/0333981 A1) hereinafter Liu et al. in view of Li et al. (US 2018/0267706 A1) hereinafter Li et al.
Regarding claim 10, Liu et al. teaches an apparatus, comprising:
a plurality of memory devices comprising a first memory device of a first type and a second memory device of second type wherein the first type and the second type are different (a hybrid memory system comprises a dynamic random access memory 200 and a non-volatile memory 300 Paragraph [0038]); and
a memory controller coupled to the plurality of memory devices, wherein the memory controller is configured to determine a type of characteristic set of a plurality of memory objects to be written to one of the first memory device or the second memory device (an access count of each memory object is monitored at an application level and access hotness information of each said memory object is obtained based on the access count Paragraph [0038]);
wherein, a memory object of the plurality of memory objects is associated with a respective key stored in the first memory device and a respective value stored in the first memory device or the second memory device, wherein a determination of where the value is stored is based on the determined type of characteristic set; wherein, the respective key indicates a location at which the memory object is stored and the respective value represents data associated with the memory object; and wherein the respective key and the respective value comprise a respective key-value pair (a memory object has corresponding key-value data Paragraph [0077], and each key-value pair has metadata indicating the storage address of its corresponding key-value data Paragraph [0053]); and
wherein the controller is further configured to: send the respective values of the plurality of memory objects to one of the first memory device or the second memory device to be stored; and send the respective keys of the plurality of memory objects to the first memory device (metadata is stored in DRAM alone while key-value data are stored in the DRAM/NVM hybrid memory pool, where its storage destination is dynamically adjusted by monitoring the access hotness information of all the memory objects, and the metadata includes a field for storing the storage address of the key-value data Paragraph [0081]).
Liu et al. does not appear to explicitly teach, however, Li et al. teaches wherein the plurality of memory objects are sent to the first memory device using a first protocol and to the second memory device using a different protocol (the requests are transmitted in a first memory device protocol used by the first memory device and in a second memory device protocol used by the second memory device, wherein the memory devices are different types of memory devices using different memory device protocols Paragraph [0061]); wherein a contiguous address space across from the first memory device and the second memory device is used for writing each of the plurality of memory objects (the hybrid storage device comprised of the first and second memory devices are presented as a single contiguous logical address storage space to the file system Paragraph [0024]).
The disclosures of Liu et al. and Li et al., hereinafter LL, are analogous art to the claimed invention because they are in the same field of reading/writing data in a hybrid memory system. Because both LL teach the use of utilizing different types of memory devices (e.g., DRAM/NVM of Liu et al.), it would have been obvious to one skilled in the art to substitute one type of memory and its respective memory device protocol for another to achieve the predictable result of availability of key data stored in the contiguous address space using a respective protocol as disclosed by Li et al., in this case, another memory device with a different protocol that is contiguous with the first memory device (KSR, MPEP 2143).
Regarding claim 12, LL teaches all of the features with respect to claim 10 as outlined above.
Liu et al. further teaches wherein the type of characteristic set indicates a frequency of access of each of the plurality of memory objects (an access count of each memory object is monitored at an application level and access hotness information of each said memory object is obtained based on the access count Paragraph [0038]).
Regarding claim 15, LL teaches all of the features with respect to claim 10 as outlined above.
Li et al. further teaches a host processor coupled to the memory controller (Fig. 1. Depicts processor cores 102 are coupled to controllers 128, 130 via a common interface 142 Paragraphs [0024]-[0025]).
Regarding claim 16, LL teaches all of the features with respect to claim 15 as outlined above.
Liu et al. further teaches wherein a first type of characteristic indicates a frequency of access that is greater than a frequency of access for a second type of characteristic set, the host processor is configured to send a memory object associated with the first type of characteristic set to the first memory device (memory objects can be associated with high access hotness or low access hotness, and key-value data of memory objects having relatively high access hotness is stored in the DRAM domain Paragraph [0006]), and Kwon et al. further teaches wherein the first memory device is a cross-point memory device (Fig. 12 depicts a first storage device which may be a 3D-Xpoint memory Paragraph [0032]).
Regarding claim 17, LL teaches all of the features with respect to claim 15 as outlined above.
Liu et al. further teaches wherein: the host processor is configured to send a memory object associated with the second type of characteristic set to the second memory device (memory objects can be associated with high access hotness or low access hotness, and key-value data of memory objects having relatively low access hotness is stored in the NVM domain Paragraph [0006]) and Kwon et al. teaches the second memory device is a NAND memory device (the non-volatile memory device may be a NAND flash memory Paragraph [0100]).
Claim(s) 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over LL in further view of Kwon et al. (US 2018/0075236 A1) hereinafter Kwon et al.
Regarding claim 11, LL teaches all of the features with respect to claim 10 as outlined above.
LL does not appear to explicitly teach, however, Kwon et al. teaches wherein the memory device of the first type is configured to communicate in accordance with a double-data rate (DDR) protocol (non-volatile memory may input and output data based on the DDR-T interface Paragraph [0115]); and the second memory device of the second type is configured to communicate in accordance with a non-volatile memory express (NVME) protocol (data may be sent to the storage devices using a first communication protocol which may be an NVMe protocol Paragraphs [0096], [0107]).
The disclosures of LL and Kwon et al., hereinafter LLK, are analogous art to the claimed invention because they are in the same field of reading/writing data in a hybrid memory system. Because both LLK teach the use of utilizing different types of communication protocols (e.g., a DRAM/NVM based protocol of Liu et al.), it would have been obvious to one skilled in the art to substitute one type of memory and its communication protocol for another to achieve the predictable result of availability of data stored using a particular type of protocol as disclosed by Kwon et al., in this case, DDR and NVMe protocols for the different memory devices (KSR, MPEP 2143).
Regarding claim 13, LL teaches all of the features with respect to claim 10 as outlined above.
Li et al. further teaches wherein first memory device is a ferroelectric random access memory (FeRAM) device (first memory device may be a ferroelectric random-access memory (FeTRAIVI) Paragraph [0034]).
LL does not appear to explicitly teach, however, Kwon et al. teaches the different protocol is a non-volatile memory express (NVME) protocol (data may be sent to the storage devices using a first communication protocol which may be an NVMe protocol Paragraphs [0096], [0107]).
The disclosures of LL and Kwon et al., hereinafter LLK, are analogous art to the claimed invention because they are in the same field of reading/writing data in a hybrid memory system. Because both LLK teach the use of utilizing different types of communication protocols (e.g., a DRAM/NVM based protocol of Liu et al.), it would have been obvious to one skilled in the art to substitute one type of memory and its communication protocol for another to achieve the predictable result of availability of data stored using a particular type of protocol as disclosed by Kwon et al., in this case, NVMe protocols for the different memory devices (KSR, MPEP 2143).
Claim(s) 18 are rejected under 35 U.S.C. 103 as being unpatentable over by Blott et al. (US 2016/0217835 A1) hereinafter Blott et al. in view of Hassan (US 2018/0024821 A1) hereinafter Hassan.
Regarding claim 18, Blott et al. teaches a method, comprising:
determining, via a controller, a type of characteristic set of each of a plurality of memory objects to be written to one of a plurality of memory devices of a memory system, wherein the type of characteristic set indicates one of a key or a value associated with each of the plurality of memory objects; and sending each of the plurality of memory objects to the memory system to be stored in one of the plurality of memory devices based on the determined type of characteristic set (the data accessed or stored in a key-value store is divided into 2 portions, where the value portion that consists of multiple page sizes is stored in the SSD while the remaining key portion is stored in DRAM Paragraphs [0058]-[0060]).
Blott et al. does not appear to explicitly teach, however, Hassan teaches wherein the type of characteristic set includes whether a memory access includes sequential or non-sequential accesses (objects are placed in a hybrid memory system based on the statistics file which includes data for each object that includes a sequential access count indicating a number of times an object was sequentially accessed and a random access count indicating whether an object is randomly accessed Paragraph [0003]).
The disclosures of Blott et al. and Hassan, hereinafter BH, are analogous art to the claimed invention because they are in the same field of reading/writing data in a hybrid memory system.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of BH before the effective filing date of the invention, to modify the teachings of Blott et al. by including wherein the type of characteristic set includes whether a memory access includes sequential or non-sequential accesses, as taught by Hassan.
One of ordinary skill in the art would have been motivated to include wherein the type of characteristic set includes whether a memory access includes sequential or non-sequential accesses because sequential vs. non-sequential objects benefit from being selectively placed on different types of memory (see [0021] of Hassan).
Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over BH in further view of Kwon et al. (US 2018/0075236 A1) hereinafter Kwon et al.
Regarding claim 19, BH teaches all of the features with respect to claim 18, as outlined above.
Blott et al. further teaches wherein the plurality of memory devices comprises a first memory device of a first type and a second memory device of a second type (the plurality of memories includes a first memory type 208 and second memory type 212, see Fig. 2), and wherein the method includes: storing, in the first memory device, a first memory object of the plurality of memory objects that is associated with a first type of characteristic set that indicates a key; and storing, in the second memory device, a memory object of the plurality of memory objects that is associated with a type of characteristic set that indicates a value, wherein the second memory device is a NAND memory device (the data accessed or stored in a key-value store is divided into 2 portions, where the value portion that consists of multiple page sizes is stored in the SSD while the remaining key portion is stored in DRAM Paragraphs [0058]-[0060], wherein the SSD is a NAND-based flash device Paragraph [0034]).
BH does not appear to explicitly teach, however, Kwon et al. teaches wherein the first memory device is a three-dimensional (3-D) cross-point memory device (non-volatile memory can be a 3D-Xpoint memory (e.g., 3D MRAM) Paragraph [0115]).
The disclosures of BH and Kwon et al., hereinafter BHK, are analogous art to the claimed invention because they are in the same field of reading/writing data in a hybrid memory system. Because both BK teach the use of utilizing different types of memory (e.g., SSDs or DRAMs of Blott et al.), it would have been obvious to one skilled in the art to substitute one type of memory for another to achieve the predictable result of availability of key data stored in the particular type of memory as disclosed by Kwon et al., in this case, 3D crosspoint memory (KSR, MPEP 2143).
Regarding claim 20, BH teaches all of the features with respect to claim 18, as outlined above.
Blott et al. further teaches wherein the method includes sending the plurality of memory objects to be stored in one of the plurality of memory devices using a particular protocol (various interfaces are used for receiving and outputting data, for example, SSDs can utilize a high speed interface such as SARA, SAS or PCIe Paragraphs [0055]-[0056]).
BH does not appear to explicitly teach, however, Kwon et al. teaches wherein those memory objects that are sent to memory devices of the first type are sent using a double-data rate (DDR) protocol (non-volatile memory may input and output data based on the DDR-T interface Paragraph [0115]); and wherein those memory objects that are sent to the memory devices of the second type are sent using a non-volatile memory express (NVME) protocol (data may be sent to the storage devices using a first communication protocol which may be an NVMe protocol Paragraphs [0096], [0107]).
The disclosures of BH and Kwon et al., hereinafter BHK, are analogous art to the claimed invention because they are in the same field of reading/writing data in a hybrid memory system. Because both BK teach the use of utilizing different types of communication protocols (e.g., SCSI or SATA of Blott et al.), it would have been obvious to one skilled in the art to substitute one type of memory for another to achieve the predictable result of availability of data stored using a particular type of protocol as disclosed by Kwon et al., in this case, DDR and NVMe protocols for the different memory devices (KSR, MPEP 2143).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 10-13 and 16-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-12 of U.S. Patent No. 12,141,465. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the parent application (see right column) teaches the claims of the instant application (see left column). It is noted that while the claims of the parent is a system and the claims of the instant application is an apparatus, the instant application merely applies the teaches to a different technological environment, and it would be obvious to derive the apparatus from a system comprising the apparatus.
Instant Application 18/938,813
US Patent No. 12,141,465
Parent Application 17/127,376
10. An apparatus, comprising:
a plurality of memory devices comprising a first memory device of a first type and a second memory device of second type wherein the first type and the second type are different; and
a memory controller coupled to the plurality of memory devices, wherein the memory controller is configured to determine a type of characteristic set of a plurality of memory objects to be written to one of the first memory device or the second memory device;
wherein, a memory object of the plurality of memory objects is associated with a respective key stored in the first memory device and a respective value stored in the first memory device or the second memory device, wherein a determination of where the value is stored is based on the determined type of characteristic set;
wherein, the respective key indicates a location at which the memory object is stored and the respective value represents data associated with the memory object; and
wherein the respective key and the respective value comprise a respective key-value pair; and
wherein the controller is further configured to:
send the respective values of the plurality of memory objects to one of the first memory device or the second memory device to be stored; and
send the respective keys of the plurality of memory objects to the first memory device; and
wherein the plurality of memory objects are sent to the first memory device using a first protocol and to the second memory device using a different protocol;
wherein a contiguous address space across the first memory device and the second memory device is used for writing each of the plurality of memory objects.
10. A system, comprising:
a host; and
a memory system coupled to the host, the memory system comprising:
a plurality of memory devices, the plurality of memory devices comprising a first memory device configured to communicate in accordance with a double-data rate (DDR) protocol and a second memory device configured to communicate in accordance with a non-volatile memory express (NVME) protocol; and
a controller coupled to the plurality of memory devices, wherein the controller is to: determine a type of characteristic set of a plurality of memory objects to be written to one of the first memory device or the second memory device, wherein:
the type of characteristic set indicates a frequency of access of each of the plurality of memory objects; and
a memory object of the plurality of memory objects is associated with a respective key stored in the first memory device and a respective value stored in the first memory device or the second memory device, wherein a determination of where the value is stored is based on the determined type of characteristic set;
the respective key indicates a location that the memory object is stored and the respective value represents data associated with the memory object; and
the respective key and the respective value comprise a respective key-value pair; and
send the respective values of the plurality of memory objects to one of the first memory device or the second memory device to be stored; and
send the respective keys of the plurality of memory objects to the first memory device;
wherein: an address space for writing each of the plurality of memory objects to in either of the first memory device or the second memory device is a contiguous address space across the first memory device and the second memory device; and
the plurality of memory objects are sent to the first memory device using the DDR protocol and to the second memory device using the NVME protocol.
11. The apparatus of claim 10, wherein the first memory device of the first type is configured to communicate in accordance with a double-data rate (DDR) protocol, and the second memory device of the second type is configured to communicate in accordance with a non-volatile memory express (NVME) protocol.
10. …
a plurality of memory devices, the plurality of memory devices comprising a first memory device configured to communicate in accordance with a double-data rate (DDR) protocol and a second memory device configured to communicate in accordance with a non-volatile memory express (NVME) protocol; …
12. The apparatus of claim 10, wherein the type of characteristic set indicates a frequency of access of each of the plurality of memory objects.
10. …
the type of characteristic set indicates a frequency of access of each of the plurality of memory objects
…
13. The apparatus of claim 10, wherein the first protocol is a double-data rate (DDR) protocol, and the second protocol is a non-volatile memory express (NVME) protocol.
10. …
the plurality of memory devices comprising a first memory device configured to communicate in accordance with a double-data rate (DDR) protocol and a second memory device configured to communicate in accordance with a non-volatile memory express (NVME) protocol…
16. The apparatus of claim 15, wherein: a first type of characteristic indicates a frequency of access that is greater than a frequency of access for a second type of characteristic set; the host processor is configured to send a memory object associated with the first type of characteristic set to the first memory device, and the first memory device is a cross-point memory device.
11. The system of claim 10, wherein: a first type of characteristic indicates a frequency of access that is greater than a frequency of access for a second type of characteristic set, the host is configured to send a memory object associated with the first type of characteristic set to the first memory device, and the first memory device is a cross-point memory device.
17. The apparatus of claim 15, wherein: the host processor is configured to send a memory object associated with the second type of characteristic set to the second memory device, and the second memory device is a NAND memory device.
12. The system of claim 11, wherein: the host is configured to send a memory object associated with the second type of characteristic set to the second memory device, and the second memory device is a NAND memory device.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10 of U.S. Patent No. 12,141,465, hereinafter Parent, in view of Lee et al. (US 2021/0191882 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the parent application (see right column) teaches the claims of the instant application (see left column).
Instant Application 18/938,813
US Patent No. 12,141,465
(Parent Application 17/127,376)
in view of Lee et al. (US 2021/0191882 A1)
15. The apparatus of claim 10, further comprising a host processor coupled to the memory controller.
Parent does not appear to explicitly teach, however, Lee et al. teaches a host processor coupled to the memory controller (host 200 may be implemented as an application processor and is coupled to controller 110 via storage device 100, see Figure 1, [0037]).
The disclosures of Parent and Lee et al., hereinafter PL, are analogous art to the claimed invention because they are in the same field of data storage in a hybrid memory and/or managing a key-value store.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of PL before them, to modify the teachings of Parent to include the teachings of Lee et al. since both PL teach storing different data portions to different types of memory. Therefore it is applying a known technique (a host processor is coupled to the memory controller of Lee et al.) to a known device of the Parent ready for improvement to yield predictable results (a host processor is coupled to the memory controller of Lee et al.), KSR, MPEP 2143.
Response to Arguments
Applicant’s arguments, with respect to the rejection(s) of the amended claim(s) 1 and 10 under 35 USC 102 have been fully considered. Upon further consideration, the prior art Li et al. (US 2018/0267706 A1) teaches the newly amended features of an emerging memory device and non-volatile memory device which form a contiguous address space (see rejection as outlined above).
Applicant’s arguments, with respect to the rejection(s) of the amended claim(s) 18 under 35 USC 103 have been fully considered. Upon further consideration, the prior art Hassan teaches the amended features of the characteristic set including non-sequential or sequential accesses (see rejection as outlined above.
Regarding the rejection of claims 10-13 ad 15-17, the newly amended claims are still rejected for Double Patenting with respect to the parent application(s). Refer to the updated mapping as outlined in the table above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANE W BENNER whose telephone number is (571)270-0067. The examiner can normally be reached Mon - Thurs (8 AM - 5 PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGINALD BRAGDON can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/ Primary Examiner, Art Unit 2139
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