DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/06/2024 was filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-9, 11-12, 15-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sudhakaran (US. Patent App. Pub. No. 2023/0327924).
As per claim 1, as shown in Fig. 13 and 14, Sudhakaran teaches a central processing unit for implementing a graphics processing pipeline which comprises a plurality of graphics processing tasks (¶ [133], “The graphics processing pipeline 1300 may be implemented via an application executed by a host processor, such as a CPU”), the central processing unit comprising:
one or more distinct graphics processing modules configured in dedicated hardware (¶ [103], further addressed below), wherein each of the one or more distinct graphics processing modules is configured to perform one of the graphics processing tasks of the graphics processing pipeline (Fig. 14, ¶ [139], CPU 14 1406 comprises plurality of processors 1412-1414 to perform the graphics pipeline 1300, Fig. 13 and recited in ¶ [133] above); and
an execution unit configured to execute instructions of an instruction set for implementing the graphics processing pipeline (see Fig. 14), wherein the execution unit (impliedly included) is configured to call each of the one or more distinct graphics processing modules (¶ [133], i.e., API calls) using a respective instruction of the instruction set (Fig. 14, instruction sets 1402 of respective processor 1412, 1414) to perform its respective graphics processing task of the graphics processing pipeline (¶ [139], independent processors).
Although Sudhakaran does not expressly teach the claimed dedicated hardware for the distinct graphics processing modules, in the configuration of the CPU 1406 employing the processors 1412, 1414, described in ¶ [139], implementing the graphics pipeline tasks shown in Fig. 13, ¶ [133]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the processors 1412, 1414 as the claimed dedicated hardware for executing instruction sets 1402 of respective processors to perform specific graphics processing tasks since the result is equivalently achieved.
As per claim 5, in the configuration of Fig. 4 and describe in ¶ [133], Sudhakaran does teaches wherein the central processing unit further comprises: a local memory (Fig. 8, local memory 804, ¶ [73]); wherein the execution unit is further configured to use the local memory when an associated one of the one or more distinct graphics processing modules is called (¶ [120]).
As per claim 6, as also shown in Fig. 8, and ¶ [120], Sudhakaran does teach wherein the local memory comprises a separate memory for each of the one or more distinct graphics processing modules.
As per claim 7, as addressed, Sudhakaran does teach wherein the instruction set architecture comprises instructions specific to each of the graphics processing modules that can be called by the execution unit (¶ [133], API calls as addressed above).
As per claim 8, as shown in Fig. 13, Sudhakaran does also teach wherein the one or more graphics processing tasks comprise one or more of: texture processing (¶ [124]), rasterization (¶ [122]), encoding, decoding, blending (¶ [134]), blitting, graphics state management, tessellation (¶ [126]), clip, cull, perspective divide, viewport transform (¶ [128]), scan conversion, hidden surface removal, multi-sampling, tiling, ray casting, ray tracing, compression, decompression, interpolation, gathering, format converting, memory management, texture mapping (¶ [130]), texture decoding, texture filtering, testing (¶ [131]), and post-processing.
As per claim 9, Sudhakaran also teaches wherein the one or more distinct graphics processing modules are configured in fixed function circuitry (¶ [134]).
As per claim 11, as addressed in claim 1, Sudhakaran impliedly teaches wherein the execution unit is further configured to receive an output from the one or more distinct graphics processing modules configured in dedicated hardware, wherein the output represents a result of the graphics processing task performed by the one or more distinct graphics processing modules.
Claim 12, which is similar in scope to claim 1 as addressed above, is thus rejected under the same rationale.
Claim 15, which is similar in scope to claim 5 as addressed above, is thus rejected under the same rationale.
Claim 16, which is similar in scope to claim 7 as addressed above, is thus rejected under the same rationale.
Claim 18, which is similar in scope to claim 11 as addressed above, is thus rejected under the same rationale.
Claim 19, which is similar in scope to claim 8 as addressed above, is thus rejected under the same rationale.
Claim 20, which is similar in scope to claim 1 as addressed above, is thus rejected under the same rationale.
Claims 2-4, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sudhakaran (US. Patent App. Pub. No. 2023/0327924) in view of Tao et al. (US. Patent App. Pub. No. 20210074239, “Tao”, hereinafter).
As per claim 2, Sudhakaran does not explicitly teach wherein the central processing unit is configured to perform one or more of the plurality of graphics processing tasks of the graphics processing pipeline without using a distinct graphics processing module configured in dedicated hardware.
However, Tao teaches a very similar method of processing graphics pipeline implemented on a CPU (see ¶ [22]), wherein the method further teaches the above feature, i.e., wherein the central processing unit is configured to perform one or more of the plurality of graphics processing tasks of the graphics processing pipeline without using a distinct graphics processing module configured in dedicated hardware (e.g., ¶ [33-34], by either removing the color transform or matrix stages. See the graphics pipeline in Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method as taught by Tao into the method as taught by Sudhakaran as addressed above, the advantage of which is to perform graphics processing tasks based on the hardware capabilities and availability of execution resources (¶ [35]).
As per claim 3, the combined teachings of Sudhakaran and Tao does substantially include wherein each of the one or more graphics processing tasks of the graphics processing pipeline that the respective one or more distinct graphics processing modules are configured to perform is at a level between a level of elemental mathematical functions and a level of a full draw call to a graphics processing unit (at best understood by the examiner as it is not clear what is meant by the claimed levels, thus interpreted as reducing the complexity of a LUT by reducing numeric precision or a number of entries in the LUT recited in ¶ [34] as taught by Tao). Thus, claim 3 would have been obvious over the combined references for the reason above.
As per claim 4, as addressed in claims 1 and 2 above, the combined Sudhakaran-Tao also impliedly teaches wherein the one or more graphics processing tasks of the graphics processing pipeline that the respective one or more distinct graphics processing modules are configured in dedicated hardware to perform are selected from the plurality of graphics processing tasks of the graphics processing pipeline based on an assessment of an improvement to the implementation of the graphics processing pipeline that would be achieved by performing the graphics processing task in a distinct graphics processing module configured in dedicated hardware compared to performing the graphics processing task without using a distinct graphics processing module configured in dedicated hardware (taught by Tao, ¶ [33-35], as addressed in claim 2, i.e., depending on the availability of the executing resources and hardware capability, the graphics processing is performed or not). Thus, claim 4 would have been obvious over the combined references for the reason above.
Claim 13, which is similar in scope to claim 2 as addressed above, is thus rejected under the same rationale.
Claim 14, which is similar in scope to claim 3 as addressed above, is thus rejected under the same rationale.
Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sudhakaran (US. Patent App. Pub. No. 2023/0327924) in view of Zhou et al., “RISC-V Graphics Rendering Instruction Set Extensions for Embedded AI Chips Implementation”, retrieved from ACM Digital Library, April, 2020, https://dl.acm.org/doi/pdf/10.1145/3378904.3378926, “Zhou”, hereinafter).
As per claim 10, Sudhakaran does not expressly teach wherein the instruction set is a RISC-V instruction set.
However, in a very similar method of processing graphics pipeline using a CPU (see page 3, Fig. 4), Zhou teaches this feature, i.e., the instruction set is a RISC-V instruction set (page 2, System Architecture, section 3.1 – 3.3, Table I, Fig. 2 and 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the method as taught by Zhou and apply to the method as taught by Sudhakaran as addressed above, the advantage of which is for lowering the power consumption while keeping high performance (page 2, left column, third paragraph).
Claim 17, which is similar in scope to claim 10 as addressed above, is thus rejected under the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hau H. Nguyen whose telephone number is: 571-272-7787. The examiner can normally be reached on MON-FRI from 8:30-5:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tammy Goddard, can be reached on (571) 272-7773.
The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAU H NGUYEN/Primary Examiner, Art Unit 2611
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