The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 3/11/2026.
Claims 6, 12 and 17-19 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Response to Arguments
Applicant`s arguments filed March 11, 2026 have been fully considered and they are persuasive with respect to prior art rejection.
As per the 103 rejection of claim 1, Applicant argued that Lercari, Li, and Yasui does not describe " transmit ... a control signal indicating a suspension of access activity to the first memory in response to transmitting the one or more read commands and the one or more write commands.", where applicant argued that Yasui's write suspend command fails to teach or suggest transmission of "a control signal indicating a suspension of access activity to the first memory in response to transmitting the one or more read commands and the one or more write commands," as recited in independent claim 1. For example, Yasui describes that the write suspend command is used to enable and execute read operations. See, e.g., id. [0019] and [0032] (emphasis added). That is, while Yasui describes that write operations may be suspended, Yasui describes that read access continues at the flash memory as a result of the write suspend command. See, e.g., id. [0019] and [0032]. Because Yasui describes that "access activity" continues to occur at the flash memory as a result the write suspend command, the write suspend command does not teach or suggest "a control signal indicating a suspension of access activity to the first memory," as recited in independent claim 1.
Moreover, Yasui also fails to describe that the write suspend command is transmitted "in response to transmitting the one or more read commands and the one or more write commands," as recited in independent claim 1. Yasui merely describes that the write suspend command is issued by the OS in response to a TLB error exception (e.g., an invalid memory state). See, e.g., id. [0032]. But absent from Yasui is any description of the write suspend command being issued in response to the transmission of "one or more read commands" and "one or more write commands," as recited in independent claim 1. Thus, Yasui does not teach or suggest "transmit . .. a control signal indicating a suspension of access activity to the first memory in response to transmitting the one or more read commands and the one or more write commands," as recited in independent claim 1 or overcome the deficiencies of Lercari.
However, Yasui discloses the present invention relates to a memory system including a flash memory, which suspends write to read data when receiving a suspend command during a write operation, to a memory read method, and to a program (Paragraph 0003), that teaches that when receiving a suspend command during a write operation, the flash memory 9 suspends the write operation to execute a read operation (Paragraph 0019), wherein the processing device sets the high priority flag based on the identification of the operation being a read request from the host; the TLB of the read-only area is turned off, and thereby, if the read operation collides with the write operation, a TLB error exception is generated. In this way, the OS 5 issues a suspend command, and the, supplies it to the flash memory. Therefore, the write operation is suspended, and thus, high-speed read is possible (Paragraph 0039); when a NOR flash memory 7 having a program suspend function is used, the application program 4 dose not directly accesses the flash memory 7 to execute a read operation. In this case, the device driver 6 executes the read operation with respect to the flash memory 7 (Paragraph 0044), where the disclosure of Yasui teaches a suspension operation based on write or read conditions during the write/read operation which triggers errors and suspend access activity to the memory to corresponds to the claimed limitation. In addition the claimed “access activity” does not explicitly include both write and read operations where it can be broadly interpreted as write operation access activity or read operation access activity or both.
Claim Rejections - 35 USC § 103
7.The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1, 5, 6, 9, 13-15 and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable by Lercari et al. (US 11,175,984) (hereinafter ‘Lercari’), in view of Li et al. (US PGPUB 2020/0218646 hereinafter referred to as Li), and further in view of Yasui et al. (US PGPUB 2009/0089488 hereinafter referred to as Yasui).
As per independent claim 1, Lercari discloses a memory system comprising: a first die; a second die; and a controller configured to control writing and reading of data to and from the first die and the second die, wherein the first die includes a first nonvolatile memory and a first volatile memory, and the second die includes a second nonvolatile memory and a second volatile memory, and the controller includes a third volatile memory, and the controller, during writing of data into the first die, stores the data in the third volatile memory, writes the data, which is stored in the third volatile memory and is to be stored in the first die, to the first volatile memory of the first die and the second volatile memory of the second die in parallel [(Column 4, lines 50-67, Column 5, lines 6-17, Column 15, lines 25-50, Column 35, lines 60-67 and Column 36, lines 1-56; Figs. 2C and 5C) where Lercari teaches FIG. 2C shows yet another implementation 241, with a host 243 and SSDs i-m, the latter respectively numbered 244-248. In this case however, instead of forwarding information to the next drive (as was the case with the embodiment in FIG. 2B), each drive forwards its data (or EC information) directly to the last SSD 248 and a direct communication among multiple drives by interconnect 582 without the involvement of the host such that each drive can thereafter send data to another drive pursuant to a move or copy, or EC information, without having to pass that data through the host. FIG. SC is used to further elaborate on peer-to-peer operations as introduced earlier. More specifically, FIG. 5C depicts two SSDs/drives, each having a controller 573/584 and respective memory 579/581 managed by that controller. each of the drives is interconnected by a peer-to-peer bus to permit drives to directly transfer information as might be commanded (575/576) by a host but permit drives to send requests to one another via a multidrop communication bus or via a network interface. to correspond to the claimed limitation].
Lercari does not appear to explicitly disclose transmit, based on receiving the inter-memory data movement command, one or more read commands to the second memory and one or more write commands to the first memory; transmit, via the second interface and based on a direction of data transfer being from the second memory to the first memory.
However, Li discloses transmit, based on receiving the inter-memory data movement command, one or more read commands to the second memory and one or more write commands to the first memory [(Paragraphs 0041-0043 and 0061; FIGs. 1 and 3) wherein Li discloses where the host (via CPU 302) can work with the SSDs (via, e.g., SSD controllers 332 and 342) to write the data to SSDs 330 and 340. For example, SSD controller 332 can obtain the placed write command from SQ 314, and execute the write command by writing data 312 to the NAND flash of SSD 330 (e.g., to a block 334 of the NAND flash of SSD 330). Similarly, SSD controller 342 can obtain another placed write command from SQ 314, and execute the other write command by writing (part of) data 312 to the NAND flash of SSD 340 (e.g., to a block 344 of the NAND flash of SSD 340). Writing data 312 to block 334 (via a communication 354) or to block 344 (via a communication 356) can be based on a direct memory access (DMA) protocol. Upon successfully executing the write command, SSD controller 332 can send to the host (via a communication 358) a complete notification, which can be a message which causes the host to place the completed command into CQ 314. Similarly, upon successfully executing the other write command, SSD controller 342 can send to the host (via a communication 360) a complete notification, can be a message which causes the host to place the completed command into CQ 314 for a read operation, host CPU 302 can send to FPGA 322 a read request and a query (via communication 350) to obtain the physical page address associated with the data to be read (e.g., data previously stored in block 344 of NAND flash of SSD 340 via communication 356). FPGA 322 can receive the read request and query (communication 350), and can determine and return to CPU 302 (via communication 350) the physical page address associated with the logical page address for the data to be read. CPU 302 can check the returned physical page address, and place in SQ 314 a command to read the requested data at the returned physical page address (via a communication 352). SSD controller 342 can obtain the placed read command from SQ 314, and execute the read command by reading data stored in block 344 of the NAND flash of SSD 340. Reading data from block 344 and placing it in DIMM 310 can be based on a DMA protocol. Upon successfully executing the read command, SSD controller 342 can send to the host (via a communication 360) a complete notification, which can be a message which causes the host to place the completed command into CQ 314 to correspond to the claimed limitation]; transmit, via the second interface and based on a direction of data transfer being from the second memory to the first memory [(Paragraphs 0043 and 0061; FIGs. 1 and 3) wherein Li discloses, for a read operation, host CPU 302 can send to FPGA 322 a read request and a query (via communication 350) to obtain the physical page address associated with the data to be read (e.g., data previously stored in block 344 of NAND flash of SSD 340 via communication 356). FPGA 322 can receive the read request and query (communication 350), and can determine and return to CPU 302 (via communication 350) the physical page address associated with the logical page address for the data to be read. CPU 302 can check the returned physical page address, and place in SQ 314 a command to read the requested data at the returned physical page address (via a communication 352). SSD controller 342 can obtain the placed read command from SQ 314, and execute the read command by reading data stored in block 344 of the NAND flash of SSD 340. Reading data from block 344 and placing it in DIMM 310 can be based on a DMA protocol. Upon successfully executing the read command, SSD controller 342 can send to the host (via a communication 360) a complete notification, which can be a message which causes the host to place the completed command into CQ 314 to correspond to the claimed limitation].
Lercari and Li are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lercari and Li before him or her, to modify the method of Lercari to include the sending of the indication based on the direction of data movement of Li because it will enhance data access.
The motivation for doing so would be [“improve the efficiency of the overall storage system” (Paragraph 0035 by Li)].
Lercari does not appear to explicitly disclose a control signal indicating a suspension of access activity to the first memory in response to transmitting the one or more read commands and the one or more write commands.
However, Yasui discloses a control signal indicating a suspension of access activity to the first memory in response to transmitting the one or more read commands and the one or more write commands [(Paragraphs 0015, 0019 and 0032; FIGs. 3-6) where there is provided a memory system comprising: a flash memory unit which suspends a write operation to execute a read operation when receiving a suspend command during a write operation; a CPU; an OS which includes a device driver; a TLB which has a page table for conversion from a virtual address to a physical address; and an application program which makes a TLB setting request with respect to the device driver when receiving a read command under the control of the CPU and the OS, acquires address information read from the page table of the TLB by the device driver in response to the setting request, and executes read directly with respect to the flash memory unit using the acquired address information without using the device driver. The memory system 100 further includes a flash memory 7, a read-only area 8 and a read/write area 9. When receiving a suspend command during a write operation, the flash memory 9 suspends the write operation to execute a read operation. The read-only area 8 and the read/write area 9 are used as a part of a memory area of the flash memory 7. However, in this case, the write operation is being executing as described later in FIG. 5, and the CPU 1 detects that the TLB of the read-only area 8 is in an off state (invalid), and thereby, a TLB error exception is generated. When detecting the TLB error exception (step S14), the OS 5 issues a write suspend command, and then, supplies it to the flash memory 7 (step S15). As a result, the flash memory 7 suspends the write operation. Thereafter, the OS 5 turns on the TLB 2 of the read-only area 8 (step S16). As a result, the CPU returns from the TLB error exception enable a read operation on the read-only area 8 to correspond to the claimed limitation].
Lercari and Yasui are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lercari before him or her, to modify the method of Lercari to include the access suspension policy of Yasui because it will enhance data access.
The motivation for doing so would be [“the read speed is intactly high speed, and response is improved” (Paragraph 0045 by Yasui)].
Lercari further teaches transfer the data from the second memory to the first memory based on transmitting the control signal [(Column 4, lines 50-67, Column 5, lines 6-17, Column 15, lines 25-50, Column 35, lines 60-67 and Column 36, lines 1-56; Figs. 2C and 5C) where Lercari teaches FIG. 5C depicts two SSDs/drives, each having a controller 573/584 and respective memory 579/581 managed by that controller. each of the drives is interconnected by a peer-to-peer bus to permit drives to directly transfer information as might be commanded (575/576) by a host but permit drives to send requests to one another via a multidrop communication bus or via a network interface; during system configuration, the host in this embodiment publishes to all controllers (e.g., controllers 573/584) routing information usable by each controller to directly access each other controller via a peer-to-peer bus, such as illustrated in the FIG. As commanded by the host, or as programmed by the host ( e.g., into an ASL register as will be discussed more fully below) each drive can thereafter send data to another drive pursuant to a move or copy, or EC information, without having to pass that data through the host. The host then determines, based on information sent to it by controller1 (i.e., associated metadata) that the "hot" data should instead be stored in memory2 581, which is part of a different drive and is managed by controller2 584. The host therefore transmits a command to controller1 to transfer the "hot" data directly to controller2, via peer-to-peer bus 582. Accordingly, controller1 573 sends a command and associated data and metadata via peer-to-peer bus 582 to controller2 584; as pertinent to the embodiment, the host can relay via controller1 573 logical, virtual or physical addresses or another form of index for memory2 581 that is to receive the data; (Column 4, lines 50-67, Column 5, lines 6-17, Column 15, lines 25-50, Column 35, lines 60-67 and Column 36, lines 1-56; Figs. 2C and 5C) where Lercari teaches FIG. 2C shows yet another implementation 241, with a host 243 and SSDs i-m, the latter respectively numbered 244-248. In this case however, instead of forwarding information to the next drive (as was the case with the embodiment in FIG. 2B), each drive forwards its data (or EC information) directly to the last SSD 248 and a direct communication among multiple drives by interconnect 582 without the involvement of the host such that each drive can thereafter send data to another drive pursuant to a move or copy, or EC information, without having to pass that data through the host. As a first example, it is assumed that controller 573 to correspond to the claimed limitation].
Therefore, it would have been obvious to combine Lercari, Yasui and Li to obtain the invention as specified in the instant claim.
As per dependent claim 5, Lercari discloses wherein the control signal indicates a duration for suspending access activity to the first memory, the duration being based on a first time value and a second time value [(Column 36, lines 52-67; Figs. 2C, 4B and 5C) where Lercari teaches an optional arbitration logic in each controller (see FIG. 4B, discussed above) provides a mechanism for avoiding competition between the peer-to-peer bus 582 and the connections to the host (575/576); in one embodiment, this mechanism simply determines whether an addressed drive or structure is already busy, and if so, it queues received commands/requests. In other embodiments, however, a busy signal can be sent to the pertinent requester and/or a "reservation" can be sent to the requester, to permit the requester to resubmit the command/request at a later time. Once again, it should be appreciated that using such an architecture, the host can dynamically schedule a write time such that the two drives exchange data in a manner that reduces interference with host access requirements, where the mechanism for avoiding competition between the peer-to-peer bus 582 and the connections to the host (575/576) and the concept of busy signal that can be sent to the pertinent requester and/or a "reservation" can be sent to the requester, to permit the requester to resubmit the command/request at a later time where the host can dynamically schedule a write time such that the two drives exchange data in a manner that reduces interference with host access requirements inherits the features of a duration for suspending access activity to the first memory, the duration being based on a first time value and a second time value to correspond to the claimed limitation].
As per dependent claim 6, Lercari discloses wherein the one or more controllers are further configured to cause the apparatus to: modify, via the second interface, the control signal to indicate a resumption of access activity to the first memory based on determining that the data has been transferred from the second memory to the first memory [(Column 36, lines 52-67; Figs. 2C, 4B and 5C) where Lercari teaches an optional arbitration logic in each controller (see FIG. 4B, discussed above) provides a mechanism for avoiding competition between the peer-to-peer bus 582 and the connections to the host (575/576); in one embodiment, this mechanism simply determines whether an addressed drive or structure is already busy, and if so, it queues received commands/requests. In other embodiments, however, a busy signal can be sent to the pertinent requester and/or a "reservation" can be sent to the requester, to permit the requester to resubmit the command/request at a later time. Once again, it should be appreciated that using such an architecture, the host can dynamically schedule a write time such that the two drives exchange data in a manner that reduces interference with host access requirements, where the mechanism for avoiding competition between the peer-to-peer bus 582 and the connections to the host (575/576) and the concept of busy signal that can be sent to the pertinent requester and/or a "reservation" can be sent to the requester, to permit the requester to resubmit the command/request at a later time where the host can dynamically schedule a write time such that the two drives exchange data in a manner that reduces interference with host access requirements inherits the features of indicate a resumption of access activity to the second memory based on determining that the data has been transferred from the second memory to the first memory to correspond to the claimed limitation].
Yasui further discloses [(Paragraph 0037)the OS 5 turns on the exclusive control lock (step S26). However, in this case, there is a possibility that other process executes a read operation for this wait operation. For this reason, the OS 5 determines whether or not the write operation is in a suspended state at present (step S27). If it is determined that the write operation is in a suspended state, the OS 5 turns off the TLB 2 of the read-only area 8 (step S31). Thereafter, the OS 5 issues a command to restart the write operation, and thereby, the write operation is continued (step S30)]
As for independent claims 9 and 15, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claim 13, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
As for dependent claims 14 and 20, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
Claims 2 and 10 are rejected under 35 U.S.C. 103(a) as being disclosed by Lercari in view of Yasui, in view of Li, as applied to claims 1 and 9, and further in view of Shaeffer et al. (US PGPUB 2016/0026583 hereinafter referred to as Shaeffer).
As per dependent claim 2, Lercari discloses the apparatus of claim 1.
Lercari does not appear to explicitly disclose first routing circuitry, wherein the first controller controls the first memory based on controlling the first routing circuitry; and second routing circuitry, wherein the second controller controls the second memory based on controlling the second routing circuitry, and wherein transferring the data is based on routing the data from the second memory to the second routing circuitry, from the second routing circuitry to the first routing circuitry, and from the first routing circuitry to the first memory.
However, Shaeffer discloses first routing circuitry, wherein the first controller controls the first memory based on controlling the first routing circuitry; and second routing circuitry, wherein the second controller controls the second memory based on controlling the second routing circuitry [(Paragraphs 0030-0034; FIGs. 23) where the controller routing circuit 215 is coupled to the read/write queues 205, 210 and the I/O interfaces 220. The routing circuit 215 can be configured by controller logic 225 to route signals between any of the read/write queues 205, 210 and any of the I/O interfaces 220 in the memory controller 101. Similarly, the routing circuit 255-1 in memory device 120-1 can be configured by memory logic 265-1 to route signals between any of sub-banks 260-1, 260-2 and I/O interfaces 250-1, 250-2. Routing circuit 255-2 can be configured by memory logic 265-2 to route signals between any of the sub-banks 260-3, 260-4 and I/O interfaces 250-3, 250-4. The routing circuits 215, 255 enable transfer of data between any read queue 205 or write queue 210 and any sub-bank 260 of memory devices 120-1, 120-2 via either data bus 140-1, 140-2 to correspond to the claimed limitation], and wherein transferring the data is based on routing the data from the second memory to the second routing circuitry, from the second routing circuitry to the first routing circuitry, and from the first routing circuitry to the first memory [(Paragraphs 0030-0036; FIGs. 4, 5A-B) where FIGS. 4, 5A, and 5B together illustrate how calibration operations are performed in a memory system for device interfaces that operate using one data bus while transferring data between the controller and a memory device via another data bus, according to one embodiment. FIG. 4 illustrates a method performed by the memory controller, according to one embodiment. At a high level, in steps 405-420, the memory controller calibrates a first data bus one device at a time. While calibrating the first data bus, the memory controller transfers data between the controller and a memory device via a second data bus. In steps 425-440, the memory controller calibrates a second data bus one device at a time. While calibrating the second data bus, the memory controller transfers data between the controller and a memory device via the first data bus. By calibrating one data bus while accessing data through another data bus, the method allows data access to continue during calibration operations. As a result, the performance degradation associated with periodically calibrating a data bus in a multi-rank configuration is reduced to correspond to the claimed limitation].
Lercari and Shaeffer are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lercari and Shaeffer before him or her, to modify the method of Lercari to include the routing methods of data movement commands of Shaeffer because it will enhance data access.
The motivation for doing so would be [“the performance degradation associated with periodically calibrating a data bus in a multi-rank configuration is reduced to correspond to the claimed limitation” (Paragraph 0036 by Shaeffer)].
Therefore, it would have been obvious to combine Lercari and Shaeffer to obtain the invention as specified in the instant claim.
As for dependent claim 10, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
Claims 3 and 11 are rejected under 35 U.S.C. 103(a) as being disclosed by Lercari in view of Yasui, in view of Li, as applied to claims 1 and 9, and further in view of Kim et al. (US PGPUB 2020/0356669 hereinafter referred to as Kim).
As per dependent claim 3, Lercari discloses the apparatus of claim 1.
Lercari does not appear to explicitly disclose wherein: the first interface is associated with a first communication protocol and the second interface is associated with a second communication protocol different than the first communication protocol; and the first interface and the second interface are operable to communicatively couple the apparatus with a host device.
However, Kim discloses wherein: the first interface is associated with a first communication protocol and the second interface is associated with a second communication protocol different than the first communication protocol; and the first interface and the second interface are operable to communicatively couple the apparatus with a host device [(Paragraphs 0086-0090; FIGs. 6) where The first pin 202 may be connected to the host processor 210, the second pin 302 may be connected to the first storage controller 310a, and the first interface may be disposed or formed between the first pin 202 and the second pin 302. The third pin 204 may be connected to the secure element 220, the fourth pin 304 may be connected to the second storage controller 310b, and the second interface may be disposed or formed between the third pin 204 and the fourth pin 304. In some example embodiments, the first interface and the second interface may conform to different protocols and may exchange signals based on the different protocols. For example, as described with reference to FIG. 2, the first interface may include a normal or general eMMC or UFS interface. The second interface may be different from the first interface and may include a dedicated security interface (or a dedicated security protocol) for secure communication to correspond to the claimed limitation].
Lercari and Kim are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lercari and Kim before him or her, to modify the method of Lercari to include the interfaces, bins and the different protocols of Kim because it will enhance data access.
The motivation for doing so would be [“the first RPMB function for the host processor and the second RPMB function for the secure element may be separately and efficiently implemented, a portion associated with the secure element may not be attacked even if the host processor is hacked, thereby having a higher security level compared to an implementation of the related art in which RPMB sub-systems are not separated” (Paragraph 0020 by Kim)].
Therefore, it would have been obvious to combine Lercari and Kim to obtain the invention as specified in the instant claim.
As for dependent claim 11, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
Claims 7 and 16 are rejected under 35 U.S.C. 103(a) as being disclosed by Lercari in view of Yasui, in view of Li, as applied to claims 1 and 15, and further in view of McCall et al. (US PGPUB 2019/0042162 hereinafter referred to as McCall).
As per dependent claim 7, Lercari discloses the apparatus of claim 1.
Lercari does not appear to explicitly disclose wherein: the first memory has a deterministic access timing and the second memory has a non-deterministic access timing.
However, McCall discloses wherein: the first memory has a deterministic access timing and the second memory has a non-deterministic access timing; [(Paragraph 0050; FIGs. 5) where the flash or emerging NVRAM technologies are understood to be slower than dynamic random access memory (DRAM) and/or have non deterministic response timing(s). With the ranks of the DIMM of FIG. 5 understood to be composed of DRAM, the DIMM 800 of FIG. 8a would generally not be able to support the data rates in/out of memory as the DIMM 500 of FIG. 5 is able to support. That is, with NVRAM being slower than DRAM and/or having non-deterministic access times (DRAM has deterministic access times), the CA and DQ bus that is coupled to an NVRAM DIMM is apt to have some quiet, unused windows of time as compared to a DRAM DIMM to correspond to the claimed limitation].
Lercari and McCall are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lercari and McCall before him or her, to modify the method of Lercari to include the DRAM and the flash storage of McCall because it will enhance data access.
The motivation for doing so would be [“ increase memory channel capacity and bandwidth while keeping power consumption in check” (Paragraph 0002 by McCall)].
Lercari discloses the control signal being transmitted after transmission of the one or more read commands and the one or more write commands [(Column 36, lines 52-67; Figs. 2C, 4B and 5C) where Lercari teaches an optional arbitration logic in each controller (see FIG. 4B, discussed above) provides a mechanism for avoiding competition between the peer-to-peer bus 582 and the connections to the host (575/576); in one embodiment, this mechanism simply determines whether an addressed drive or structure is already busy, and if so, it queues received commands/requests. In other embodiments, however, a busy signal can be sent to the pertinent requester and/or a "reservation" can be sent to the requester, to permit the requester to resubmit the command/request at a later time. Once again, it should be appreciated that using such an architecture, the host can dynamically schedule a write time such that the two drives exchange data in a manner that reduces interference with host access requirements to correspond to the claimed limitation].
Therefore, it would have been obvious to combine Lercari and McCall to obtain the invention as specified in the instant claim.
As for dependent claim 16, the applicant is directed to the rejections to claim 7 set forth above, as they are rejected based on the same rationale.
Claim 8 is rejected under 35 U.S.C. 103(a) as being disclosed by Lercari in view of Yasui, in view of Li, as applied to claims 1 and 9, and further in view of Lee et al. (US PGPUB 2016/0196216 hereinafter referred to as Lee).
As per dependent claim 8, Lercari discloses the apparatus of claim 1.
Lercari does not appear to explicitly disclose wherein, to transfer the data, the one or more controllers are further configured to cause the apparatus to: read a first subset of data bits of the data from the second memory, the first subset of data bits having a first size; write the first subset of data bits of the data to the first memory; read, after writing the first subset of data bits, a second subset of data bits of the data from the second memory, the second subset of data bits having the first size; and write the second subset of data bits of the data to the first memory.
However, Lee discloses wherein, to transfer the data, the one or more controllers are further configured to cause the apparatus to: read a first subset of data bits of the data from the second memory, the first subset of data bits having a first size [(Paragraphs 0190-0193; FIGs. 12A) where the RAID controller 1100B sequentially stores data that is to be written, in the NVRAM 1500. When pieces of data that are together equivalent to the size of one memory block are initially collected in the NVRAM 1500, the RAID controller 1100B reads the data from the NVRAM 1500 and writes the read data in a memory block #1 of the first SSD 1300-1, which is empty. Accordingly, as shown in FIG. 12A, data is stored in the NVRAM 1500 and the first through N-th SSDs 1300-1 through 1300-N; Next, when pieces of data that are together equivalent to the size of one memory block are secondly collected in the NVRAM 1500, the RAID controller 1100B reads the secondly-collected data from the NVRAM 1500 and writes the read data to a memory block #1 of the second SSD 1300-2, which is empty. Accordingly, as shown in FIG. 12B, data is stored in the NVRAM 1500 and the first through N-th SSDs 1300-1 through 1300-N. Next, when pieces of data that are together equivalent to the size of one memory block are thirdly collected in the NVRAM 1500, to correspond to the claimed limitation]; write the first subset of data bits of the data to the first memory; read, after writing the first subset of data bits, a second subset of data bits of the data from the second memory, the second subset of data bits having the first size; and write the second subset of data bits of the data to the first memory [(Paragraphs 0190-0193; FIGs. 12A) where the RAID controller 1100B sequentially stores data that is to be written, in the NVRAM 1500. When pieces of data that are together equivalent to the size of one memory block are initially collected in the NVRAM 1500, the RAID controller 1100B reads the data from the NVRAM 1500 and writes the read data in a memory block #1 of the first SSD 1300-1, which is empty. Accordingly, as shown in FIG. 12A, data is stored in the NVRAM 1500 and the first through N-th SSDs 1300-1 through 1300-N; Next, when pieces of data that are together equivalent to the size of one memory block are secondly collected in the NVRAM 1500, the RAID controller 1100B reads the secondly-collected data from the NVRAM 1500 and writes the read data to a memory block #1 of the second SSD 1300-2, which is empty. Accordingly, as shown in FIG. 12B, data is stored in the NVRAM 1500 and the first through N-th SSDs 1300-1 through 1300-N. Next, when pieces of data that are together equivalent to the size of one memory block are thirdly collected in the NVRAM 1500, the RAID controller 1100B reads the thirdly-collected data from the NVRAM 1500 and writes the read data to a memory block #1 of the third SSD 1300-3, which is empty. Accordingly, as shown in FIG. 12C, data is stored in the NVRAM 1500 and the first through N-th SSDs 1300-1 through 1300-N. After sequentially writing data to the first through (N-1)th SSDs 1300-1 through 1300-(N-1), defining one stripe, in the above-described manner, the RAID controller 1100B calculates parity information about the data that is stored in the NVRAM 1500 and defines one stripe, and writes the calculated parity information to a memory block #1 of the N-th SSDN 1300-N. Thereafter, the RAID controller 1100B performs a flush operation for emptying the NVRAM 1500. Accordingly, as shown in FIG. 12D, data is stored in the NVRAM 1500 and the first through N-th SSDs 1300-1 through 1300-N to correspond to the claimed limitation].
Lercari and Lee are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Lercari and Lee before him or her, to modify the method of Lercari to include the RAID controller method of data movement commands of Lee because it will enhance data storage operations.
The motivation for doing so would be [“to reduce or minimize an inter-valid-page copy operation during garbage collection” (Paragraph 0215 by Lee)].
Therefore, it would have been obvious to combine Lercari and Lee to obtain the invention as specified in the instant claim.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 4, 12 and 17-19, but would be allowable if rewritten in an independent form.
The reasons for allowance of claim 4 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein: the inter-memory data movement command comprises a first address associated with the first memory and a second address associated with the second memory; and to transmit the one or more read commands and the one or more write commands, the one or more controllers are further configured to cause the apparatus to: transmit a first indication of the first address to the first memory; and transmit a second indication of the second address to the second memory, wherein transferring the data is based on the first indication and the second indication”.
The reasons for allowance of claim 17 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein, to determine the direction of data movement, the one or more controllers are further configured to cause the apparatus to: determine that the direction of the data movement is from the first memory to the second memory; and transmitting, based on determining that the direction of data movement is from the first memory to the second memory, one or more read commands to the first memory and one or more write commands the second memory before transmitting the indication to suspend access activity”.
The reasons for allowance of claim 18 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein, to determine the direction of data movement, the one or more controllers are further configured to cause the apparatus to: determine that the direction of the data movement is from the second memory to the first memory; and transmitting, based on determining that the direction of data movement is from the second memory to the first memory, one or more read commands to the first memory and one or more write commands the second memory after transmitting the indication to suspend access activity”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED M GEBRILohamed Gebril whose telephone number is (571)270-1857 and email address is mohamed.gebril @uspto.gov. The examiner can normally be reached on Monday-Friday 9-5 ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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