DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 March 2026 is entered.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
i. Applicant argues that the Examiner’s assertion – that limitations of claim 13 (now cancelled and recited claim 1) are taught by the reference Kim et al. (2020/0394953) is hindsight and unreasonable broad interpretation. Please consider the following grounds of respectful disagreement.
The allegation is substantiated in pointing to Kim’s teaching that the independent compensation of driving transistors in equivalent first and second pixel driving circuit blocks [0167] does not read fairly upon the recitation of the number of operations for Vth characteristic compensation of a driving transistor in the first and second pixel driving circuit blocks being controlled differently. However, the claim recites neither that the number of operations themselves are different, nor a more narrow capture of what constitutes being “…controlled differently…” as claimed. Kim’s explicit teaching of Vth compensation in each of the pixel driving circuit blocks being independent of one another similarly communicates parameters of said compensation (including the claimed number of operations) being controlled differently. This would be true even if said number of operations (of Vth characteristic compensation), upon being compensated, were the same.
ii. Arguments directed toward the allowability of claims depending from those reciting the argued language are moot, in view of the maintained rejection, in view of the reasoning above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
i. Claims 1, 5, 7, 8, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2020/0394953; hereinafter Kim; cited in Applicant’s 11 August 2025 IDS).
Regarding claim 1, Kim discloses an electronic device [0112] comprising:
a display (Figures 2A, 3: Comprising 100) comprising a plurality of pixels (Comprising 110; Figure 10A1) comprising light-emitting diodes (Comprising 120) and pixel driving circuits (Comprising 111, 112) for light emission of the light-emitting diodes (Comprising 120);
a display driver integrated circuit (DDI) configured to drive the display [0060];
memory storing one or more computer programs [0352]; and
one or more processors communicatively coupled to the memory [0353] and the DDI [0209], wherein each of the plurality of pixels (Comprising 110) comprises:
a first pixel driving circuit block (Comprising 111) configured to generate a pulse width modulation (PWM) signal for controlling driving timing [0089] of the light-emitting diodes [0090], and
a second pixel driving circuit block (Comprising 112) configured to control intensity of a current [0089] supplied to the light-emitting diodes [0097], wherein
the first pixel driving circuit block (Comprising 111) comprises a plurality of transistors (Comprising T1…T5) and a first capacitor (Comprising C1), and wherein
the second pixel driving circuit block (Comprising 112) comprises a plurality of transistors (Comprising T6…T11) and a second capacitor (Comprising C2), wherein the instructions, when executed by the one or more processors individually or collectively, cause the electronic device to
control a compensation voltage for compensating for a Vth characteristic [0164]2 to be supplied to a source terminal of a driving transistor (Figure 10A: Comprising T8; [0163]) arranged in the second pixel driving circuit block (Comprising 112), and
maintain the compensated Vth characteristic of the driving transistor (Comprising T8) arranged in the second pixel driving circuit block (Comprising 112; [0147], [0148]),
control an initialization voltage (Figure 10A: Comprising Vini) to be supplied to a gate node of a driving transistor (Comprising T3) arranged in the first pixel driving circuit block (Comprising 111) and a gate node of the driving transistor (Comprising T8) arranged in the second pixel driving circuit block (Comprising 112), and
differently control a number of operations of Vth characteristic compensation of the driving transistor arranged in the first pixel driving circuit block and Vth characteristic compensation of the driving transistor arranged in the second pixel driving circuit block (Figures 10A, 10B; Independent compensation of T3, T8 [0167] according to respective pulse waveforms of SPWM [0135] and SPAM [0134]).
Kim does not expressly state the device being provided wherein a capacity of the second capacitor is two times or more larger than a capacity of the first capacitor so as to maintain the compensated Vth characteristic of the driving transistor arranged in the second pixel driving circuit block. However, please consider the following.
The instant application describes the second capacitance value as at least twice the first capacitance value, as a measure implemented to maintain the driving transistor threshold voltage characteristic compensation value [0264]3. Kim actively compensates driving transistors’ threshold voltage ([0147], [0148], [0167]) and acknowledges the role of capacitance when driving transistors’ gate electrode [0174].
Applicant does not furnish detail of the manner by which the superiority of the claimed factor of two (between respective capacitance value) compared to other relative values of the first and second capacitors was ascertained, as requiring greater than ordinary skill in the art. Selection of the relative values of first (Figure 10: Comprising C1) and second (C2) capacitors fulfilling the aforementioned compensatory function is deemed a matter of optimization at which an Artisan may arrive through routine experimentation.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Kim to be modified wherein a capacity of the second capacitor is two times or more larger than a capacity of the first capacitor, to arrive at the claimed invention, in view of the reasoning above.
Regarding claim 5, Kim discloses the electronic device of claim 1. Kim discloses the device further comprising: a switching transistor (Figure 10A: Comprising T9) connected to, as a diode connection circuit, a drain terminal and a gate terminal of the driving transistor (Comprising T8) arranged in the second pixel driving circuit block (Comprising 112).
Regarding claim 7, Kim discloses the electronic device of claim 1. Kim discloses the device wherein instructions, when executed by the one or more processors individually or collectively, further cause the electronic device to control the gate node of the driving transistor (Figure 10A: Comprising T3) arranged in the first pixel driving circuit block (Comprising 111) and the gate node of the driving transistor (Comprising T8) arranged in the second pixel driving circuit block (Comprising 112) to be initialized together (By VST).
Regarding claim 8, Kim discloses the electronic device of claim 7. Kim discloses the device wherein the light-emitting diodes (Figure 10A: Comprising 120) are located at one place in a light emission path comprising a second node to which a VSS voltage (Comprising VSS) is supplied from a first node to which a VDD voltage (Comprising VDD_PAM) is supplied via the driving transistor (Comprising T8) arranged in the second pixel driving circuit block (Comprising 112).
Regarding claim 14, Kim discloses the electronic device of claim 1. Kim discloses the device wherein the instructions, when executed by the one or more processors individually or collectively, further cause the electronic device to control a Vth characteristic compensation value of the driving transistor arranged in the second pixel driving circuit block to be maintained for a predetermined period (Figures 10A, 10B; [0134]: Duration of SPAM low pulse applied to gate of T7, T9 for Vth compensation of T8).
ii. Claims 2, 3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claim 1 above, and further in view of Toyomura et al. (2021/0343244; hereinafter Toyomura; cited in Applicant’s 6 November 2024 IDS).
Regarding claim 2, Kim discloses the electronic device of claim 1. Kim discloses the device wherein the instructions, when executed by the one or more processors individually or collectively, further cause the electronic device to control a voltage (Figure 10A: Comprising Sig) supplied to a source terminal of a driving transistor (Comprising T8) arranged in the second pixel driving circuit block (Comprising 112) to be separately input into each of a red pixel, a green pixel, and a blue pixel (Figure 19C).
Kim does not explicitly disclose the device wherein the voltage is a compensation voltage (Vref).
In the same field of endeavor, Toyomura discloses display driving [0002] wherein signal lines (Figure 7: Comprising 33) transmit a video signal (Comprising V.sub.sig) and reference voltage (Comprising V.sub.ofs) used for threshold value correction [0048]. This is among measures implemented to reduce peripheral circuit size [0009].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Kim to be modified wherein the voltage is a compensation voltage (Vref), in view of the teaching of Toyomura, to reduce peripheral circuit size.
Regarding claim 3, Kim discloses the electronic device of claim 1. Kim discloses the device wherein the instructions, when executed by the one or more processors individually or collectively, further cause the electronic device to control a voltage (Figure 10A: Comprising Sig) supplied to a source terminal of a driving transistor (Comprising T8) arranged in the second pixel driving circuit block (Comprising 112) to be input into a red pixel, a green pixel, and a blue pixel in common (Figure 18A).
Kim does not explicitly disclose the device wherein the voltage is a compensation voltage (Vref).
In the same field of endeavor, Toyomura discloses display driving [0002] wherein signal lines (Figure 7: Comprising 33) transmit a video signal (Comprising V.sub.sig) and reference voltage (Comprising V.sub.ofs) used for threshold value correction [0048]. This is among measures implemented to reduce peripheral circuit size [0009].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Kim to be modified wherein the voltage is a compensation voltage (Vref), in view of the teaching of Toyomura, to reduce peripheral circuit size.
iii. Claims 9 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claim 7 above, and further in view of Shigeta et al. (2020/0265777; hereinafter Shigeta; cited in Applicant’s 6 November 2024 IDS).
Regarding claim 9, Kim discloses the electronic device of claim 7. Kim discloses the device wherein the instructions, when executed by the one or more processors individually or collectively, further cause the electronic device to: initialize the gate node of the driving transistor arranged in the second pixel driving circuit block [0145]; and control a Vth characteristic compensation operation [0164] to be repeatedly performed (Figures 10A, 10B: With every pulse of SPAM applied to gate of T9).
Kim does not explicitly disclose the frequency of initializing as every duty driving.
In the same field of endeavor, Shigeta discloses display driving [0002] wherein the driving transistor (Figure 16A: Comprising T8) of the PAM pixel circuit (Comprising 140”) receives an initial voltage (Comprising V_initial) according to the timing of a gate driving signal (Comprising INI{n}) coincident with every emission (Comprising EMT{n}) pulse (Figure 16B: Temporal overlap of INI{n} and EMT{n} signals). This is among measures implemented to overcome existing limits of a light emission duty ratio [0010].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Kim to be modified wherein the frequency of initializing as every duty driving, in view of the teaching of Shigeta, to overcome existing limits of light emission duty ratio.
Regarding claim 10, Kim in view of Shigeta discloses the electronic device of claim 9. Kim discloses the device wherein the instructions, when executed by the one or more processors individually or collectively, further cause the electronic device to control Vth characteristic compensation [0162] of the driving transistor (Figure 10A: Comprising T3) arranged in the first pixel driving circuit block (Comprising 111), and sweep coupling [0174] to be repeatedly performed ([0091]: Every frame).
Regarding claim 11, Kim in view of Shigeta discloses the electronic device of claim 10. Kim discloses the device wherein the instructions, when executed by the one or more processors individually or collectively, further cause the electronic device to control a voltage stored in the first capacitor (Figure 10A: Comprising C1) to be initialized (Application of Vini, to one terminal thereof) in units of frames (By timing of VST applied to gate of T12; waveform shown in Figure 10B).
Regarding claim 12, Kim in view of Shigeta discloses the electronic device of claim 10. Kim discloses the device wherein the instructions, when executed by the one or more processors individually or collectively, further cause the electronic device to control a voltage value stored in the second capacitor (Figure 10A: Comprising C2) to be initialized (Application of Vini to one terminal thereof, through T11).
Kim does not explicitly disclose the aforementioned initialization in units of duties.
In the same field of endeavor, Shigeta discloses display driving [0002] wherein the second capacitor (Figure 16A: Comprising C2) receives an initial voltage (Comprising V_initial) according to the timing of a gate driving signal (Comprising INI{n}) coincident with every emission (Comprising EMT{n}) pulse (Figure 16B: Temporal overlap of INI{n} and EMT{n} signals). This is among measures implemented to overcome existing limits of a light emission duty ratio [0010].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Kim to be modified wherein the frequency of initializing as every duty driving, in view of the teaching of Shigeta, to overcome existing limits of light emission duty ratio.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Aaron Midkiff whose telephone number is (571)270-5875. The examiner can normally be reached Monday - Friday, 8:00am - 4:00pm.
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/AARON MIDKIFF/
Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
1 Reference number 110 designates pixel circuits in Figures 3 [0079], 7A [0132], with the reference numeral 100 used for latter illustrations of the pixel circuit, including in Figure 10A. To avoid confusion with identifying the display panel, 110 exclusively will be relied upon to identify the pixel circuit.
2 Driving transistor threshold compensation with reference to Figures 10A, 10B among subject matter comparable to that of Figure 7A, 7B and omitted for brevity; [0193].
3 Paragraph citation in PG Publication 2025/0061847.
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