DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 11/6/2024.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 1 recites “…a controller configurable to receive an access request including a memory address from a peripheral; and a cache configuration register coupled to the controller and configured to store a first mask bit associated with the peripheral, wherein the controller is configurable to: perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocate a cache way to a cache tag associated with the memory address using the first output bit” (independent claim 1, lines 2-10).
The Examiner is uncertain if the recitation of “a controller configurable to receive an access request including a memory address from a peripheral” means any one of the following:
“a controller” receives “an access request” from “a peripheral” in which the access request includes “a memory address”;
“a controller” receives “an access request” that includes “a memory address” that is from (i.e., associated with or part of) “a peripheral”; or
some other possible, unforeseen interpretation.
In addition, the Examiner is uncertain if “allocate a cache way to a cache tag associated with the memory address using the first output bit” means any one of the following:
“a cache way” is allocated “to a cache tag associated with the memory address” by “using the first output bit”;
“using the first output bit,” “a cache way” is allocated “to a cache tag associated with the memory address”’
or some other possible, unforeseen interpretation.
For the sake of examination, the Examiner has interpreted “…a controller configurable to receive an access request including a memory address from a peripheral; and a cache configuration register coupled to the controller and configured to store a first mask bit associated with the peripheral, wherein the controller is configurable to: perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocate a cache way to a cache tag associated with the memory address using the first output bit” to read “…a controller configurable to receive an access request from a peripheral, wherein the access request includes a memory address; and a cache configuration register coupled to the controller and configured to store a first mask bit associated with the peripheral, wherein the controller is configurable to: perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and, using the first output bit, allocating a cache way to a cache tag associated with the memory address from the access request.” Dependent claims 2-12, which ultimately depend from independent claim 1, are rejected for carrying the same deficiency.
Claims 13-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 13 recites “…receiving an access request including a memory address from a peripheral; retrieving a first mask bit associated with the peripheral from a cache configuration register; performing a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocating a cache way to a cache tag associated with the memory address using the first output bit” (independent claim 13, lines 2-8).
The Examiner is uncertain if the recitation of “receiving an access request including a memory address from a peripheral” means any one of the following:
“an access request” is received from “a peripheral” in which the access request includes “a memory address”;
“an access request” that includes “a memory address” is received from (i.e., associated with or part of) “a peripheral”; or
some other possible, unforeseen interpretation.
In addition, the Examiner is uncertain if “allocating a cache way to a cache tag associated with the memory address using the first output bit” means any one of the following:
“a cache way” is allocated “to a cache tag associated with the memory address” by “using the first output bit”;
“using the first output bit,” “a cache way” is allocated “to a cache tag associated with the memory address”’
or some other possible, unforeseen interpretation.
For the sake of examination, the Examiner has interpreted “…receiving an access request including a memory address from a peripheral; retrieving a first mask bit associated with the peripheral from a cache configuration register; performing a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocating a cache way to a cache tag associated with the memory address using the first output bit” to read “…receiving, from a peripheral, an access request that includes a memory address; retrieving a first mask bit associated with the peripheral from a cache configuration register; performing a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and using the first output bit to allocate a cache way to a cache tag associated with the memory address from the access request.” Dependent claims 14-18, which ultimately depend from independent claim 13, are rejected for carrying the same deficiency.
Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 19 recites “…a memory cache including a cache way; a peripheral; a cache controller configurable to receive an access request including a memory address from the peripheral; and a cache configuration register coupled to the cache controller and configured to store a first mask bit associated with the peripheral, wherein the cache controller is configurable to: perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocate the cache way to a cache tag associated with the memory address using the first output bit” (independent claim 19, lines 2-12). The Examiner is uncertain if the recitation of “a controller configurable to receive an access request including a memory address from a peripheral” means any one of the following:
“a cache controller” receives “an access request” from “the peripheral” in which the access request includes “a memory address”;
“a cache controller” receives “an access request” that includes “a memory address” that is from (i.e., associated with or part of) “the peripheral”; or
some other possible, unforeseen interpretation.
In addition, the Examiner is uncertain if “allocate the cache way to a cache tag associated with the memory address using the first output bit” means any one of the following:
“a cache way” is allocated “to the cache tag associated with the memory address” by “using the first output bit”;
“using the first output bit,” “a cache way” is allocated “to the cache tag associated with the memory address”’
or some other possible, unforeseen interpretation.
For the sake of examination, the Examiner has interpreted “…a memory cache including a cache way; a peripheral; a cache controller configurable to receive an access request including a memory address from the peripheral; and a cache configuration register coupled to the cache controller and configured to store a first mask bit associated with the peripheral, wherein the cache controller is configurable to: perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocate the cache way to a cache tag associated with the memory address using the first output bit” to read “…a memory cache including a cache way; a peripheral; a cache controller configurable to receive an access request from the peripheral, wherein the access request includes a memory address; and a cache configuration register coupled to the cache controller and configured to store a first mask bit associated with the peripheral, wherein the cache controller is configurable to: perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and using the first output bit to allocate the cache way to a cache tag associated with the memory address from the access request.” Dependent claim 20, which ultimately depends from independent claim 19, is rejected for carrying the same deficiency.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 13, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7-8, 13, and 18-19 of U.S. Patent No. 12,141,435 (“Chirca”). The following tables, in which similarities between independent claims 1, 13, and 19 of the instant application and Chirca are highlighted in bold, and accompanying reasoning clearly show that claims 1, 13, and 19 of the instant application are not patentably distinct over Chirca:
Instant Application, Independent Claim 1
Chirca, Claims 1 and 7-8
A device comprising: a controller configurable to receive an access request including a memory address from a peripheral; and a cache configuration register coupled to the controller and configured to store a first mask bit associated with the peripheral, wherein the controller is configurable to: perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocate a cache way to a cache tag associated with the memory address using the first output bit.
A device comprising: a cache configuration register; and a controller coupled to the cache configuration register, wherein the controller is configured to: receive a pointer including a first pointer bit; retrieve a first mask including a first mask bit from the cache configuration register; retrieve a second mask including a second mask bit from the cache configuration register; perform a first logical operation with the first pointer bit and the first mask bit to generate a first output bit; perform a second logical operation with the first output bit and the second mask bit to generate a first way identifier bit; and allocate a cache way to addressable memory space or data cache based on the first way identifier bit.
The device of claim 1, wherein the controller is configured to receive a memory access request associated with a cache tag, and wherein the controller is further configured to allocate the cache way to the cache tag based on the first way identifier bit.
The device of claim 7, wherein the controller is configured to: receive the memory access request from a requesting device, and retrieve the first mask and the second mask based on whether the requesting device is associated with real-time or non-real-time.
The Examiner notes that “a requesting device” of claim 8 of Chirca is a device that sends memory access requests to the controller and is thus “a peripheral.” In addition, the Examiner notes that “the first output bit” of Chirca is used in conjunction with the second mask of Chirca to allocate a cache way to a memory address associated with the access request received from “the requesting device” (i.e., the peripheral), The first output bit of Chirca is thus used to allocate a cache way to a memory address associated with the access request received from the requesting device (i.e., the peripheral).
Instant Application, Independent Claim 13
Chirca, Claims 13 and 18-19
13. A method comprising: receiving an access request including a memory address from a peripheral; retrieving a first mask bit associated with the peripheral from a cache configuration register; performing a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocating a cache way to a cache tag associated with the memory address using the first output bit.
13. A method comprising: receiving, at a controller, a pointer including a first pointer bit; retrieving, by the controller, a first mask including a first mask bit from a cache configuration register; retrieving, by the controller, a second mask including a second mask bit from the cache configuration register; performing, by the controller, a first logical operation with the first pointer bit and the first mask bit to generate a first output bit; performing, by the controller, a second logical operation with the first output bit and the second mask bit to generate a first way identifier bit; and allocating, by the controller, a cache way to addressable memory space or data cache based on the first way identifier bit.
18. The method of claim 13, further comprising receiving a memory access request associated with a cache tag, and wherein allocating the cache way comprises allocating the cache way to the cache tag is based on the first way identifier bit.
19. The method of claim 18, wherein receiving the memory access request comprises receiving the memory access request from a requesting device, and wherein retrieving the first mask and the second mask is based on whether the requesting device is associated with real-time or non-real-time.
The Examiner notes that “a requesting device” of claim 8 of Chirca is a device that sends memory access requests to the controller and is thus “a peripheral.” In addition, the Examiner notes that “the first output bit” of Chirca is used in conjunction with the second mask of Chirca to allocate a cache way to a memory address associated with the access request received from “the requesting device” (i.e., the peripheral), The first output bit of Chirca is thus used to allocate a cache way to a memory address associated with the access request received from the requesting device (i.e., the peripheral).
Instant Application, Independent Claim 19
Chirca, Claims 1 and 7-8
Chirca,
19. A system comprising: a memory cache including a cache way; a peripheral; a cache controller configurable to receive an access request including a memory address from the peripheral; and a cache configuration register coupled to the cache controller and configured to store a first mask bit associated with the peripheral, wherein the cache controller is configurable to: perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and allocate the cache way to a cache tag associated with the memory address using the first output bit.
A device comprising: a cache configuration register; and a controller coupled to the cache configuration register, wherein the controller is configured to: receive a pointer including a first pointer bit; retrieve a first mask including a first mask bit from the cache configuration register; retrieve a second mask including a second mask bit from the cache configuration register; perform a first logical operation with the first pointer bit and the first mask bit to generate a first output bit; perform a second logical operation with the first output bit and the second mask bit to generate a first way identifier bit; and allocate a cache way to addressable memory space or data cache based on the first way identifier bit.
The device of claim 1, wherein the controller is configured to receive a memory access request associated with a cache tag, and wherein the controller is further configured to allocate the cache way to the cache tag based on the first way identifier bit.
The device of claim 7, wherein the controller is configured to: receive the memory access request from a requesting device, and retrieve the first mask and the second mask based on whether the requesting device is associated with real-time or non-real-time.
The Examiner first notes that “a device” as claimed in Chirca is a system used for caching at ways of a cache, which means that “a device” of Chirca is “a system” that necessarily includes a memory cache that has cache ways for performing caching. In addition, the Examiner notes that “a requesting device” of claim 8 of Chirca is a device that sends memory access requests to the controller and is thus “a peripheral.” Finally, the Examiner notes that “the first output bit” of Chirca is used in conjunction with the second mask of Chirca to allocate a cache way to a memory address associated with the access request received from “the requesting device” (i.e., the peripheral), The first output bit of Chirca is thus used to allocate a cache way to a memory address associated with the access request received from the requesting device (i.e., the peripheral).
Conclusion
The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure:
Non-patent literature “A Multistep Tag Comparison Method for a Low-Power L2 Cache”: teaches managing cache operations and power consumption in a multi-level cache hierarchy that selectively powers tag arrays.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135