DETAILED ACTION
Claims 1-20 are presented for examination, of which, claims 16-20 are non-elected from further consideration pursuant to 35 CFR 1.142(b) as being drawn to a nonelected election. Election was made without traverse during the response filed on 06-18-2026.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claim 1 is an independent claim. Claims 2-15 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 11-06-2024.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. It is also noted, that applicant has filed a certified copy on 11-27-2025 as required by 35 U.S.C. 119(b).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11-06-2024 is in compliance with the provisions of 37 CFR 1.97
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 11-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Publication No. 2025/0077461 (hereinafter, “Ahmed”).
As per claim(s) 1, Ahmed discloses a receiving device comprising:
a reception circuit provided in a physical area of the receiving device, the reception circuit configured to: ( at least Fig. 4 illustrates a decoder/deserializers/high-speed clock & datarecovery 902 provided by the receiver)
generate data based on a differential signals received from a transmitter, and transfer the data to a logical area of the receiving device; and (at least Fig. 4 illustrates a decoder that generates RXab, RXbc and RXca data for deserializers from transmitter /deserializers generate data symbols from transmitter/clock and data recovery 902)
a controller provided in the logical area, the controller configured to: (control register/finite state machine/PPI interface; Fig 9
determine an operation mode based on the data, generate an operation control signal based on the operation mode, and transfer the operation control signal to the reception circuit. (at least Fig’s 9-11 illustrate where the PPI interface may detect “an end of transmission” data state ¶ [0072]. In response, PPI EOT signal is generated to control the power mode (e.g, disable or low power) of the speed clock & and recovery device 902. (Also, ¶s [0070]- [0071])
As per claim 2, Ahmed discloses a receiving device wherein the reception circuit comprises: a high-speed receiver configured to: receive a first signal and a second signal, which are the differential signals, and generate first data based on the first signal and the second signal; (Fig. 9 illustrates high-speed clock & and recovery device 902 to receive trio signals that have different states (e.g., 1,0,-1 ¶ [0046] )and generate decoded data )
a first low-power receiver configured to: receive the first signal, and generate second data based on the first signal; and a second low-power receiver configured to: receive the second signal, and generate third data based on the second signal. (Fig. 3 illustrates a system having multiple receivers within each of the subordinated devices. Fig 9 further illustrates where each receiver includes a high-speed clock & and recovery device 902 that is controlled to operate to lower power mode based on PPI EOT signal. Therefore, the Office submits that the low power operation of high speed clock & recovery device found in each of exemplary receivers shown in Fig 3 is equivalent with the claimed language recited )
As per claim 3, Ahmed discloses a receiving device wherein the controller is further configured to: generate the operation control signal having a first level based on the operation mode being a low-power mode, and generate the operation control signal having a second level based on the operation mode being a high-speed mode. (¶ [004] discloses the invention where C-PHY high-speed mode uses a low-voltage for low-power modes and higher voltages for high-speed modes. Also, ¶s [0046]-[0047] )
As per claim 4, Ahmed discloses a receiving device wherein the controller is further configured to turn off the high-speed receiver based on the operation control signal being the first level, and turn on the high-speed receiver based on the operation control signal being the second level. (¶ [0071] discloses where the interface may transition to a disabled power mode operation or low-power mode of operation. )
As per claim 6, Ahmed discloses a receiving device wherein the controller is further configured to turn off at least one of the first and the second low-power receivers based on the operation control signal being the first level. (Fig. 3 illustrates a system having multiple receivers within each of the subordinated devices. Fig 9 further illustrates where each receiver includes a high-speed clock & and recovery device 902 that is controlled to operate to lower power mode based on PPI EOT signal. Furthermore “ a receiver may determine that the C-PHY interface is configured for the low-power mode of operation 716 based on detection of signaling at the higher voltage levels associated with the low-power mode.” ¶ [0057])
As per claim 11, Ahmed discloses a receiving device wherein the reception circuit is further configured to: generate a clock from signals received from the transmitter; and replace the clock with an internal clock signal based on an output of a low-power receiver of the reception circuit transitioning from a second level to a first level. (Ahmed discloses the invention of increasing the clock rates used to control signaling over serial interfaces. For example, the version 2.0 specification for MIPI C-PHY interfaces provides for transmission clock rates of between 4.5 GHZ and 6.0 GHz. ¶ [005], Also, a synchronization circuit is configured to propagate the first EOT signal as a second EOT signal in accordance with timing provided by an internally generated clock signal used by the finite state machine ¶ [0014])
As per claim 12, Ahmed discloses a receiving device wherein: the receiving device complies with D-PHY protocol of Mobile Industry Processor Interface (MIPI) alliance, (¶ [003])
the reception circuit comprises a data lane and a clock lane, the data lane is configured to generate the data from data signals received from the transmitter, the clock lane is configured to generate a clock from clock signals received from the transmitter, and the controller is further configured to turn off the reception circuit of the clock lane based on the operation mode being a low-power mode. (Fig. 9 illustrates decoded data lane and Rx clock lane. Further, Fig’s 9-11 illustrate where the PPI interface may detect “an end of transmission” data state ¶ [0072]. In response, PPI EOT signal is generated to control the power mode (e.g, disable or low power) of the speed clock & and recovery device 902. (Also, ¶s [0070]- [0071])
As per claim 13, Ahmed discloses a receiving device wherein the controller is further configured to turn on a high-speed receiver of the clock lane based on the operation mode being a high-speed mode. (Fig. 9 illustrates decoded data lane and Rx clock lane. Further, Fig’s 9-11 illustrate where the PPI interface may detect “an end of transmission” data state ¶ [0072]. In response, PPI EOT signal is generated to control the power mode (e.g, disable or low power) of the speed clock & and recovery device 902. (Also, ¶s [0070]- [0071])
As per claim 14, Ahmed discloses a receiving device wherein the controller is further configured to maintain a low-power receiver of the clock lane to be turned off based on the operation mode being a high-speed mode. (Fig. 9 illustrates decoded data lane and Rx clock lane. Further, Fig’s 9-11 illustrate where the PPI interface may detect “an end of transmission” data state ¶ [0072]. In response, PPI EOT signal is generated to control the power mode (e.g, disable or low power) of the speed clock & and recovery device 902. (Also, ¶s [0070]- [0071])
As per claim 15, Ahmed discloses a receiving device wherein: the receiving device complies with the C-PHY protocol of Mobile Industry Processor Interface (MIPI) (¶[003]) alliance; the reception circuit comprises a clock lane operating as a continuous clock mode and two data lanes receiving the data from the transmitter; and the controller is further configured to turn off the clock lane based on the operation mode of the data lane being a low-power mode. (Fig. 9 illustrates decoded data lane and Rx clock lane. Further, Fig’s 9-11 illustrate where the PPI interface may detect “an end of transmission” data state ¶ [0072]. In response, PPI EOT signal is generated to control the power mode (e.g, disable or low power) of the speed clock & and recovery device 902. (Also, ¶s [0070]- [0071])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2025/0077461 (hereinafter, “Ahmed”) in view of U.S. Publication No. 20090144571 (hereinafter, “Tatsumi”).
As per claim 5, Ahmed does not distinctly disclose a receiving device wherein the controller is further configured to turn the high-speed receiver on or off by opening or closing a first switch connected to an input end of the high-speed receiver.
However, Tatsumi explicitly discloses receiving device wherein the controller is further configured to turn the high-speed receiver on or off by opening or closing a first switch connected to an input end of the high-speed receiver. (Fig. 1 illustrates the invention where a system contains a plurality of power switches that are operable to turn on/off for controlling power to one or more power domains.)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ahmed and Tatsumi because both references are in the same field of endeavor. Tatsumi’s teaching of power switching for controlling power to different domains would enhance Ahmed's system by eliminating any power leaks further enhancing power management for the computer system.
As per claim 7, Ahmed as modified discloses a receiving device wherein the controller is further configured to turn at least one of the first and the second low-power receivers on or off by opening or closing a second switch for transferring a driving current to the at least one of the first and the second low-power receivers. (Fig. 1 illustrates the invention where a system contains a plurality of power switches that are operable to turn on/off for controlling power to one or more power domains.) & (Fig. 3 illustrates a system having multiple receivers within each of the subordinated devices. Fig 9 further illustrates where each receiver includes a high-speed clock & and recovery device 902 that is controlled to operate to lower power mode based on PPI EOT signal. Furthermore “ a receiver may determine that the C-PHY interface is configured for the low-power mode of operation 716 based on detection of signaling at the higher voltage levels associated with the low-power mode.” ¶ [0057])
Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2025/0077461 (hereinafter, “Ahmed”) in view of U.S. Patent No. 6,133,717 (hereinafter, “Ng”).
As per claim 8, Ahmed explicitly discloses a receiving device wherein the controller is further configured to: turn off the reception circuit (Fig 9 further illustrates where each receiver includes a high-speed clock & and recovery device 902 that is controlled to operate to lower power mode based on PPI EOT signal.)
Ahmed does not distinctly disclose the following:
receive a pulse signal from the transmitter through a synchronization pin; and based on a width of the pulse signal exceeding a reference pulse width while the reception circuit is operating.
However, Ng explicitly discloses disclose a receiving device wherein the controller is further configured to: receive a pulse signal from the transmitter through a synchronization pin; a width of the pulse signal exceeding a reference pulse width while the reception circuit is operating. (Col 7 lines 20-31 and Col lines 59-64)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Ahmed and Ng because both references are in the same field of endeavor. Ng’s teaching of synchronization pin would enhance Ahmed's system by eliminating any interference noise, thus enhancing communication technology for the computer device.
As per claim 9, Ahmed discloses a receiving device wherein the controller is further configured to turn on the reception circuit based on the width of the pulse signal exceeding the reference pulse width while the reception circuit is turned off. (Fig 9 further illustrates where each receiver includes a high-speed clock & and recovery device 902 that is controlled to operate to lower power mode based on PPI EOT signal.) & (Ng: (Col 7 lines 20-31 and Col lines 59-64))
As per claim 10, Ahmed discloses a receiving device wherein the controller is further configured to: generate a horizontal synchronization signal or a vertical synchronization signal based on the width of the pulse signal being smaller than the reference pulse width. (Fig 9 further illustrates where each receiver includes a high-speed clock & and recovery device 902 that is controlled to operate to lower power mode based on PPI EOT signal.) & (Ng: (Col 7 lines 20-31 and Col lines 59-64))
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
Prosecution Insights