DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over Cai et al (US Pat. 10,997,017; hereinafter referred to as Cai) in view of Nguyen et al (US Pat. 9,437,320; hereinafter referred to as Nguyen).
As per claims 1, 22:
Cai teaches a memory method and device, comprising:
a memory comprising a memory cell array arranged according to a plurality of word lines and a plurality of bit lines (Fig. 3); and
a memory controller configured to manage operations of the memory to determine corrective read information (Fig. 1, 100), wherein the memory controller is configured to:
perform a hard read on a victim memory cell based on a hard read threshold (Fig. 4B, R1-R7) to estimate a memory state of the victim memory cell (col.12, lines 45-47),
perform one or more soft reads on the victim memory cell to generate soft information for the victim memory cell (col. 12, lines 47-48),
calculate an initial error correction confidence value of the victim memory cell based on the hard read performed on the victim memory cell and the soft information (Figs. 9-10, 90; col. 12, lines 47-48),
perform a hard read on a neighboring aggressor memory cell to determine a memory state of the neighboring aggressor memory cell (Fig. 12, 1250; col. 12, lines 58-60), the memory state of the neighboring aggressor memory cell being in a high substate or a low substate (Fig. 6), and
refine the initial error correction confidence value of the victim memory cell, based on the hard read on the neighboring aggressor memory cell, to generate a refined error correction confidence value of the victim memory cell (Fig. 12, 1260).
Not explicitly disclosed is performing one or more soft reads on the victim memory cell based on one or more soft read thresholds to generate soft information for the victim memory cell, and refining the initial error correction confidence value based on a vector of the initial error correction confidence value. However, Nguyen in an analogous art teaches performing a soft read (col. 9, line 65-col. 10, line 2) for generating soft information based on one or more soft read thresholds (col. 11, lines 8-32), and refining the LLR confidence value (Fig. 14, 212) based on a vector of an initial LLR confidence value (col. 10, lines 53-64; col. 13, lines 43-53).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the LLR of Nguyen in the system of Cai. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Cai teaches using LLRs (col. 10, lines 64-66).
As per claim 2:
Nguyen further teaches the memory device of claim 1, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 1), refine the initial error correction confidence value, the vector of which indicates a low confidence of an erased state (Fig. 15B, row 1, soft bit 0 for erased state),
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, last row), refine the initial error correction confidence value, the vector of which indicates a low confidence of a programmed state (Fig. 15B, last row, soft bit 0 for programmed state).
Not explicitly disclosed is adjusting the initial error correction confidence value to a lower confidence level. However, Cai teaches a confidence value adjusting component (Fig. 9, 920) for adjusting the LLR when aggressor cells have strong influence on victim cells (col. 11, lines 47-52). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to make the adjustments recommended by Nguyen in Fig. 15B since Nguyen shows likely outcomes of different victim and aggressor cell combinations.
As per claim 3: Nguyen further teaches the memory device of claim 2, wherein the vector that indicates the low confidence of the erased state corresponds to the victim memory cell having a first read voltage value that is between the hard read threshold and a first soft read threshold, the first soft read threshold being less than the hard read threshold (Fig. 5, bin 1 with respect to Vr2), and
wherein the vector that indicates the low confidence of the programmed state corresponds to the victim memory cell having a second read voltage value that is between the hard read threshold and a second soft read threshold, the second soft read threshold being greater than the hard read threshold (Fig. 5, bin 2 with respect to Vr2).
As per claim 4: Nguyen further teaches the memory device of claim 1, wherein the initial error correction confidence value is an initial log likelihood ratio (LLR) value, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 1), refine the initial LLR value (Fig. 15B, row 1, soft bit 0), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, last row), refine the initial LLR value to zero (Fig. 15B, last row, soft bit 0).
Not explicitly disclosed is refining an initial LLR value to zero, the initial LLR having a vector of +1 or -1. However, Cai teaches a confidence value adjusting component for adjusting the LLR (Fig. 9, 920; col. 11, lines 47-62). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to adjust an initial LLR to 0 for the situations as above since it is suggested by Nguyen in Fig. 15B.
As per claim 5: Nguyen further teaches the memory device of claim 1, wherein the initial error correction confidence value is an initial log likelihood ratio (LLR) value (col. 10, lines 40-42),
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 1), refine the initial LLR value, having a vector of +2, by lowering the initial LLR value to +1 or to zero (Fig. 15B, row 1, low confidence that current bit=0), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, last row), refine the initial LLR value, having a vector of −2, by increasing the initial LLR value to −1 or to zero (Fig. 15B, last row, low confidence that current bit=1).
Although Nguyen does not explicitly disclose the initial LLR having a value of +2 or -2 (which indicate increased likelihood of a 0 or 1, respectively), Nguyen teaches the initial bit being respectively read as a 0 or 1. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use such a notation for indicating 0 or 1, as explained by Cai in col. 11, lines 47-62. Also not explicitly disclosed is adjusting the confidence value toward 0. However, Cai teaches a confidence value adjusting component for adjusting the LLR (Fig. 9, 920; col. 11, lines 47-62). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to adjust an initial LLR to 0 for the situations as above since it is suggested by Nguyen in Fig. 15B.
As per claim 6:
Nguyen further teaches the memory device of claim 1, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 5), the vector of which indicates a programmed state, by setting the initial error correction confidence value to a higher confidence level (Fig. 15B, row 5, soft bit=1 for programmed state), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 4), the vector of which indicates an erased state, by adjusting the initial error correction confidence value to a higher confidence level (Fig. 15B, row 4, soft bit=1 for erased state).
Not explicitly disclosed is refine the initial error correction confidence value, the vector of which indicates a low confidence of a programmed state and a low confidence of an erased state. However, Cai teaches a confidence value adjusting component (Fig. 9, 920) for adjusting the LLR when aggressor cells have strong influence on victim cells (col. 11, lines 47-52). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to make the adjustments recommended by Nguyen in Fig. 15B from any initial LLR since Nguyen shows likely outcomes of different victim and aggressor cell combinations.
As per claim 7: Nguyen further teaches the memory device of claim 1, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 4), the vector of which indicates a high confidence of an erased state (Fig. 15B, row 4, soft bit 1 for erased state), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 5), the vector of which indicates a high confidence of a programmed state (Fig. 15B, row 5, soft bit=1 for programmed state).
Not explicitly disclosed is refine the initial error correction confidence value and adjusting the initial error correction confidence value to a higher confidence level. However, Cai teaches a confidence value adjusting component (Fig. 9, 920) for adjusting the LLR when aggressor cells have strong influence on victim cells (col. 11, lines 47-52). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to make the adjustments recommended by Nguyen in Fig. 15B from any initial LLR since Nguyen shows likely outcomes of different victim and aggressor cell combinations.
As per claim 8: Nguyen further teaches the memory device of claim 7, wherein the vector that indicates the high confidence of the erased state corresponds to the victim memory cell having a first read voltage value that is less than a first soft read threshold (Fig. 5, V1 with respect to bin 1), the first soft read threshold being less than the hard read threshold (Fig. 5, bin 1 with respect to Vr2), and wherein the vector that indicates the high confidence of the programmed state corresponds to the victim memory cell having a second read voltage value that is greater than a second soft read threshold (Fig. 5, V0 with respect to bin 2), the second soft read threshold being greater than the hard read threshold (Fig. 5, bin 2 with respect to Vr2).
As per claim 9: Nguyen further teaches the memory device of claim 1, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 4), refine the initial error correction confidence value, the vector of which indicates a high confidence of an erased state (Fig. 15B, row 4, soft bit 1 for erased state), by maintaining the initial error correction confidence value at a same confidence level (Fig. 15B, confidence levels are maintained as shown in the Table), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 5), refine the initial error correction confidence value, the vector of which indicates a high confidence of a programmed state (Fig. 15B, row 5, soft bit=1 for programmed state), by maintaining the initial error correction confidence value at a same confidence level (Fig. 15B, confidence levels are maintained as shown in the Table).
As per claim 10: Nguyen further teaches the memory device of claim 1, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 8), the vector of which indicates a programmed state, by adjusting the initial error correction confidence value to a lower confidence level (Fig. 15B, row 8, soft bit=0 for programmed state), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 1), the vector of which indicates an erased state, by adjusting the initial error correction confidence value to a lower confidence level (Fig. 15B, row 1, soft bit=0 for erased state).
Not explicitly disclosed is refine the initial error correction confidence value, the vector of which indicates a high confidence of a programmed state and a high confidence of an erased state. However, Cai teaches a confidence value adjusting component (Fig. 9, 920) for adjusting the LLR when aggressor cells have strong influence on victim cells (col. 11, lines 47-52). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to make the adjustments recommended by Nguyen in Fig. 15B from any initial LLR since Nguyen shows likely outcomes of different victim and aggressor cell combinations.
As per claim 11:
Nguyen further teaches the memory device of claim 1, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 1), the vector of which indicates a low confidence of an erased state (Fig. 15B, row 1, soft bit 0 for erased state), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 8), the vector of which indicates a low confidence of a programmed state (Fig. 15B, row 8, soft bit=0 for programmed state),
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 4), the vector of which indicates a high confidence of the erased state (Fig. 15B, row 4, soft bit=1 for erased state), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 5), the vector of which indicates a high confidence of the programmed state (Fig. 15B, row 8, soft bit=1 for programmed state).
Not explicitly disclosed is refine the initial error correction confidence value and adjusting the initial error correction confidence value to reenforce it. However, Cai teaches a confidence value adjusting component (Fig. 9, 920) for adjusting the LLR when aggressor cells have strong influence on victim cells (col. 11, lines 47-52). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to make the adjustments recommended by Nguyen in Fig. 15B from any initial LLR since Nguyen shows likely outcomes of different victim and aggressor cell combinations.
As per claim 12: Nguyen further teaches the memory device of claim 11, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 5), refine the initial error correction confidence value, by adjusting the initial error correction confidence value to a higher confidence level (Fig. 15B, row 5, soft bit=1 for programmed state; therefore it would be obvious to raise any initial LLR for row 5 as suggested by Nguyen), and wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 4), refine the initial error correction confidence value, by adjusting the initial error correction confidence value to a higher confidence level (Fig. 15B, row 4, soft bit=1 for erased state; therefore it would be obvious to raise any initial LLR for row 5 as suggested by Nguyen).
As per claim 13: Cai further teaches the memory device of claim 1, further comprising: an error correction code (ECC) decoder (Fig. 7, 130; col. 4, lines 57-58) configured to receive the refined error correction confidence value, and determine a memory value of the victim memory cell based on the refined error correction confidence value (Fig. 12, 1270).
As per claim 14: Cai further teaches the memory device of claim 1, wherein the victim memory cell is a single-bit memory cell (Fig. 4A, SLC).
As per claim 15: Cai further teaches the memory device of claim 1, wherein the victim memory cell is a multi-bit memory cell (Fig. 4A, MLC).
As per claim 16:
Cai teaches a memory system, comprising: a memory comprising:
a memory comprising a memory cell array arranged according to a plurality of word lines and a plurality of bit lines (Fig. 3); and
a memory controller configured to manage operations of the memory to determine corrective read information (Fig. 1, 100), wherein the memory controller is configured to:
perform a hard read on a victim memory cell based on a hard read threshold (Fig. 4B, R1-R7) to estimate a memory state of the victim memory cell (col.12, lines 45-47),
perform one or more soft reads on the victim memory cell to generate soft information for the victim memory cell (col. 12, lines 47-48),
calculate an initial error correction confidence value of the victim memory cell based on the hard read performed on the victim memory cell and the soft information (Figs. 9-10, 90; col. 12, lines 47-48),
perform a hard read on a neighboring aggressor memory cell to determine a memory state of the neighboring aggressor memory cell (Fig. 12, 1250; col. 12, lines 58-60), the memory state of the neighboring aggressor memory cell being in a high substate or a low substate (Fig. 6), and
refine the initial error correction confidence value of the victim memory cell, based on the hard read on the neighboring aggressor memory cell, to generate a refined error correction confidence value of the victim memory cell (Fig. 12, 1260).
Not explicitly disclosed is performing one or more soft reads on the victim memory cell based on one or more soft read thresholds to generate soft information for the victim memory cell, and refining the initial error correction confidence value based on an LLR value bucket of the initial LLR value. However, Nguyen in an analogous art teaches performing a soft read (col. 9, line 65-col. 10, line 2) for generating soft information based on one or more soft read thresholds (col. 11, lines 8-32), and refining the LLR confidence value (Fig. 14, 212) based on a LLR value bucket (col. 11, lines 27-35).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the LLR of Nguyen in the system of Cai. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Cai teaches using LLRs (col. 10, lines 64-66).
As per claim 17: Cai teaches the memory system of claim 16, wherein the victim memory cell and the neighboring aggressor memory cell are arranged on adjacent word lines of the memory cell array, and wherein the victim memory cell and the neighboring aggressor memory cell are adjacent memory cells (Figs. 5-6).
As per claim 18: Cai teaches the memory system of claim 16, further comprising: an error correction code (ECC) decoder configured to receive the refined LLR value (Fig. 7, 130; col. 4, lines 57-58), and correct a memory value of the victim memory cell based on the refined LLR value (Fig. 12, 1270 and 1280 YES).
As per claim 19: Nguyen further teaches the memory system of claim 16, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 1), the LLR value bucket of which indicates a low confidence of an erased state (Fig. 15B, row 1, soft bit 0 for erased state), and wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 8), the LLR value bucket of which indicates a low confidence of a programmed state (Fig. 15B, row 5, soft bit=0 for programmed state).
Not explicitly disclosed is refining the initial LLR value by adjusting the initial LLR value to a lower confidence level. However, Cai teaches a confidence value adjusting component (Fig. 9, 920) for adjusting the LLR when aggressor cells have strong influence on victim cells (col. 11, lines 47-52). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to make the adjustments recommended by Nguyen in Fig. 15B from any initial LLR since Nguyen shows likely outcomes of different victim and aggressor cell combinations.
As per claim 20: Nguyen further teaches the memory system of claim 19, wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the high substate (Fig. 15B, row 4), refine the initial LLR value, the LLR value bucket of which indicates a high confidence of the erased state (Fig. 15B, row 4, soft bit 1 for erased state), by adjusting the initial LLR value to a higher confidence level or maintaining the initial LLR value at a same confidence level (Nguyen maintains LLR in Fig. 15B), and
wherein the memory controller is configured to, based on the memory state of the neighboring aggressor memory cell being in the low substate (Fig. 15B, row 5), refine the initial LLR value, the LLR value bucket of which indicates a high confidence of the programmed state (Fig. 15B, row 5, soft bit=1 for programmed state), by adjusting the initial LLR value to a higher confidence level or maintaining the initial LLR value at a same confidence level (Nguyen maintains LLR in Fig. 15B).
As per claim 21: Nguyen further teaches the memory system of claim 16, wherein, in the high substate, a read voltage value of the neighboring aggressor memory cell is greater than the hard read threshold (Fig. 5, V0 is greater than Vr2), and wherein, in the low substate, the read voltage value of the neighboring aggressor memory cell is less than the hard read threshold (Fig. 5, V1 is less than Vr2).
As per claim 23: Cai further teaches the method of claim 22, further comprising: selectively modifying, by the memory controller, a log likelihood ratio (LLR) value of the victim memory cell based on the refined error correction confidence value (Fig. 12, 1260-1270).
As per claim 24: Nguyen further teaches the method of claim 22, further comprising: bucketizing, by the memory controller, one or more bits of the victim memory cell into different confidence levels based on a substate of the neighboring aggressor memory cell (Fig. 19A).
As per claim 25: Nguyen further teaches the method of claim 22, further comprising: analyzing, by the memory controller, shifts in a read voltage distribution of the victim memory cell influenced by electric fields from the neighboring aggressor memory cell (Fig. 7B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure are directed to adjacent memory cell interference remedies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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