DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities: In para. [0041] “…second electrode layers 132a and 132b…” should read “…second electrode layers 131b and 132b…”.
Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. US 20210233712 A1 (hereafter referred to as Lee).
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Figure 1: Examiner modified Fig. 5C of Lee pointing out the connection terminals.
Regarding claim 14, Lee discloses:
A multilayer electronic component, comprising: a body (110 – Fig. 1 para. [0045]) including a dielectric layer (111- Fig. 3 para. [0045]) and a plurality of internal electrodes disposed alternately with the dielectric layer in a first direction (121, 122 – Fig. 3 para. [0045]), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface connected to the first and second surfaces and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first to the fourth surfaces and opposing each other in a third direction (Fig. 1 shows a body with a parallelepiped shape); and external electrodes disposed on the third and fourth surfaces (131, 132 – Fig. 3 para. [0045]), wherein the plurality of internal electrodes each include a main portion (121a, 122a – Figs. 5A/B para. [0045]) and a lead-out portion extending from the main portion toward the third or fourth surface (121b, 122b – Figs. 5A/B para. [0045]), the lead-out portion having a connection terminal in contact with a corresponding one of the external electrodes (Figure 1 shown above; para. [0078]), wherein a width of the lead-out portion in the third direction gradually decreases from the main portion to the connection terminal (Figs. 5A/B para. [0079]), wherein the lead-out portion of one internal electrode has an overlap region overlapping the main portion of a neighboring internal electrode among the plurality of internal electrodes in the first direction (Fig. 5C para. [0072]), and wherein, when a width of the connection terminal in the third direction is defined as W1 (H2 – Fig. 5C) and a width of the main portion in the third direction is defined as W2 (H1 – Fig 5C), W1/W2 is 0.4 or higher and 0.75 or lower (para. [0075] discloses a range for H2/H1 of 0.3 to 0.85, overlapping with the claimed range. See Table 1 for specific examples within the claimed range).
Regarding claim 15, Lee discloses:
The multilayer electronic component of claim 14, wherein, when a maximum length of the overlap region in the second direction is defined as Lo, Lo is 25 μm or greater (L1 – Fig. 5C para. [0072] discloses 0.05 mm (50 um) or greater, overlapping with the claimed range. See Table 1 for specific examples within the claimed range).
Regarding claim 16, Lee discloses:
The multilayer electronic component of claim 15, wherein Lo is 75 μm or lower (L1 – Fig. 5C para. [0072] discloses 0.05 mm (50 um) or more, overlapping with the claimed range. See Table 1 for specific examples within the claimed range).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 17, Lee discloses:
The multilayer electronic component of claim 14, wherein, when a region of the lead-out portion other than the overlap region is defined as a margin region (Lm – Fig. 5C and Lm’ – Fig. 8. In Lee, Lm’ is used to denote when there is no overlap and should be seen as interchangeable with Lm as both referring to the margin region). Lee does not explicitly disclose wherein a maximum length of the margin region in the second direction is 5 μm or greater and 45 μm or lower.
However, Lee teaches that the length of the margin region is a result effective variable. Particularly, when the margin region is too large (i.e., a length of the margin region is equal to the length of the lead-out portion), warpage stress may be concentrated at ends of the main portion, causing cracks to occur (para. [0070]). Furthermore, if the length of the margin region is too small, the capacitor may be shorted, making the capacitor non-functional.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to construct the capacitor of Lee having a maximum length of the margin region in the second direction is 5 μm or greater to prevent the potentially shorting the capacitor, and 45 μm or lower to prevent cracks from occurring as taught by Lee. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 1-4, 6-7, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Nakamura et al. JP 2010093136 A (hereafter referred to as Nakamura).
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Figure 2: Examiner modified Fig. 5C of Lee showing the top right corner after modification by Nakamura. As there is a non-overlap region, the first saddle portion and the second saddle portion do not overlap.
Regarding claim 1, Lee discloses:
A multilayer electronic component, comprising: a body (110 – Fig. 1 para. [0045]) including a dielectric layer (111- Fig. 3 para. [0045]) and a plurality of internal electrodes disposed alternately with the dielectric layer in a first direction (121, 122 – Fig. 3 para. [0045]), the body including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface connected to the first and second surfaces and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first to the fourth surfaces and opposing each other in a third direction (Fig. 1 shows a body with a parallelepiped shape); and external electrodes disposed on the third and fourth surfaces (131, 132 – Fig. 3 para. [0045]), wherein the plurality of internal electrodes each include a main portion (121a, 122a – Figs. 5A/B para. [0045]) and a lead-out portion extending from the main portion toward the third surface or the fourth surface (121b, 122b – Figs. 5A/B para. [0045]), the lead-out portion having a connection terminal in contact with a corresponding one of the external electrodes (Figs. 5A/B para. [0079]), wherein a width of the lead-out portion in the third direction gradually decreases from the main portion to the connection terminal (Fig. 5C para. [0072]), wherein the lead-out portion of one internal electrode has an overlap region overlapping the main portion of a neighboring internal electrode among the plurality of internal electrodes in the first direction (Fig. 5C para. [0072]).
Lee fails to disclose wherein the main portion includes a first saddle portion disposed on an end portion of the main portion spaced apart from the lead-out portion, and the lead-out portion includes a second saddle portion disposed on a side end portion of the lead-out portion in the third direction, wherein thicknesses of the first and second saddle portions in the first direction are greater than a thickness of a central portion in the second direction of the main portion.
Nakamura discloses wherein the main portion includes a first saddle portion disposed on an end portion of the main portion spaced apart from the lead-out portion (16B – Fig. 1B para. [0015]), and the lead-out portion includes a second saddle portion disposed on a side end portion of the lead-out portion in the third direction (16C, 16D – Fig. 1C para. [0015]), wherein thicknesses of the first and second saddle portions in the first direction are greater than a thickness of a central portion in the second direction of the main portion (para. [0015]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include saddle portions of Nakamura to the main portion including the side end of the lead-out portion of Lee to improve connectivity and suppress lamination misalignment (paras. [0010] and [0015]).
Regarding claim 2, Lee as modified by Nakamura further discloses:
The multilayer electronic component of claim 1, wherein, when a width of the connection terminal in the third direction is defined as W1 (H2 – Fig 5C of Lee) and a width of the main portion in the third direction is defined as W2 (H1 – Fig 5C of Lee), W1/W2 is 0.4 or higher and 0.75 or lower (para. [0075] of Lee discloses a range for H2/H1 of 0.3 to 0.85, overlapping with the claimed range. See Table 1 of Lee for specific examples within the claimed range).
Regarding claim 3, Lee as modified by Nakamura further discloses:
The multilayer electronic component of claim 1, wherein, when a maximum length of the overlap region in the second direction is defined as Lo, Lo is 25 μm or greater (L1 – Fig. 5C para. [0072] of Lee discloses 0.05 mm (50 um) or greater, overlapping with the claimed range. See Table 1 of Lee for specific examples within the claimed range).
Regarding claim 4, Lee as modified by Nakamura further discloses:
The multilayer electronic component of claim 3, wherein Lo is 75 μm or lower (L1 – Fig. 5C para. [0072] of Lee discloses 0.05 mm (50 um) or greater, overlapping with the claimed range. See Table 1 of Lee for specific examples within the claimed range).
Regarding claim 6, Lee as modified by Nakamura further discloses:
The multilayer electronic component of claim 1, wherein, when a region of the lead-out portion other than the overlap region is defined as a margin region (Lm – Fig. 5C and Lm’ – Fig. 8 of Lee. In Lee, Lm’ is used to denote when there is no overlap and should be seen as interchangeable with Lm as both referring to the margin region). Lee does not explicitly disclose wherein a maximum length of the margin region in the second direction is 5 μm or greater and 45 μm or lower.
However, Lee teaches that the length of the margin region is a result effective variable. Particularly, when the margin region is too large (i.e., a length of the margin region is equal to the length of the lead-out portion), warpage stress may be concentrated at ends of the main portion, causing cracks to occur (para. [0070]). Furthermore, if the length of the margin region is too small, the capacitor may be shorted, making the capacitor non-functional.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to construct the capacitor of Lee having a maximum length of the margin region in the second direction is 5 μm or greater to prevent the potentially shorting the capacitor, and 45 μm or lower to prevent cracks from occurring as taught by Lee. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 7, Lee as modified by Nakamura further discloses:
The multilayer electronic component of claim 1, wherein the side end portion in the third direction of the lead-out portion has a curved shape (Fig. 5C of Lee).
Regarding claim 13, Lee as modified by Nakamura further discloses:
The multilayer electronic component of claim 1, wherein in the cross-section of the body in the first and second directions, passing through a region adjacent to a side end portion in the third direction of the main portion, one end of the first saddle portion in the third direction of one internal electrode does not overlap one end of the second saddle portion in the third direction of a neighboring internal electrode among the plurality of internal electrodes in the first direction (Figure 2 shown above shows that the first saddle portion and the second saddle portion do not overlap when Lee is modified by Nakamura. This is a consequence of the non-overlap portion of Lee).
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Nakamura and further in view of Park et al. US 2020/0203072 A1 (hereafter referred to as Park).
Regarding claim 10, Lee as modified by Nakamura further discloses:
The multilayer electronic component of claim 1, wherein the body has a corner portion connecting the third surface to the fifth surface, connecting the third surface to the sixth surface, connecting the fourth surface to the fifth surface, and connecting the fourth surface to the sixth surface (Fig. 1 of Lee shows a body with a parallelepiped shape with a corner portion where the surfaces of the body meet) and wherein the connection terminal is spaced apart from the corner portion (Figure 2 shown above). Lee fails discloses the corner portion having a rounded shape. Nakamura fails to disclose the corner portion having a rounded shape.
Park discloses the corner portion having a rounded shape (R2 – Fig. 5 para. [0098] and Abstract).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the corner portion of Lee as modified by Nakamura to have the rounded corner portion of Park in order to more reliably prevent chips from being formed on the body and improve moisture reliability (paras. [0060-0061] of Park).
Regarding claim 11, Lee as modified by Nakamura and further modified by Park discloses:
The multilayer electronic component of claim 10. Lee fails to disclose wherein, when a radius of curvature of the corner portion is defined as Rc, and a distance between a side end portion in the third direction of the main portion and the fifth or sixth surface of the body is defined as Wm, Rc and Wm satisfy Rc > Wm.
Nakamura fails to discloses wherein, when a radius of curvature of the corner portion is defined as Rc, and a distance between a side end portion in the third direction of the main portion and the fifth or sixth surface of the body is defined as Wm, Rc and Wm satisfy Rc > Wm.
Park discloses wherein, when a radius of curvature of the corner portion is defined as Rc (R2 – Fig. 5), and a distance between a side end portion in the third direction of the main portion and the fifth or sixth surface of the body is defined as Wm (Wm – Fig. 4), Rc and Wm satisfy Rc > Wm (para. [0103] discloses that advantageously 1.0 ≤ R2/Wm ≤ 1.4 meaning that R2 > Wm).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the radius of curvature larger than the distance between a side end portion in the third direction of the main portion and the fifth or sixth surface of the body in order to better prevent chipping (paras. [0101-0104] of Park).
Regarding claim 12, Lee as modified by Nakamura and further modified by Park discloses:
The multilayer electronic component of claim 11. Lee fails to disclose wherein Rc and Wm satisfy Rc ≤ 22 μm and Wm ≤ 20 μm. Nakamura fails to disclose wherein Rc and Wm satisfy Rc ≤ 22 μm and Wm ≤ 20 μm.
Park discloses wherein Rc and Wm satisfy Rc ≥ 5 μm (para. [0098] significantly overlapping with the claimed range) and Wm ≤ 15 μm (para. [0097] significantly overlapping with the claimed range).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to impose the range of 5 um or more on Rc to mitigate potential chipping and to impose the range of 15 um or less on Wm to protect the internal electrodes from moisture and improve capacitance per unit volume (para. [0097 of Park).
Allowable Subject Matter
Claim(s) 5, 8-9, and 18-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 5, prior art cannot be found within the claimed range for t1/te. The closest prior art is Nakamura which discloses a minimum ratio of (1.2 + 0.11) / 1.2 or 1.092. Regarding claims 8-9 and 18-19, prior art cannot be found which discloses the area ratio of the non-overlap portion to the main portion. Although, prior art can be found wherein there is a non-overlap region (e.g., Lee et al. US 20210233712 A1 and Yamauchi et al US 20040027787 A1), it cannot be verified whether the ratio would fall into the claimed range.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2004/0027787 A1: Fig. 21 para. [0008]
JP 2005285801 A: t1, t2 – Fig. 1
JP 2015141982 A: Fig. 1 b/c
JP 2015053512 A: t1, t2 – Fig. 5 paras. [0037] and [0046]
US 10741328 B2: Fig. 4
US 2013/0279070 A1: Fig. 2
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/T.J.T./Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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