DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claim 15 be found allowable, claim 17 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-5, 11-14 and 18-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4-5, 19-20 and 22-23 of U.S. Patent No. 12,159,059. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims 1-2, 4-5, 19-20 and 22-23 of Patent No. 12,159,059 recite all of the elements of Claims 2-5, 11-14 and 18-21 of the instant application, wherein the claims of Patent No. 12,159,059 recite additional narrowing limitations.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8, 10-15 and 17-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Reina (US PGPUB 2020/0202938).
With regard to Claim 2, Reina teaches a memory system, comprising:
one or more memory devices (Fig. 1: Memory Units 120); and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to (Fig. 1: Controller 106):
receive an indication of a count of program/erase cycles associated with an address of the memory system; determine whether the count of program/erase cycles associated with the address satisfies a threshold; and adjust a duration for performing a programming operation on the address based at least in part on determining whether the count of program/erase cycles satisfies the threshold ([0010] “The memory device... can decrease the voltage step size when the device conditions are more likely to cause errors (e.g., .... when there are above a threshold number of program/erase cycles),” wherein the “number of program/erase cycles” of the memory device are “the count of program/erase cycles associated with the address” since the address is within the memory device. [0043] “At block 310, a reduced voltage step size can be selected. The reduced voltage step size, when in strenuous conditions, causes smaller iterations of voltage to be applied... The standard voltage step size, when not in strenuous conditions, allows for fewer iterations of voltage to be applied, reducing the time need to perform the program operation,” wherein the selection of a “reduced voltage step size” increases the duration for performing the programming operation.); and
perform the programming operation using the adjusted duration ([0045] “At block 312, the program operation can be performed using the selected voltage step size, as described above in relation to FIG. 2.”).
With regard to Claim 3, Reina teaches the memory system of claim 2, wherein the processing circuitry is configured to cause the memory system to:
adjust a distribution of a states stored in a memory cell based at least in part on determining that the count of program/erase cycles satisfies the threshold, wherein performing the programming operation is based at least in part on adjusting the distribution of the states ([0023] “The memory device 102 can use processing levels 154 for storing or accessing data. The processing levels 154 can include thresholds or operating levels for voltage or current. The processing levels 154 can include a threshold voltage 156, a read level voltage 158, a programming level voltage 160, one or more programming voltage steps 162A-N, or any combination thereof.” [0037] “The memory system 100 can dynamically calculate or adjust the processing levels 154 based on feedback information... The memory system 100 can dynamically adjust the distribution targets based on feedback data using a target calibration mechanism 178 to adjust for the shift in the measured values,” wherein the “feedback” information is associated with the “threshold number of program/erase cycles” as discussed above.).
With regard to Claim 4, Reina teaches the apparatus of claim 3, wherein the processing circuitry is configured to cause the memory system to:
determine whether to improve a reliability of data stored at the address of the memory system based at least in part on determining that the count of program/erase cycles satisfies the threshold, wherein adjusting the distribution of the states stored in the memory cell is based at least in part on determining to improve the reliability of the data stored at the address ([0041] “At block 306, method 300 can determine whether the identified device conditions are strenuous device conditions... strenuous device conditions can be a number of program/erase cycles being above a threshold.” [0043] “If there are strenuous device conditions, method 300 can proceed to block 310... At block 310, a reduced voltage step size can be selected. The reduced voltage step size, when in strenuous conditions, causes smaller iterations of voltage to be applied, reducing the likelihood that memory cells will be over-charged,” wherein “reducing the likelihood that memory cells will be over-charged” serves to “improve the reliability of data”.).
With regard to Claim 5, Reina teaches the memory system of claim 2, wherein the processing circuitry is configured to cause the memory system to:
adjust a trim parameter for operating the memory system based at least in part on determining whether the count of program/erase cycles satisfies the threshold, the programming operation is performed using the adjusted trim parameter ([0041] “At block 306, method 300 can determine whether the identified device conditions are strenuous device conditions... strenuous device conditions can be a number of program/erase cycles being above a threshold.” [0043] “If there are strenuous device conditions, method 300 can proceed to block 310... At block 310, a reduced voltage step size can be selected,” wherein the “voltage step size” is the “trim parameter”.).
With regard to Claim 6, Reina teaches the memory system of claim 2, wherein the processing circuitry is configured to cause the memory system to:
determine that a quantity of errors associated with the address of the memory system fails satisfies a threshold based at least in part on determining whether the count of program/erase cycles satisfies the threshold, wherein performing the programming operation is based at least in part on determining that the quantity of error fails to satisfy the threshold ([0040] “At block 304, method 300 can determine device conditions for the program operation. Device conditions can comprise various contexts such as... a rate of errors for a block containing the target memory cells.” [0044] “In some cases, trigger conditions can cause the selecting of reduced voltage step sizes. For example, an error rate at which the memory device is over-charging memory cells can be tracked, and when this rate exceeds a threshold it can trigger a reduction in the voltage step size.”).
With regard to Claim 8, Reina teaches the memory system of claim 2, wherein the processing circuitry is configured to cause the memory system to:
adjust a trim parameter to a first value for operating the memory system based at least in part on determining that the count of program/erase cycles satisfies the threshold ([0040] “At block 304, method 300 can determine device conditions for the program operation. Device conditions can comprise various contexts such as... a rate of errors for a block containing the target memory cells.” [0044] “In some cases, trigger conditions can cause the selecting of reduced voltage step sizes. For example, an error rate at which the memory device is over-charging memory cells can be tracked, and when this rate exceeds a threshold it can trigger a reduction in the voltage step size.” Fig. 3: Step 310 - Select reduced voltage step size).; or
adjust the trim parameter to a second value for operating the memory system based at least in part on determining that the count of program/erase cycles fails to satisfy the threshold ([0043] “If there are not strenuous device conditions, method 300 can proceed to block 308... At block 308, a standard voltage step size can be selected.” Fig. 3: Step 308 - Select standard voltage step size).
With regard to Claim 10, Reina teaches the memory system of claim 2, wherein, to receive the indication of the count of program/erase cycles, the processing circuitry is configured to cause the memory system to:
receive, from a host system, a sequence of one or more commands to perform the programming operation on the address ([0009] “The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.” [0039] “At block 302, a program operation is initiated to record values in target cells of a memory.”).
With regard to Claims 11-15, these claims are equivalent in scope to Claims 2-6 rejected above, merely having a different independent claim type, and as such Claims 11-15 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 2-6.
With further regard to Claim 11, the claim recites additional elements not specifically addressed in the rejection of Claim 2. The Reina reference also anticipates these additional elements of Claim 11, for example, Reina teaches:
A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to [perform operations] ([0049] “Processing device 402 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like... The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein.” [0050] “The data storage system 418 can include a machine-readable storage medium 424 (also known as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methodologies or functions described herein. The instructions 426 can also reside, completely or at least partially, within the main memory 404 and/or within the processing device 402.”).
With regard to Claim 17, this claim is equivalent in scope to Claim 6 rejected above, merely having a different independent claim type, and as such Claim 17 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 6.
With regard to Claims 18-21, these claims are equivalent in scope to Claims 2-5 rejected above, merely having a different independent claim type, and as such Claims 18-21 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 2-5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Reina as applied to Claims 5 and 12 above, and further in view of Lin et al. (US PGPUB 2021/0342097).
With regard to claim 7, Reina teaches all the limitations of claim 5 as described above. Reina does not teach the write amplification determination as described in claim 7. Lin teaches wherein the processing circuitry is configured to cause the memory system to:
determine that a write amplification associated with the memory system satisfies a threshold based at least in part on determining whether the count of program/erase cycles satisfies the threshold, wherein performing the programming operation is based at least in part on determining that the write amplification satisfies the threshold ([0101] “the life cycle parameters can be one of TeraBytes Written (TBW), Program/Erase count (P/E count).” [0106] “In step S1102, the write command is received from the host system. In step S1104, it is determined whether the life cycle parameter is greater than the preset cycle threshold... If it is determined that the life cycle parameter is greater than the preset cycle threshold (step S1104, the determining result is YES), then in step S1108, it is determined whether the write amplification factor is greater than the preset threshold. If it is determined that the write amplification factor is not greater than the preset threshold (step S1108, the determining result is NO), then the data is written into the first area in step S1110.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Reina with the write amplification determination as taught by Lin in order “to avoid reduction of the service life of flash memory module” (Lin [0007]).
With regard to Claim 16, this claim is equivalent in scope to Claim 7 rejected above, merely having a different independent claim type, and as such Claim 16 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 7.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Reina as applied to Claim 2 above, and further in view of Melik-Martirosian (US PGPUB 2012/0239858; hereinafter “Melik”).
With regard to claim 9, Reina teaches all the limitations of claim 2 as described above. Reina does not teach the management scheme as described in claim 9. Melik teaches wherein the processing circuitry is configured to cause the memory system to:
identify a management scheme for operating the memory system based at least in part on a look-up table and the count of program/erase cycles, wherein performing the programming operation is based at least in part on identifying the management scheme ([0043] “controller 101 may access one or more trigger lookup tables stored on storage medium 102 to determine when a trigger should take place. The one or more lookup tables may provide trigger information based on a number of P/E cycles or range of cycles and/or a duration as previously described. In some aspects, adjustments to parameter values are planned as the drive ages via one or more parameter lookup tables, which may be indexed by cycle and/or timestamp. Once a trigger event is met (for example, ‘BOL’, ‘low cycles’, ‘mid cycles’, ‘EOL’), controller 101 accesses the one or more parameter lookup tables to facilitate adjustment of the ISPP and/or ISPE parameters.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Reina with the write management scheme as taught by Melik in order “to achieve a higher number of cycles the device can undergo, thereby improving the reliability and endurance of flash memory, making it suitable for enterprise applications” (Melik [0024]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Kim (US PGPUB 2015/0270852) discloses a method of programming target memory cells of a nonvolatile memory device which includes programming the target memory cells using an incrementally adjusted program time based on a determined bit error rate (BER), wherein consideration is given to the number of program/erase cycles associated with a target flash memory cell as well.
Suh et al. (“A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” 1995) discusses a memory system having an incremental step pulse programming scheme (ISPP) which is introduced to dynamically optimize program voltage according to cell characteristics on a cell-by-cell basis.
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 December 27, 2025