DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d) which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is objected to because:
The Cross-Reference to Related Applications section in paragraph [0001] of the specification does not provide the status of U.S. application serial no. 18,498,069 (i.e., now U.S. Patent No. 12,197,285).
Drawings
The formal drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claim 1-20 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,197,285.
For example, claim 1 of the instant application teaches “a flash memory apparatus, comprising: a flash memory module comprising a plurality of storage blocks; and a flash memory controller, coupled to the flash memory module, configured for enabling a single-level-cell (SLC) programming mode to determine a storage block of a chip of the flash memory module as an SLC block by sending a set feature command sequence which sequentially comprises a set feature command indicated by a hexadecimal value of EFh, a specific address of a control register of a chip of the flash memory module, and a specific hexadecimal value of 01h to be written into the control register, into the flash memory module, so as to make the chip of the flash memory module enter an SLC mode after the flash memory module receives the hexadecimal value of EFh and the specific hexadecimal value of 01h, the SLC block to be programmed based on an SLC programming; wherein the flash memory controller is arranged to enable a multiple-level-cell (MLC) programming mode by sending a set feature command sequence which sequentially comprises a set feature command indicated by the hexadecimal value of EFh, a specific address of a control register of a chip of the flash memory module, and a specific hexadecimal value of 02h to be written into the control register, into the flash memory module. Whereas claim 1 of U.S. Patent No. 12,197,285 teaches “a flash memory apparatus, comprising: a flash memory module comprising a plurality of storage blocks; and a flash memory controller, coupled to the flash memory module, configured for enabling a single-level-cell (SLC) programming mode to determine a storage block of a chip of the flash memory module as an SLC block by sending a set feature command sequence which sequentially comprises a set feature command indicated by a hexadecimal value of EFh, a specific address of a control register of a chip of the flash memory module, and a specific hexadecimal value of 01h to be written into the control register, into the flash memory module, so as to make the chip of the flash memory module enter an SLC mode after the flash memory module receives the hexadecimal value of EFh and the specific hexadecimal value of 01h, the SLC block to be programmed based on an SLC programming; wherein the flash memory controller is used for: writing a plurality of groups of data into the flash memory module; executing an error correction and a de-randomize operation upon the groups of data to generate de-randomized data; executing a randomize operation upon the de-randomized data to generate randomized data; and performing error code encoding upon the randomized data and writing the randomized data into the flash memory module”.
Rationales:
Although the conflicting claims are not identical, they are not patentably distinct from each other because the additional limitation (enabling a multiple-level-cell (MLC) programming mode by sending a set feature command sequence) of instant application would have been obvious to one of ordinary skill in the art at the time of invention and on the other side eliminating several limitations “executing an error correction and a de-randomize operation upon the groups of data to generate de-randomized data; executing a randomize operation upon the de-randomized data to generate randomized data; and performing error code encoding upon the randomized data and writing the randomized data into the flash memory module” which is obvious broadens the scope of claim 1. It is obvious the limitations of claim 1 of the Patent ‘285 read on the limitations of claim 1 of the instant application. Further, it has been held that the omission of an element and its function is an obvious expedient if the remaining elements perform the same functions as before. See /n re Karlson, 136 USPQ 184(CCPA 1963). Also note Ex parte Rainu, 168 USPQ 375 (BdPat App&int 1970); omission of a reference element whose function is not needed would be obvious to one skilled in the art.
Other parallel independent claims of the instant application have corresponding issues with the independent claims of U.S. Patent No. 12,197,285 are also rejected under non-statutory obviousness-type double patenting for the same rationales discussed above.
Other parallel dependent claims have corresponding issues with the dependent claims of U.S. Patent No. 12,197,285 are also rejected under non-statutory obviousness-type double patenting.
"A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQat 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Allowable Subject Matter
The Examiner would like to point out that a properly executed Terminal Disclaimer will overcome the rejection and thereafter the claims can be in condition for allowance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kato et al. (U.S. PN:7,248,504) describes a control circuit (CONT)109 controls reading, erasing, and writing operation control sequences and operating power switching in the flash memory modules 118 according to control data set on the control register of the flash memory controller 116.
Pignatelli (US 2013/0318285) teaches a flash controller Device, is described using an interruptible micro coded state machine engine to provide these features. An apparatus for storing digital data, is disclosed, having a controller, a flash memory controller, the flash memory controller in communication with the controller and with a plurality of FLASH memory circuits.
Weathers et al. (US 2013/0318422) teaches a Flash memory 103 may comprise single-level cell (SLC) memory, multi-level cell (MLC) memory and/or three-level cell (TLC) memory device.
Chow et al. (US 7,877,542) teaches one flash memory module 103 may comprise one or more flash memory chips or integrated circuits. The flash memory chips may be single-level cell (SLC) or multi-level cell (MLC).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112