CTNF 18/939,521 CTNF 79649 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 7/17/2025 was considered by the examiner. Drawings The drawings received on11/7/2024 have been accepted by the examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Jiao et al. [“The Design and Implementation of a Capacity-Variant Storage System”] . Claim 1, Jiao et al. discloses a data storage device comprising: a memory device including a plurality of memory areas; and a controller [section 3.2, discloses a flash based capacity variant SSD (CV-SSD) controlled by flash translation layer (FTL) firmware managing blocks partitioned across physical flash channels and dies] configured to classify the plurality of memory areas as a plurality of storage areas, manage the plurality of storage areas by mapping logical addresses externally received to each of the plurality of storage areas [Section 3.2; the controller maps external host side Logical Block Addresses (LBAs) to internal physical blocks. These physical blocks are classified into discrete storage allocation pools or segments], monitor defect information generated in a memory area corresponding to each of the plurality of storage areas, and remap the logical addresses for each of the plurality of storage areas based on the defect information [The FTL monitors runtime metrics including bit error rates, erase failures, and retirement status for each storage segment. When a pool’s reliability drops, the FTL changes the mapping table, section 3.1]. Claim 2, Jiao et al. discloses the data storage device according to claim 1, wherein the controller is further configured to: determine, based on defect information in each of the plurality of storage areas, a decrease target storage area for decreasing a number of mapped logical addresses [FTL identifies flash memory regions accumulating hardware defects, the controller designates those areas for structural down scaling. The number of Logical Block Numbers mapped to these failing areas is actively reduced to isolate bad blocks, section 3.1] and an increase target storage area for increasing a number of mapped logical addresses [uses an active over provisioning pool and healthy channels to absorb host writes. The healthy zones are designated to receive the logical mapping lines stripped from the failing blocks, section 3.1]; determine a number of logical addresses to be mapped to each of the plurality of storage areas based on the determination; and remap the logical addresses to each of the plurality of storage areas based on the number of logical addresses to be mapped, which is determined for each of the plurality of storage areas [The controller does not use static sizing. It executes a runtime calculation to determine the number of active LPNs each pool can safely handle based on its current health state, modifying the global mapping table to reflect these localized updates]. Claim 3, Jiao et al. discloses the data storage device according to claim 2, wherein the controller is further configured to: determine a reference value, compare a defect information monitoring value of each of the plurality of storage areas with the reference value, determine a storage area, of which the defect information monitoring value is greater than the reference value, as the decrease target storage area, and determine a storage area, of which the defect information monitoring value is less than the reference value, as the increase target storage area [Section 3.2.3;discloses determining a reference baseline to classify pools into decrease targets or increase targets; the controller monitors localized block health indicators against a baseline failure threshold; pools tracking above this defect rate are targeted for size reduction, while pools tracking below are maintained or expanded]. Claim 4, Jiao et al. discloses the data storage device according to claim 3, wherein the controller is further configured to determine an average of the defect information monitoring value of each of the plurality of storage areas as the reference value [Section 2.1; uses a running drive wide average metric to determine relative wear distribution; the FTL tracks the mean erase counts and global error rates across all combined memory pools to serve as the reference benchmark for identifying abnormally fast degrading segments]. Claim 5, Jiao et al. discloses the data storage device according to claim 3, wherein the controller is further configured to: determine a number of logical addresses to be decreased for each storage area of the decrease target storage area in proportion to a value obtained by subtracting the reference value from the defect information monitoring value of each storage area, and determine a number of logical addresses to be increased for each storage area of the increase target storage area in proportion to a value obtained by subtracting the defect information monitoring value of each storage area from the reference value [Section 1 and 3.1; executes an online, fine grained reduction where capacity drops match the error severity; the system avoids binary shutdowns by reducing capacity in an online, fine grained manner…]. Claim 6, Jiao et al. discloses the data storage device according to claim 3, wherein the controller is further configured to: determine a number of logical addresses to be decreased for each storage area of the decrease target storage area in proportion to a value obtained by subtracting the reference value from the defect information monitoring value of each storage area, acquire a total number of logical addresses to be decreased by adding up the number of logical addresses to be decreased for each storage area of the decrease target storage area, acquire a number of storage areas corresponding to the increase target storage area, and equally determine a number of logical addresses to be increased for each storage area of the increase target storage area based on a value obtained by dividing the total number of logical addresses to be decreased by the number of storage areas corresponding to the increase target storage area [Section 3.2.1; distributes host write traffic uniformly across remaining healthy lines to prevent wear hotspots; when logical space is withdrawn from an error prone pool, the total aggregate of remaining active low defect pools are equally designated to absorb the shifted write distribution lines]. Claim 7, Jiao et al. discloses the data storage device according to claim 5, wherein the controller is further configured to: remap the logical addresses to each of the plurality of storage areas based on the number of logical addresses to be decreased or the number of logical addresses to be increased, which is determined for each storage area; and remap the logical addresses mapped to each storage area to increase sequentially [Section 3.1; dynamically re-indexes the remaining capacity to ensure standard filesystem compatibility; following a capacity modification, the FTL collapses internal tracking gaps and maps the surviving logical addresses to form a contiguous monotonically increasing sequence exported to the host]. Claim 8, Jiao et al. discloses the data storage device according to claim 5, wherein the controller is configured to: remap the logical addresses to each of the plurality of storage areas based on the number of logical addresses to be decreased or the number of logical addresses to be increased, which is determined for each storage area; release mapping of logical addresses for as many as the number of logical addresses to be decreased among previously mapped logical addresses for the decrease target storage area; and map logical addresses unmapped from the decrease target storage area for an increase target storage area [Section 3.1; explicitly hands off unmapped logical slots from broken regions to stable zones]. Claim 9, Jiao et al. discloses the data storage device according to claim 1, wherein the controller is configured to: determine a logical address remapping activation condition; and remap the logical addresses to each of the plurality of storage areas only when the logical address remapping activation condition is satisfied [Section 3.3; gates capacity shifting events using operational hardware triggers]. Claim 10, Jiao et al. discloses the data storage device according to claim 1, wherein the defect information includes a bad block count value [Section 3.2.3; tracks individual retired blocks as the primary health unit]. Claims 11-20 are rejected using the same rationale as Claims 1-10 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Feng [US 2025/0298741]; Memory Systems and Operation Methods Thereof and Storage Devices and Operation Methods Thereof. Par. 0104 and Claim 3. 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To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MIDYS ROJAS/ Primary Examiner, Art Unit 2133 Application/Control Number: 18/939,521 Page 2 Art Unit: 2133 Application/Control Number: 18/939,521 Page 3 Art Unit: 2133 Application/Control Number: 18/939,521 Page 4 Art Unit: 2133 Application/Control Number: 18/939,521 Page 5 Art Unit: 2133 Application/Control Number: 18/939,521 Page 6 Art Unit: 2133
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