DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5,12-15, 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,2,5,7,12,13,14 of U.S. Patent No.12158501. Although the claims at issue are not identical, they are not patentably distinct from each other because 1-5,12-15, 17 are anticipated by claims 1,2,5,7,12,13,14.
18939673 12158501
1. An integrated circuit comprising: a monitoring circuit comprising a plurality of devices, wherein the monitoring circuit is configured to: select a device, among the plurality of devices, to be monitored; generate a first signal, which is an analog signal, based on input digital data; apply the first signal to the selected device to be monitored; and generate output digital data based on a second signal generated by the device to be monitored.
3. The integrated circuit of claim 1, wherein the plurality of devices are arranged in an array form, wherein the monitoring circuit further comprises a selection circuit configured to the device to be monitored, and wherein the selection circuit comprises a first multiplexer configured to select one or more rows of the array and a second multiplexer configured to select one or more columns of the array.
4. The integrated circuit of claim 3, wherein the selection circuit further comprises a feedback amplifier configured to compensate for noise of a voltage signal, the feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting one of the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to each of the plurality of devices in parallel.
1. A monitoring circuit comprising: a sensor circuit comprising: a plurality of devices, and a selection circuit configured to select a first device to be monitored among the plurality of devices; an input circuit configured to apply, based on input digital data, a first signal to the first device to be monitored; and an output circuit configured to generate output digital data based on a second signal generated by the sensor circuit, wherein the input circuit comprises a digital-to-analog converter configured to convert the input digital data into the first signal, and the output circuit comprises an analog-to-digital converter, wherein the selection circuit comprises a feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting the first device among the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to the first device through a first switch and a second switch of a first multiplexer in parallel.
2. The integrated circuit of claim 1, wherein the plurality of devices comprise at least one of an n-channel metal-oxide-semiconductor (NMOS) transistor, a p-channel metal-oxide-semiconductor (PMOS) transistor, or a resistor.
2. The monitoring circuit of claim 1, wherein the plurality of devices comprise at least one of an n-channel metal-oxide-semiconductor (NMOS) transistor, a p-channel metal-oxide-semiconductor (PMOS) transistor, or a resistor.
5. The integrated circuit of claim 4, wherein the plurality of devices comprise transistors, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to drain terminals of the transistors in parallel.
5. The monitoring circuit of claim 4, wherein the plurality of devices comprise transistors, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to drain terminals of the transistors in parallel.
12. The integrated circuit of claim 1, further comprising a control circuit configured to: store monitoring result data of the plurality of devices, based on the output digital data; and compensate for a supply voltage or a supply frequency, based on the monitoring result data.
12. The monitoring circuit of claim 1, further comprising a control circuit configured to store monitoring result data of the plurality of devices, based on the output digital data.
13. The monitoring circuit of claim 12, wherein the control circuit configured to compensate a supply voltage or a supply frequency, based on the monitoring result data.
13. The integrated circuit of claim 1, further comprising a sub-monitoring circuit comprising a ring oscillator configured to monitor frequency performance of the plurality of devices.
14. The monitoring circuit of claim 1, further comprising a sub-monitoring circuit comprising a ring oscillator configured to monitor frequency performance of the plurality of devices.
14. A process characteristics monitoring method performed by a monitoring circuit, the monitoring method comprising: selecting a device, among a plurality of devices, to be monitored; generating a first signal, which is an analog signal, based on input digital data; applying the first signal to the selected device to be monitored; and generating output digital data based on a second signal generated by the device to be monitored.
1. A monitoring circuit comprising: a sensor circuit comprising: a plurality of devices, and a selection circuit configured to select a first device to be monitored among the plurality of devices; an input circuit configured to apply, based on input digital data, a first signal to the first device to be monitored; and an output circuit configured to generate output digital data based on a second signal generated by the sensor circuit, wherein the input circuit comprises a digital-to-analog converter configured to convert the input digital data into the first signal, and the output circuit comprises an analog-to-digital converter, wherein the selection circuit comprises a feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting the first device among the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to the first device through a first switch and a second switch of a first multiplexer in parallel.
15. The monitoring method of claim 14, wherein the plurality of devices comprise at least one of an n-channel metal-oxide-semiconductor (NMOS) transistor, a p-channel metal-oxide-semiconductor (PMOS) transistor, or a resistor.
2. The monitoring circuit of claim 1, wherein the plurality of devices comprise at least one of an n-channel metal-oxide-semiconductor (NMOS) transistor, a p-channel metal-oxide-semiconductor (PMOS) transistor, or a resistor.
17. The monitoring method of claim 14, wherein the second signal comprises a current signal, and wherein the generating of the output digital data further comprises converting the second signal into a voltage signal.
7. The monitoring circuit of claim 1, wherein the second signal comprises a current signal, and wherein the output circuit further comprises a current-to-voltage converter configured to convert the second signal into a voltage signal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881)
Regarding claims 1,14, Meninger et al. teach An integrated circuit comprising:
a monitoring circuit comprising a plurality of devices, (An apparatus includes a plurality of semiconductor devices and an electrical input device for applying voltage to the plurality of semiconductor devices. Abstract) wherein the monitoring circuit is configured to:
select a device, among the plurality of devices, to be monitored; (There is a switching array configured to sequentially interconnect the electrical input device to each of the semiconductor devices and disconnect the other semiconductor devices from the electrical input device. Abstract)
generate a first signal, which is an analog signal, based on input digital data; suggested by (Electrical input device 18 is used to apply a voltage to a terminal, such as the gate in an FET or the base in a BJT, of the device under test 14 to activate the device for testing. Electrical input device 18 is typically implemented as a digital-to-analog converter (DAC) and may be configured as a passive DAC such as a resistor ladder network referenced to the on-chip supply voltage to eliminate the need for an additional pin on the IC. [0021]
apply the first signal to the selected device to be monitored; (Electrical input device 18 is used to apply a voltage to a terminal, such as the gate in an FET or the base in a BJT, of the device under test 14 to activate the device for testing. Electrical input device 18 is typically implemented as a digital-to-analog converter (DAC) and may be configured as a passive DAC such as a resistor ladder network referenced to the on-chip supply voltage to eliminate the need for an additional pin on the IC. [0021].
Meninger et al. does not teach generate output digital data based on a second signal generated by the device to be monitored.
Jan et al. teach generate output digital data based on a second signal generated by the device to be monitored. (The high-speed ADC 110 converts the analog response signal 112 from the MTJ DUT 5 to a digitized response signal that is transferred to the stimulus/response controller 100. Par. [0062])
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al.to include the teaching of generate output digital data based on a second signal generated by the device to be monitored to provide a digital signal to be further processed by a digital input device.
Regarding claims 2 and 15, Meninger et al. teach wherein the plurality of devices comprise at least one of an n-channel metal-oxide-semiconductor (NMOS) transistor, a p-channel metal- oxide-semiconductor (PMOS) transistor, or a resistor. (The devices to be tested may be any kind of semiconductor devices, such as field effect transistors, bipolar junction transistors, diodes, and/or resistors, as well as the different varieties of such devices like MOSFETs, JFETs, n-doped and p-doped FETs, and devices with different physical parameters, such as different gate lengths and widths. Par. [0019]
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Kim et al. (US 20170146598).
Meninger et al. as modified teach the instant invention except the following.
Regarding claim 3, Meninger et al. does not teach wherein the plurality of devices are arranged in an array form, and wherein the selection circuit comprises a first multiplexer configured to select one or more rows of the array and a second multiplexer configured to select one or more columns of the array.
Jan et al. teach wherein the plurality of devices are arranged in an array form, (In other embodiments that accomplish at least one of these objects, the magnetic electrical test apparatus is configured for testing an array MTJ DUT's. ) [par. 0031] and
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Meninger et al. to include plurality of devices are arranged in an array form to provide similar devices for testing on the same substrate in oppose to separate substrates.
Meninger et al. teach the selection circuit (see rejection of claim 1 above)
Kim et al. teach wherein the selection circuit comprises a first multiplexer configured to select one or more rows of the array and a second multiplexer configured to select one or more columns of the array. (Each of the row signal selection unit 340 and the column signal selection unit 350 may include a plurality of multiplexers for selecting an input signal in response to the wafer-level test enable signal WTEST_EN enabled when a wafer-level test is performed.) [par. 0049]
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. and Jan et al. in view of Kim et al. to include wherein the selection circuit comprises a first multiplexer configured to select one or more rows of the array and a second multiplexer configured to select one or more columns of the array to select a specific device from a plurality devices present.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Potyrailo et al. (US 20140095102).
Meninger et al. teach the instant invention except the following claim limitations.
Regarding claim 7, Meninger et al. in view of Jan et al. does not teach wherein the second signal comprises a current signal, and wherein the output circuit further comprises a current-to-voltage converter configured to convert the second signal into a voltage signal.
Potyrailo et al. teach wherein the second signal comprises a current signal, and wherein the output circuit further comprises a current-to-voltage converter configured to convert the second signal into a voltage signal. (In the illustrated embodiment, the impedance reader comprises an impedance analyzer 64 having a voltage excitation generator containing a direct digital synthesizer (DDS) 66 and a voltage-mode digital to analog converter (DAC) 68, a receiver comprising a trans-impedance amplifier, also known as a current to voltage converter (CVC) 70, and analog to digital converter (ADC) 72; and optionally one or more filters 74. The DDS 66 generates the digital representation of the excitation carrier frequency which is converted by the DAC 68 to an analog voltage signal applied to the resonant sensor 62. The CVC converts the current flowing through the resonant sensor 62 into a voltage which is digitized by the analog to digital converter 72.) par. [0088]
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. and Jan et al. in view of Potyrailo et al. to include a current-to-voltage converter configured to: receive a second signal from the device to be monitored in response to the first signal, and convert the second signal into a voltage signal; and an output circuit comprising an analog-to-digital-converter configured to generate a digital output by converting the voltage signal into the digital output to provide the digital data to further digital processing devices for example a microprocessor.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Potyrailo et al. (US 20140095102) in view of Charles (US 20150091591).
Meninger et al. as modified the instant invention except the following.
Regarding claim 8, Meninger et al. as modified does not teach wherein the current-to-voltage converter further comprises a first variable resistor configured to amplify a magnitude of the voltage signal.
Charles teach wherein the current-to-voltage converter further comprises a first variable resistor configured to amplify a magnitude of the voltage signal. (converting the current into the voltage by passing the current through a variable resistor having a resistance, claim 16)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. and Jay et al. and Potyrailo et al. in view of Charles to include the current-to-voltage converter further comprising a first variable resistor configured to amplify a magnitude of the voltage signal to provide the ability to adjust voltage.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Potyrailo et al. (US 20140095102) in view of Charles (US 20150091591) in view of Van Dijk et al. (US 20150346241, here after Van)
Meninger et al. as modified teach the instant invention except the following.
Regarding claim 9, Meninger et al. as modified does not teach wherein the current-to-voltage converter further comprises a first comparator configured to output a variable resistance set signal based on the voltage signal and a first reference voltage as inputs.
Van teach wherein the current-to-voltage converter further comprises a first comparator configured to output a variable resistance set signal based on the voltage signal and a first reference voltage as inputs.( For example, the reference comparator 304 may be configured to compare the output voltage of the sensor component 302 to a reference voltage and provide feedback to the auto-range circuit 306. In one embodiment, the voltage may be 1.8 V. One of ordinary skill, however, will recognize other suitable reference voltages that may be used. The auto-range circuit 306 may then cause another sense resistor 216a-n in the sensor component 302 to be activated. For example, the auto-range circuit 306 may apply a voltage to a switch transistor 308a-n (Mrange1, . . . n) causing current to flow through the corresponding sense resistor 216a-n.) [par 0034]; (wherein the sense control circuit further comprises a comparator configured to trigger adjustment of the adjustable resistance component in response to an output voltage of the sensor component crossing a threshold set by a reference voltage.) (claim 5.)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. and Jan et al. and Potyrailo et al. and Charles in view of Van to include a first comparator configured to output a variable resistance set signal based on the voltage signal and a first reference voltage as inputs to adjust resistance component in response to an output voltage of the sensor component crossing a threshold set by a reference voltage. Claim 5)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Potyrailo et al. (US 20140095102) further in view of Wang (US 20040251947).
Meninger et al. teach the instant invention except the following claim limitations.
Regarding claim 10, Meninger et al. does not teach a gain amplification circuit configured to amplify the voltage signal, wherein the gain amplification circuit further comprises a second comparator and a second variable resistor configured to set the voltage signal as a second reference voltage.
Wang teach a gain amplification circuit configured to amplify the voltage signal, wherein the gain amplification circuit further comprises a second comparator (33, par. 0015) and a second variable resistor (30, par. 0015) configured to set the voltage signal as a second reference voltage. (Note par. 0015)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. to include the teaching of a gain amplification circuit configured to amplify the voltage signal, wherein the gain amplification circuit further comprises a second comparator and a second variable resistor configured to set the voltage signal as a second reference voltage to provide offset cancellation. (Note Wang abstract)
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Mori et al. (JP 2020064965).
Meninger et al. teach the instant invention except:
Regarding claim 13, Meninger et al. as modified does not teach a sub-monitoring circuit comprising a ring oscillator configured to monitor frequency performance of the plurality of devices.
Meninger et al. in view of Jan et al. teach plurality devices above. (See rejection of claim 1)
Mori et al. teach a sub-monitoring circuit comprising a ring oscillator configured to monitor frequency performance of the plurality of devices.( Measuring the oscillation frequency of the oscillator circuit when the measuring transistor is in the ON state; Based on the measured oscillation frequency, detecting the presence or absence of a difference between the threshold voltage of the measurement transistor and the ideal value of the threshold voltage,)(Under “(15)”, second to third paragraph)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. and Jan et al. in view of Mori et al. to include a sub-monitoring circuit comprising a ring oscillator configured to monitor frequency performance of the plurality of devices to detecting the presence or absence of a difference between the threshold voltage of the measurement transistor and the ideal value of the threshold voltage . (Mori et al. ,Under “(15)”, second to third paragraph)
Claims 12, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) further in view of Yang et al. (US 20120158338).
Regarding claims 12, 19 and 20 Meninger et al. does not teach a control circuit configured to: store monitoring result data of the plurality of devices, based on the output digital data; and compensate for a supply voltage or a supply frequency, based on the monitoring result data.
Yang et al. teach a control circuit (1000, Fig. 1) configured to: store monitoring result data of the plurality of devices, based on the output digital data; and compensate for a supply voltage or a supply frequency, based on the monitoring result data. (Note abstract)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. to include the teaching of a control circuit configured to: store monitoring result data of the plurality of devices, based on the output digital data; and compensate for a supply voltage or a supply frequency, based on the monitoring result data to increase the accuracy of the data.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Kim et al. (US 20170146598) in view of Zhang et al. (CN 110691445 A1).
Meninger et al. teach the instant invention except the following claim limitations.
Regarding claim 4, Meninger et al. does not teach the selection circuit further comprises a feedback amplifier configured to compensate for noise of a voltage signal, the feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting one of the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to each of the plurality of devices in parallel.
Zhang et al. teach the selection circuit further comprises a feedback amplifier (W1, Fig. 3) configured to compensate for noise of a voltage signal,(110, Fig. 4) the feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting one of the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to each of the plurality of devices in parallel. (Note that the all elements in Fig. 3 are connected to each other including the input and output terminals. Note M1 is in parallel with M1, M2, M3 are in parallel with M4, M5 and M6, Fig. 3)
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Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. to include the teaching of selection circuit further comprises a feedback amplifier configured to compensate for noise of a voltage signal, the feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting one of the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to each of the plurality of devices in parallel to compensate for any errors that may be present.
Regarding claim 5, Meninger et al. does not teach wherein the plurality of devices comprise transistors, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to drain terminals of the transistors in parallel.
Zhang et al. teach wherein the plurality of devices comprise transistors, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to drain terminals of the transistors in parallel. (Note W1 and M1-M6 and all the elements in Fig. 3 are connected to each other and the transistors M1-M3 and in parallel to M4-M6)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. to include the teaching of wherein the plurality of devices comprise transistors, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to drain terminals of the transistors in parallel to remove any unwanted elements in the signal.
Regarding claim 6, Meninger et al. does not teach the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to drain terminals of transistors in parallel.
Zhang et al. teach the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to drain terminals of transistors in parallel. (Note W1 and M1-M6 and all the elements in Fig. 3 are connected to each other and the transistors M1-M3 and in parallel to M4-M6)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. to include the teaching of the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to drain terminals of transistors in parallel to remove any unwanted elements in the signal.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Zhang et al. (CN 110691445 A1).
Meninger et al. teach the instant invention except the following claim limitations.
Regarding claim 16, Melinger et al. does not teach amplifying the second signal by using a feedback amplifier configured to compensate for noise of a voltage signal, the feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting one of the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to each of the plurality of devices in parallel.
Zhang et al. teach amplifying the second signal by using a feedback amplifier (W1, Fig. 3) configured to compensate for noise of a voltage signal, the feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting one of the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to each of the plurality of devices in parallel. (Note all elements are connected to each other, Fig. 3 below)
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Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Melinger et al. to include the teaching of amplifying the second signal by using a feedback amplifier configured to compensate for noise of a voltage signal, the feedback amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the feedback amplifier is configured to receive a select signal for selecting one of the plurality of devices, and wherein the second input terminal of the feedback amplifier and the output terminal of the feedback amplifier are connected to each of the plurality of devices in parallel to remove any unwanted elements impacting the signal.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) further in view of Yoon et al. (US 20150233996)
Meninger et al. teach the instant invention except the following claim limitations.
Regarding claim 17, Meninger et al. does not teach wherein the second signal comprises a current signal, and wherein the generating of the output digital data further comprises converting the second signal into a voltage signal.
Yoon et al. teach wherein the second signal comprises a current signal, and wherein the generating of the output digital data further comprises converting the second signal into a voltage signal. (Note par. 0044, A leakage current measurement circuit in accordance with principles of inventive concepts may include a mirror circuit configured to mirror leakage current to a current-to-voltage converter (which may be a resistor), and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value.)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. to include the teaching of teach wherein the second signal comprises a current signal, and wherein the generating of the output digital data further comprises converting the second signal into a voltage signal to provide a digital representation of the measured leakage current. (Note Meninger et al. par. 0047)
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) further in view of Yoon et al. (US 20150233996) further in Jung et al. (US 20210184478)
Meninger et al. teach the instant invention except the following claim limitations,
Regarding claim 18m Meninger et al. does not teach wherein the generating of the output digital data further comprises setting the voltage signal as a first reference voltage, and the first reference voltage is a maximum voltage level based on characteristics of the selected device to be monitored.
Jung et al. teach wherein the generating of the output digital data further comprises setting the voltage signal as a first reference voltage, and the first reference voltage is a maximum voltage level based on characteristics of the selected device to be monitored. (par. 0071, The controller 200 may convert a voltage value into a digital signal. For example, the controller 200 may utilize an analog-to-digital converter (ADC), and when the input voltage is alternating current, may convert it into direct current to set a reference voltage.)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify to include the teaching of the generating of the output digital data further comprises setting the voltage signal as a first reference voltage, and the first reference voltage is a maximum voltage level based on characteristics of the selected device to be monitored to control the charge breaker, (Note Jung et al. par. 0058)
Claims 11 are rejected under 35 U.S.C. 103 as being unpatentable over Meninger et al. (US 20160139180) in view of Jan et al. (US 20190257881) in view of Potyrailo et al. (US 20140095102) further in view of Liu et al. (US 20080298113).
Meninger et al. teach the instant invention except the following claim limitations.
Regarding claim 11, Meninger et al. does not teach wherein the selection circuit further comprises a leakage current prevention circuit on a path of an unselected device, and wherein the leakage current prevention circuit transfers a voltage level at one end of a selected device, which is connected to the selection circuit, to one end of a unselected device, which is connected to the selection circuit.
Liu et al. teach wherein the selection circuit (450, Fig. 4a, par. 0032) further comprises a leakage current prevention circuit (660, Fig. 4a, par. 0031) on a path of an unselected device, and wherein the leakage current prevention circuit transfers a voltage level at one end of a selected device (320 a), which is connected to the selection circuit, to one end of a unselected device, (10a, Fig. 41, par. 0032) which is connected to the selection circuit. (Note par. 0032, memory cell 10 c which suggested that the voltage passes through 10a and 10c,of Fig. 4A)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Meninger et al. to include the teaching of wherein the selection circuit further comprises a leakage current prevention circuit on a path of an unselected device, and wherein the leakage current prevention circuit transfers a voltage level at one end of a selected device, which is connected to the selection circuit, to one end of a unselected device, which is connected to the selection circuit to prevent parallel leak current from flowing through non-selected memory cells. (Note Liu et al. abstract)
Conclusion
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/DEMETRIUS R PRETLOW/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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