DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-27 are presented for examination.
Priority
Acknowledgement is made of applicant's claim for domestic priority under 35 U.S.C. § 120, through utility U.S. Application No. 18/227,545, filed July 28, 2023, which claims priority from United States Provisional Application for Patent No. 63/402,182, filed August 30, 2022.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is objected to because:
The Cross-Reference to Related Applications section in paragraph [0001] of the specification does not provide the status of U.S. application serial no. 18/227,545 (i.e., now U.S. Patent No. 12,170,120).
Drawings
The formal drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-27 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 12,170,120.
For example, claim 1 of the present application a memory circuit, comprising: a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column; a word line drive circuit for each row having an output connected to drive the word line of the row; a row decoder circuit configured to support two modes of memory circuit operation including: a first mode where the row decoder circuit actuates only one word line in the memory array during a memory read and a second mode where the row decoder circuit simultaneously actuates one word line per sub-array during the memory read; and an input/output circuit for each column comprising: a plurality of bit line inputs coupled to the local bit lines of the sub-arrays; a column data output coupled to the plurality of bit line inputs; and a plurality of sub-array data outputs, where each sub-array data output is coupled to a corresponding bit line input. Whereas claim 1 of U.S. PN. 12,170,120 teaches a memory circuit, comprising: a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column; a word line drive circuit for each row having an output connected to drive the word line of the row; a row decoder circuit configured to support two modes of memory circuit operation including: a first mode where the row decoder circuit actuates only one word line in the memory array during a memory read and a second mode where the row decoder circuit simultaneously actuates one word line per sub-array during the memory read; and an input/output circuit for each column comprising: a plurality of bit line inputs coupled to the local bit lines of the sub-arrays; a column data output coupled to the plurality of bit line inputs; and a plurality of sub-array data outputs, where each sub-array data output is coupled to a corresponding bit line input; wherein the input/output circuit for each column further comprises a logic gate having a first input coupled to the local bitline, a second input coupled to receive automated test pattern generated (ATPG) test pattern data, and an output coupled to the column data output and coupled to the sub-array data output.
Rationales:
Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant applicant's claim 1 broadens the scope of claim 1 of the U.S. Patent No. 12,170,120 by eliminating several imitations such as “wherein the input/output circuit for each column further comprises a logic gate having a first input coupled to the local bitline, a second input coupled to receive automated test pattern generated (ATPG) test pattern data, and an output coupled to the column data output and coupled to the sub-array data output”. It is obvious the limitations of claim 1 of U.S. Patent No. 12,170,120 read on the limitations of claim 1 of the instant application Thus, the claims are obvious variations of each other and not patentably distinct. Further, it has been held that the omission of an element and its function is an obvious expedient if the remaining elements perform the same functions as before. See /n re Karlson, 136 USPQ 184(CCPA 1963). Also note Ex parte Rainu, 168 USPQ 375 (BdPat App&int 1970); omission of a reference element whose function is not needed would be obvious to one skilled in the art.
"A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Comparing the dependent claims of the instant application with the dependent claims of U.S. Patent No. 12,170,120 have corresponding issues as indicated below and they are also rejected under non-statutory obviousness-type double patenting.
Instant application No.18/227,545 U.S. PN: 12,170,120
Claim 2 Claim 2
Claim 3 Claim 3
Claim 4 Claim 5
Claim 5 along with claim 1 Claim 7
Claim 6 Claim 8
Claim 7 Claim 9
Claim 8 Claim 10
Claim 9 Claim 11
Claim 10 along with claim 1 Claim 7
Claim 11 Claim 8
Claim 12 Claim 9
Claim 13 Claim 10
Claim 14 Claim 11
Claim 15 Claim 7
Claim 16 Claim 8
Claim 17 Claim 5
Claim 18 Claim 11
Claim 19 Claim 11
Claim 20 along with claim 1 Claim 7
Claim 21 Claim 8
Claim 22 Claim 11
Claim 23 along with claim 1 Claim 7
Claim 24 Claim 8
Claim 25 Claim 11
Claim 26 Claim 1
Claim 27 Claim 6
Allowable Subject Matter
The Examiner would like to point out that a properly executed Terminal Disclaimer will overcome the rejection and thereafter the claims can be in condition for allowance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. US-11501846 describe a memory core includes a memory cell array that stores data, and a data input/output circuit connected to a data input/output pad. The BIST circuit is connected to a test pad that is disposed separate from the data input/output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data to the memory cell array through the data input/output circuit.
Schreiber et al. US-11264115 teach an integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode.
Jung et al. US-7607055 describe a built- in- self test (BIST) circuit for a semiconductor memory device including an output buffer, a pattern generator configured to generate a test pattern, a mode selector configured to select the test pattern and provide the test pattern to the output buffer, and a comparator configured to compare the test pattern with a received test pattern.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112