DETAILED ACTION
This action is responsive to the following communications: the Application filed November 07, 2024.
Claims 1-20 are pending. Claim 1 and claim 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Regarding Fig. 1a and Fig. 1b, new corrected drawings in compliance with 37 CFR 1.121(d) are required in this application. Fig. 1a and Fig. 1b should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled "Replacement Sheet" in the page header (as per 37 CFR 1.84(c) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Furthermore, Fig. 1a is objected to as failing to comply with 37 CFR 1.84(p)(5) because it includes reference numeral 114a, which is not described in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Fig. 2a is incorrectly referred to as Fig. 2 in the specification. Moreover, Fig. 2a appears to depict bitcell array 210a as being on the same layer as bitcell array 210b. This is inconsistent with the disclosure at page 9, lines 14-21 of the specification, which states that: “In contrast to the conventional storage circuitry (e.g. as depicted in Figure 1a), where the bitcell arrays and associated redundant arrays are arranged in the same metal or poly layer, in accordance with the present techniques the bitcell arrays 210a/b and associated redundant arrays 212a/b are provided [fabricated] in different layers (e.g. polysilicon or metal layers) of the storage circuit 200. Thus, the bitcells of the bitcell arrays 210a/b and the redundant bitcells of the associated redundant arrays 212a/b are provided in different layers to one another.” Thus, the disclosure lacks clarity regarding whether bitcell arrays 210a and 210b are arranged on the same layer. MPEP § 2173.02, Section 2 (Threshold Requirements of Clarity and Precision) states that “The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity." The section further explains that “As the statutory language of ‘particular[ity]' and 'distinct[ness]' indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not. Packard, 751 F.3d at 1313, 110 USPQ2d at 1788. Definiteness of claim language must be analyzed, not in a vacuum, but in light of: (A) The content of the particular application disclosure.” Furthermore, Fig. 2a includes reference numerals 215a-215b labeled as “WL MSB”, which is inconsistent with “rWL MSB” as disclosed in the specification.
In addition, Fig. 2a is objected to under 37 CFR 1.84(p)(5) because it includes reference numerals 204, 214a-214c, 217a-217b, which are not described in the specification. Please refer to paragraph 2 of this section for suggested corrections.
Regarding Fig. 3a and Fig. 4, they are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include reference numeral 222, which is not disclosed in the specification. Please refer to paragraph 2 of this section for suggested corrections.
Regarding Fig. 3b, Fig. 6a, Fig. 6b, corrected drawings compliant with 37 CFR 1.121(d) are required, as the reference numerals and text are not legible. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Regarding Fig. 8, it is objected to under 37 CFR 1.84(p)(5) because it includes reference numerals 520, 540, 550, which are not described in the specification. Please refer to paragraph 2 of this section for suggested corrections.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specific to independent claim 1 (and as inherited through all dependent claims 2-18 and 20), Claim 1 is not consistent with the specification because it recites that “the bitcell array is provided at a first layer of the storage circuitry” and further recites that the “bitcell array is provided at a second layer of the storage circuitry”, which suggests that the same bitcell array is located in both layers. See MPEP 2173.03.
The Specification at page 9, lines 14-21 states “In contrast to the conventional storage circuitry (e.g. as depicted in Figure 1a), where the bitcell arrays and associated redundant arrays are arranged in the same metal or poly layer, in accordance with the present techniques the bitcell arrays 210a/b and associated redundant arrays 212a/b are provided [fabricated] in different layers (e.g. polysilicon or metal layers) of the storage circuit 200. Thus, the bitcells of the bitcell arrays 210a/b and the redundant bitcells of the associated redundant arrays 212a/b are provided in different layers to one another”. The Specification, thus, appears to indicate the invention requires the bitcell array to be in one layer and the redundant array being in another layer.
However, claim 1 recites the bitcell array is in the both “first layer” and the “second layer.” The redundant array is not claimed to be in any particular layer. This creates uncertainty as to whether the same bitcell array is in both layers or whether different bitcell arrays are intended or whether claim 1’s recitation in the last clause (i.e., “the bitcell array is provided at a second layer”) was instead intended to recite the redundant array is in the second layer. Thus, the scope of claim 1 is unclear. See MPEP § 2173.03, Correspondence Between Specification and Claims (claim may be indefinite when inconsistencies between the claim and specification make the scope uncertain).
For purposes of compact prosecution (MPEP 2173.06), claim 1 is treated as though it recites “the redundant array is provided at the second layer of the storage circuit.”
Claim 2 is indefinite because the claim recites “first layer” and “second layer” which are indefinite for the reasons stated above in claim 1. In addition, the phrase “second or third layer of the storage circuitry” is ambiguous because it is unclear whether the second bitline portion is located at the second layer, the third layer, or both, and the scope of “third layer” is unclear.
Claims 3 (and claims 13-18, which inherit the defect of claim 3), 4 (and claim 5, which inherits the defect of claim 4), and 6 are indefinite because the term “floating bitline” is undefined.
MPEP 2173.02(II) instructs examiners to determine definiteness, not in a vacuum, but in light of the following: (A) The content of the particular application disclosure; (B) The teachings of the prior art; and (C) The claim interpretation that would be given by one possessing the ordinary level of skill in the pertinent art at the time the invention was made.
The term “floating” is used in applicant’s originally filed Specification at 24 locations, but none of these locations provide a definition or indication of what structure or property is required for the “bitline” to be considered “floating.” It appears, based upon the context, “floating bitline” does not refer to the act of placing the bitline into a floating state. Specific to the claim language “floating bitline,” in Specification, page 9, line 26 or Specification, page 10, lines 30-32, applicant refers to FBL as being a “flexible or floating bitline.” The term “flexible,” according to Merriam-Webster.com, means “capable of being flexed,” “yielding to influence,” or “characterized by a ready capability to adapt to new, different, or changing requirements.” None of these definitions appear applicable to applicant’s use of “flexible” as an adjective for a “bitline” because the bitline is not capable of being flexed, does not yield to influence, or would not be characterizable as having capability to adapt to new, different or changing circumstances. The term “floating” as an adjective for a conductive line, like a bitline, also does not provide clear distinction as to what structure, properties, or characteristics the claimed bitline must have to be deemed “floating.” The remaining locations in the originally filed Specification do not provide clarity as to what a “floating bitline” is and how it is different from a bitline, or any conductive line connected to the bitline.
Claims 4 (and dependent claim 5, which inherits the defect of claim 4), and 6 are indefinite because the term “floating bitline cell” is also not clearly defined.
MPEP 2173.02(II) instructs examiners to determine definiteness, not in a vacuum, but in light of the following: (A) The content of the particular application disclosure; (B) The teachings of the prior art; and (C) The claim interpretation that would be given by one possessing the ordinary level of skill in the pertinent art at the time the invention was made.
Just like the term “floating bitline,” “floating bitline cell” does not appear to involve the act of placing a bitline cell into a “floating state.” The term “floating bitline cell” does not have a recognized definition and does not appear to be a term of art. The originally filed Specification, at page 14, lines 13-19 states:
In FIGS. and 3a & 3b and in the following illustrative examples the transition region 230a/b to electrically couple the respective bitline portions is described as an FBL cell 230a located between the redundant array and the bitcell array. In the present illustrative example of FIG. 3b, the transition region 230a comprises a FBL cell 230a. Depending on the technology, the FBL cell 230 may comprise, for example, a two or four contacted poly pitch (4Cpp), and an example of the transition region comprising an FBL cell is shown in FIG. 3b below.
In other words, this portion of the Specification suggests that Figure 3A, transition region 230A is “described as” a “floating bitline cell” or “comprises” a “floating bitline cell.” Figure 3A illustrates region 230A as an empty box, with no further detail as to what is included. In other words, Figure 3A does not provide clarity to aid in understanding the meaning of the term “floating bitline cell.”
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Figure 3b has marking that state FBL_cell, but the Figure on the record is illegible. As such, the term “floating bitline cell” is indeterminate.
Claim 5 (and claim 6 which inherits claim 5’s defect) is indefinite because of lack of antecedent basis for “the first bitline portion” and “the second bitline portion.”
Claims 5-6 are indefinite because the term “transition region” is not clearly defined.
Claim 19 is indefinite because although claim 19 is presented as a method claim, the claim merely recites structural components of storage circuitry, and does not recite any method steps or operations performed by the claimed method. Thus, it is unclear what steps constitute the claimed method.
Claim 20 is rejected under 35 U.S.C. 112(b) as indefinite. The claim recites a non-transitory computer-readable medium storing computer readable code “for fabrication” of storage circuitry of claim 1. However, it does not identify the fabrication operations performed by the code nor does it define the scope of the claimed fabrication process. At most, this claim appears to find support in Figure 8, but Figure 8 is described as a “flow diagram” where each step is an “operation [] to fabricate circuitry” followed by the circuitry, as disclosed in the specification at pages 22 and 23, without further details as to any specific fabrication process or fabrication machinery or any actual fabrication code or algorithm.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-14, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Merritt (US 5706292) in view of Gomes et al. (US 11257822 B2; hereinafter “Gomes”).
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Regarding independent claim 1 and independent method claim 19 (which only differs from claim 1 in that it requires “controlling a read or write operation”; see Merrritt col. 6, ll. 37-41), Merritt discloses, consistent with the 112(b) definitenessrejection supra, a storage circuitry (Fig. 3) comprising:
a bitcell array (Fig. 3: e.g., 231) having a plurality of bitcells, each bitcell accessible via at least one bitline and at least one wordline (not shown but the memory 230 being an “array” means it is organized in columns, i.e., bitlines, and rows, i.e., word lines), where the bitcell array is provided at a “first layer” (i.e., a layer within plane A, as explained in column 8, line 47, which is formed on a substrate as apparent from column 5, lines 1-5) of the storage circuitry;
a redundant array (Fig. 3: e.g., 107, 108) associated with the bitcell array (Fig. 3: 231), the redundant array having a plurality of redundant bitcells (see column 9, lines 30-31: “row of redundant memory cells in redundant row 107), each redundant bitcell accessed via at least one redundant bitline and at least one redundant wordline (not shown but the redundant row of memory cells 107 is accessible by at least one redundant row access line, i.e., word line, and each memory cell in that row is accessible by its column, i.e., bitline), where the redundant array is provided at a “second layer” (i.e., the redundant row 107 is in an another “layer” of plane A, which is formed on a substrate as apparent from col. 5, ll. 1-5) of the storage circuitry.
However, assuming claim 1 was actually intended to recite the bitcell array is provided at a second layer of the storage circuit, Merritt is silent with respect to “the bitcell array is provided at a second layer of the storage circuitry.”
Gomes teaches the memory array is formed in multiple layers on top of each other (see Examiner’s Markup Gomes Fig. 4B). Thus, Gomes teaches the bitcell array is provided at a second layer of the storage circuitry, as claimed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Gomes with the teachings of Merritt such that layered memory architecture taught by Gomes is utilized with the storage device having the redundancy circuitry taught by Merritt, in order to improve defect tolerance and memory reliability in layered memory circuitry as well as to increase density of memory cells by utilizing stacked layers of memory cells (see Gomes col. 2, ll. 39-42 and 51-53).
Regarding claim 2, Merritt and Gomes, as combined, teach the limitations of claim 1.
Merritt shows “column selection circuitry” (Fig. 3: 112) to, responsive to a column select signal (col. 4., ll. 9-12: external address word), select at least one bitcell via the least one bitline (see col. 4, ll. 9-12: “the plurality of primary circuit elements [or i.e., memory cells] are addressable by electrically conductive row and column lines based on an external address word having a predetermined length”).
Gomes, as combined with Merritt, shows the at least one bitline comprises a first bitline portion (see Fig. 4B: 440) provided at the first layer of the storage circuitry (Fig. 4B: 440 has a “portion” in the uppermost memory layer) and a second bitline portion (see Fig. 4B: 440) provided at the second or third layer of the storage circuitry (Fig. 4B: 440 also has a “portion” in the other memory layers), and where the first bitline portion is in electrical communication with the second bitline portion (Fig. 4B: 440).
Regarding claim 3, Merritt and Gomes, as combined, teach the limitations of claim 1.
Merritt teaches “column selection circuitry” by column decoders (Fig. 3: 112) responsive to a redundant column select signal. The Specification explains that the column selection circuitry 208a/208b provides an appropriate signal via flexible or floating bitlines (fBLn/fnBLn) and further explains that the floating bitlines extend in the same layer as the bitcells (Specification, p. 10, ll. 27-32). This description suggests that the floating bitline functions as a bitline extension coupling the redundant array to the column selection circuitry. Thus, the claimed selection of a redundant bitcell via at least one floating bitline is taught by the connection between redundant memory cells (Fig. 3: e.g., 107, 108) and column decoders (Fig. 3: 112) in Merritt.
Regarding claim 7, Merritt and Gomes, as combined, teach the limitations of claim 1.
Merritt teaches “wordline selection circuitry” (Fig. 3: 111) to generate “a wordline signal” to select at least one bitcell (as a row decoder would be expected to function under normal operation).
Regarding claim 8, Merritt and Gomes, as combined, teach the limitations of claim 1.
Merritt also teaches “redundant row wordline selection circuitry” (Fig. 3: also within 111; but also see Fig. 3: 120 which is involved circuitry) to generate a redundant wordline signal to select at least one redundant bitcell (see col. 9, ll. 19-31).
Regarding claim 9, Merritt and Gomes, as combined, teach the limitations of claim 8.
Merritt further teaches the redundant row wordline selection circuitry (Fig. 3: 111, 120) is configured to receive a faulty row address (see col. 9, ll. 19-24: one of the addresses stored in the fuse banks) and a main address (see col. 9, ll. 19-24: the address received from the control logic and address buffer circuitry), and determine whether there is a match between the faulty row address and the main address (see col. 9, ll. 19-24: if the address received from the control logic and address buffer circuitry, i.e., main address, matches one of the addresses stored in the fuse banks, i.e., faulty address, then the compare circuit outputs a match signal M, and during a row access mode, the row decoder receives the match signal M and uses it to enable the appropriate redundant row).
Regarding claim 10, Merritt and Gomes, as combined, teach the limitations of claim 9.
Merritt further teaches the redundant row wordline selection circuitry (Fig. 3: 111, 120) is to generate “a match signal” (Fig. 3: M) responsive to a match between the faulty row address and the main address (see col. 9, ll. 19-24: if the address received from the control logic and address buffer circuitry, i.e., main address, matches one of the addresses stored in the fuse banks, i.e., faulty address, then the compare circuit outputs a match signal M, and during a row access mode, the row decoder receives the match signal M and uses it to enable the appropriate redundant row).
Regarding claim 11, Merritt and Gomes, as combined, teach the limitations of claim 10.
Merritt further teaches the redundant row wordline selection circuitry (Fig. 3: 111, 120) is to generate the match signal (Fig. 3: M) responsive to a match between the faulty row address and the main address (see col. 9, ll. 19-24: if the address received from the control logic and address buffer circuitry, i.e., main address, matches one of the addresses stored in the fuse banks, i.e., faulty address, then the compare circuit outputs a match signal M, and during a row access mode, the row decoder receives the match signal M and uses it to enable the appropriate redundant row) when a row redundancy enable signal is asserted (see Fig. 3: RA9 and ECOLF, where, as explained in col. 9, ll. 16-18 that RA9 is used to select the fuse banks and as explained in col. 11, ll. 50-52, RAS asserted at active low with ECOLF at low will result in row address latching at the MUX, meaning the match signal M for the redundant row will not occur unless RAS and ECOLF are in states for row selection).
Regarding claim 12, Merritt and Gomes, as combined, teach the limitations of claim 9.
Merritt further teaches the redundant row wordline selection circuitry (Fig. 3: 111, 120) comprises redundant wordline driver circuitry (Fig. 3: 111 for 107) to generate the redundant wordline signal (e.g., col. 9, ll. 25-31) responsive to the match signal (Fig. 3: M) and a clock path signal (see col. 11, ll. 45-52, explaining reliance upon RAS).
Regarding claim 13, Merritt and Gomes, as combined, teach the limitations of claim 3.
Claim 13 further requires a column write device arranged between the second bitline portion and write driver circuitry to enable the write driver circuitry to store a data value at one or more accessed bitcells. Merritt teaches column selection circuitry by column decoders (Fig. 3: 112) for selecting a column, including a redundant memory column (Fig. 3: e.g., 107, 108), for a write operation.
Regarding claim 14, Merritt and Gomes, as combined, teach the limitations of claim 3.
Claim 14 further requires one or more redundant column write devices arranged between the redundant bitline and write driver circuitry to enable the write driver circuitry to store a data value at one or more accessed redundant bitcells. Merritt teaches redundant memory columns (Fig. 3: e.g., 107, 108) selectively accessed through column decoder (Fig. 3: 112) for writing data to a selected redundant memory column.
Regarding claim 16, Merritt and Gomes, as combined, teach the limitations of claim 3.
Claim 16 further requires a column read device arranged between the second bitline portion and sense amplifier circuitry. Merritt teaches column selection circuitry by column decoders (Fig. 3: 112) for selecting a memory column, including a redundant memory column (Fig. 3: e.g., 107, 108), during a read operation.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Merritt (US 5706292) in view of Gomes et al. (US 11257822 B2; hereinafter “Gomes”) and further in view of Fujiwara et al. (US 11088151 B2; hereinafter “Fujiwara”).
Regarding claim 4, Merritt and Gomes, as combined, teach the limitations of claim 1.
Claim 4 further requires a floating bitline cell provided between the bitcell array and the associated redundant array. The specification explains that, “depending on the technology, the FBL cell 230 may comprise, for example, a two or four contacted poly pitch (4Cpp)” (p. 14, ll. 17-23). Fujiwara teaches SRAM bitcells implemented using a four-contact polysilicon pitch (4Cpp) (US 11088151, p. 20, col. 14, ll. 47-59).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the known 4Cpp architecture taught by Fujiwara in implementing the claimed FBL cell.
Regarding claim 5, Merritt, Gomes, and Fujiwara, as combined, teach the limitations of claim 4.
Claim 5 further requires that the first bitline portion in electrical communication with the second bitline portion at a transition region. Gomes teaches bitline structures extending through multiple memory layers of the memory device and electrically coupled to provide a continuous signal path (Fig. 4B), thereby providing electrical communication between the first bitline portion and the second bitline portion.
Regarding claim 6, Merritt, Gomes, and Fujiwara, as combined, teach the limitations of claim 5.
Claim 6 further requires that the transition region comprises a floating bitline (FBL) cell. The specification further explains that the FBL cell may comprise, for example, a two or four-contacted poly pitch (2Cpp/4Cpp) cell (p. 14, ll. 17-23). Fujiwara teaches SRAM bitcells implemented using a four-contacted poly pitch (4Cpp) architecture (US 11088151, p. 20, col. 14, ll. 47-59).
Claims 15, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Merritt (US 5706292) in view of Gomes et al. (US 11257822 B2; hereinafter “Gomes”) and further in view of Park et al. (US 20090303819 A1; hereinafter “Park”).
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Regarding claim 15, Merritt and Gomes, as combined, teach the limitations of claim 14.
Claim 15 further requires a pass-gate to provide a word data signal to the one or more accessed bitcells. The Specification describes redundant column write (RCW) as passgates 232/234 comprising pairs of NMOS transistors that are arranged in parallel (Specification, p. 12, ll. 17-19, and p. 15, ll. 27-28). Park teaches transmission gates (Fig. 2: e.g., 220, 224) that couple write driver (Fig. 2: 160) to bitlines (Fig. 2: e.g., 120, 120’) when a column is selected (US 20090303819 A1, p. 3, para. 44, p. 4, para. 50). Thus, Park teaches the claimed passgates.
Regarding claim 17, Merritt and Gomes, as combined, teach the limitations of claim 16.
Claim 17 further requires a pass-gate to enable the sense amplifier circuitry to sense a data value stored at one or more accessed bitcells. The Specification describes column read (CR) as passgates comprising pairs of PMOS transistors that are arranged in parallel and coupled between the corresponding bitlines (BLn/nBLn) and sensed data lines (SDn/nSDn) which are coupled to sense amplifier (SA) circuitry (Specification, p. 13, ll. 12-15). Park teaches transmission gates (Fig. 2: 220, 224) that couple sense amplifier (Fig. 2: 160) to bitlines (Fig. 2: 120, 120’) when a column is selected for a read operation (US 20090303819 A1, p. 3, para. 44, p. 4, para. 54). Thus, Park teaches the claimed passgates.
Regarding claim 18, Merritt and Gomes, as combined, teach the limitations of claim 3.
Claim 18 further requires a common pass-gate to select one or more columns of redundant bitcells. The Specification describes redundant column write (RCW) devices as comprising pairs of NMOS transistors (Specification, p. 12, ll. 17-19), and redundant column read (RCR) devices as comprising pairs of PMOS transistors (Specification, p. 16, ll. 30-31), but does not define “common passgates”. Under the broadest reasonable interpretation, common passgates are passgates configured to selectively couple signals through a common access path. Park teaches transmission gates (Fig. 2: 220, 224) that selectively couple bitlines (Fig. 2: 120, 120’) to sense amplifier/write driver (Fig. 2: 160) when a column is selected (US 20090303819 A1, p. 3, para. 44, p. 4, para. 50, 54). Thus, Park teaches the claimed common passgates.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Merritt (US 5706292) in view of Gomes et al. (US 11257822 B2; hereinafter “Gomes”) and further in view of Katase et al. (US 20060214119 A1; hereinafter “Katase”).
Regarding claim 20, Merritt and Gomes, as combined, teach the limitations of claim 1.
However, Merritt and Gomes do not teach a non-transitory computer-readable medium storing computer-readable code for fabrication of the storage circuitry. Katase teaches a computer-readable medium recorded with a pattern data creation program (see US 20060214119 A1, p. 21, claim 8), wherein the program includes program code for generating and modifying pattern data used in semiconductor manufacturing. Katase further teaches a method of fabricating a semiconductor device using the generated pattern data and an exposure mask (see US 20060214119 A1, p. 20, claim claim 7). Therefore, the combination of Merritt, Gomes, and Katase teaches a non-transitory computer-readable medium storing computer-readable code for fabrication of the storage circuitry of claim 1.
Conclusion
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/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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