DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
[0040] line 2- delete the duplicated phrase “on one hand”
[0053] line 6- the punctuation after the word “process” should be corrected, a period followed by a comma is improper.
[0075] line 5- the phrase “it is indicates” is improper. This sentence should be rephrased to improve clarity.
Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: S121, S122, S1211, S1213. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 12-20 are rejected under 35 U.S.C. 101.
Claims 12-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 12 recites:
A method for data processing, comprising:
determining a first sub-block from a plurality of sub-blocks of an instruction block stored in an Instruction Cache (ICache) based on a fetch instruction;
determining first pre-decoding information of the first sub-block based on position information of the first sub-block in the instruction block, wherein the first pre-decoding information of the first sub-block is configured to indicate whether an instruction stored in the first sub-block is an instruction boundary; and
repairing second pre-decoding information of at least one target sub-block in the instruction block based on the first pre-decoding information of the first sub-block when second pre-decoding information of the first sub-block stored in the ICache is different from the first pre-decoding information of the first sub-block.
Examiner notes that since the claim is directed to a method, the contingent limitation “repairing… when second pre-decoding information of the first sub-block stored in the ICache is different…” is not required under BRI, see MPEP 2111.04(II).
The claim is directed to the abstract idea of a mental process (Step 2A Prong One, Yes) because a person can mentally perform the step of determining a first sub-block from a plurality of sub-blocks of an instruction block stored in an Instruction Cache (ICache) based on a fetch instruction, for example, by examining a fetch instruction address and determining that there is a sub-block at that address in an instruction cache. The claim is also directed to the abstract idea of a mental process because a person can mentally perform the step of determining first pre-decoding information of the first sub-block based on position information of the first sub-block in the instruction block, wherein the first pre-decoding information of the first sub-block is configured to indicate whether an instruction stored in the first sub-block is an instruction boundary, for example, by mentally determining the position of an instruction boundary in an instruction block layout. Since the only additional elements recited by the claim are contingent limitations not required under BRI of a method claim, the claim does not recite any additional elements that, alone or in combination, integrate the abstract idea into a practical application (Step 2A Prong Two, No). At Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, either alone or in combination. The analysis for Step 2B is the same as for Step 2A.
Claim 13 recites:
13. The method of claim 12, wherein determining the first pre-decoding information of the first sub-block based on position information of the first sub-block in the instruction block comprises at least one of:
determining the first pre-decoding information of the first sub-block based on a previous instruction block when the position information is configured to indicate that the first sub-block is a first one of the plurality of sub-blocks of the instruction block (this contingent limitation is not required under BRI of a method claim); or
taking first information as the first pre-decoding information of the first sub-block when the position information is configured to indicate that the first sub-block is not the first one of the plurality of sub-blocks of the instruction block, wherein the first information is configured to indicate that the instruction stored in the first sub-block is the instruction boundary (this “or” limitation is not required under BRI).
Since the BRI of claim 13 does not require any additional elements, it does not recite any additional elements that would integrate the judicial exception into a practical application or amount to significantly more than the judicial exception.
Claim 14 recites:
14. The method of claim 13, wherein determining the first pre-decoding information of the first sub-block based on the previous instruction block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises:
acquiring instruction information stored in a last one of sub-blocks of the previous instruction block;
taking second information as the first pre-decoding information of the first sub-block when the instruction information is configured to indicate that low-order bits of an instruction are stored in the last one of the sub-blocks, wherein the second information is configured to indicate that the instruction stored in the first sub-block is a non-instruction boundary; and
taking the first information as the first pre-decoding information of the first sub-block when the instruction information is configured to indicate that high-order bits of the instruction or all bits of the instruction are stored in the last one of the sub-blocks.
Since the BRI of claim 14 does not require any additional elements, it does not recite any additional elements that would integrate the judicial exception into a practical application or amount to significantly more than the judicial exception.
Claim 15 recites:
15. The method of claim 12, wherein the at least one target sub-block comprises the first sub-block,
wherein repairing the second pre-decoding information of the at least one target sub-block in the instruction block based on the first pre-decoding information of the first sub-block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises:
repairing the second pre-decoding information of the first sub-block based on the first pre-decoding information of the first sub-block;
when the at least one target sub-block comprises at least one second sub-block, for each second sub-block, determining first pre-decoding information of the second sub-block based on instruction information stored in a previous sub-block of the second sub-block, and repairing second pre-decoding information of the second sub-block based on the first pre-decoding information of the second sub-block; and
writing repaired second pre-decoding information of the at least one target sub-block back into the ICache.
Since the BRI of claim 15 does not require any additional elements, it does not recite any additional elements that would integrate the judicial exception into a practical application or amount to significantly more than the judicial exception.
Claim 16 recites:
16. The method of claim 15, wherein repairing the second pre-decoding information of the first sub-block based on the first pre-decoding information of the first sub-block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises:
updating the second pre-decoding information of the first sub-block to be the first pre-decoding information of the first sub-block.
Since the BRI of claim 16 does not require any additional elements, it does not recite any additional elements that would integrate the judicial exception into a practical application or amount to significantly more than the judicial exception.
Claim 17 recites:
17. The method of claim 15, wherein determining the first pre-decoding information of the second sub-block based on the instruction information stored in the previous sub-block of the second sub-block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises at least one of:
taking second information as the first pre-decoding information of the second sub-block when the instruction information is configured to indicate that low-order bits of an instruction are stored in the previous sub-block; or
taking first information as the first pre-decoding information of the second sub-block when the instruction information is configured to indicate that high-order bits of the instruction or all bits of the instruction are stored in the previous sub-block.
Since the BRI of claim 17 does not require any additional elements, it does not recite any additional elements that would integrate the judicial exception into a practical application or amount to significantly more than the judicial exception.
Claim 18 recites:
18. The method of claim 15, wherein repairing the second pre-decoding information of the second sub-block based on the first pre-decoding information of the second sub-block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises:
reading the second pre-decoding information of the second sub-block from the ICache;
updating the second pre-decoding information of the second sub-block to be the first pre-decoding information of the second sub-block when the second pre-decoding information of the second sub-block is different from the first pre-decoding information of the second sub-block; and
keeping the second pre-decoding information of the second sub-block unchanged when the second pre-decoding information of the second sub-block is the same as the first pre-decoding information of the second sub-block.
Since the BRI of claim 18 does not require any additional elements, it does not recite any additional elements that would integrate the judicial exception into a practical application or amount to significantly more than the judicial exception.
Claim 19 recites:
19. The method of claim 12, further comprising:
acquiring the instruction block from a memory;
determining respective second pre-decoding information of each sub-block of the plurality of sub-blocks; and
storing each sub-block of the plurality of sub-blocks and the respective second pre-decoding information of the sub-block into the ICache.
The step of determining respective second pre-decoding information of each sub-block of the plurality of sub-blocks is directed to the abstract idea of a mental process as a person can mentally perform this determination. The additional elements of acquiring the instruction block from a memory; and storing each sub-block of the plurality of sub-blocks and the respective second pre-decoding information of the sub-block into the ICache amount to retrieving and storing information in memory, which is insignificant extra solution activity and does not integrate the judicial exception into a practical application or amount to significantly more than the judicial exception.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of “a computer-readable storage medium” encompasses transitory forms of signal transmission, which is a non-statutory embodiment. This is further evidenced by [00209] of the specification, which discloses that “The computer-readable storage medium may be transitory or non-transitory.” Examiner suggests amending the claims to recite “A non-transitory computer-readable storage medium”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shang US 5,941,980.
Regarding claim 12, Shang teaches:
12. A method for data processing, comprising:
determining a first sub-block from a plurality of sub-blocks of an instruction block stored in an Instruction Cache (ICache) based on a fetch instruction (col 10 lines 1-19 discloses fetching/determining a sequence of data words/sub-blocks (including a first data word/sub-block) from a cache line/instruction block of instruction cache 30 based on a request (i.e., a fetch instruction) from the prefetcher; instruction cache 30 and boundary memory 20 are collectively an ICache);
determining first pre-decoding information of the first sub-block based on position information of the first sub-block in the instruction block, wherein the first pre-decoding information of the first sub-block is configured to indicate whether an instruction stored in the first sub-block is an instruction boundary (col 11 lines 5-23: the instruction length verifier (ILV) generates a vector of indicators, the indicator bit of the first instruction is first pre-decoding information of a first sub-block (which indicates whether that data word/sub-block is an instruction boundary) that is determined based on position information of the first sub-block in the instruction block since each indicator bit corresponds to a data word position/location, see col 9 lines 36-49; in other words, the position of the first data word/sub-block of the first instruction is used by the ILV to determine which indicator bit should be set in the vector of indicators); and
repairing second pre-decoding information of at least one target sub-block in the instruction block based on the first pre-decoding information of the first sub-block when second pre-decoding information of the first sub-block stored in the ICache is different from the first pre-decoding information of the first sub-block (this contingent limitation is not required under BRI of a method claim).
Regarding claim 13, Shang teaches:
13. The method of claim 12, wherein determining the first pre-decoding information of the first sub-block based on position information of the first sub-block in the instruction block comprises at least one of:
determining the first pre-decoding information of the first sub-block based on a previous instruction block when the position information is configured to indicate that the first sub-block is a first one of the plurality of sub-blocks of the instruction block (this contingent limitation is not required under BRI of a method claim); or
taking first information as the first pre-decoding information of the first sub-block when the position information is configured to indicate that the first sub-block is not the first one of the plurality of sub-blocks of the instruction block, wherein the first information is configured to indicate that the instruction stored in the first sub-block is the instruction boundary (this “or” limitation is not required under BRI).
Regarding claim 14, Shang teaches:
14. The method of claim 13, wherein determining the first pre-decoding information of the first sub-block based on the previous instruction block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises:
acquiring instruction information stored in a last one of sub-blocks of the previous instruction block;
taking second information as the first pre-decoding information of the first sub-block when the instruction information is configured to indicate that low-order bits of an instruction are stored in the last one of the sub-blocks, wherein the second information is configured to indicate that the instruction stored in the first sub-block is a non-instruction boundary; and
taking the first information as the first pre-decoding information of the first sub-block when the instruction information is configured to indicate that high-order bits of the instruction or all bits of the instruction are stored in the last one of the sub-blocks.
Regarding claim 15, Shang teaches:
15. The method of claim 12, wherein the at least one target sub-block comprises the first sub-block,
wherein repairing the second pre-decoding information of the at least one target sub-block in the instruction block based on the first pre-decoding information of the first sub-block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises:
repairing the second pre-decoding information of the first sub-block based on the first pre-decoding information of the first sub-block;
when the at least one target sub-block comprises at least one second sub-block, for each second sub-block, determining first pre-decoding information of the second sub-block based on instruction information stored in a previous sub-block of the second sub-block, and repairing second pre-decoding information of the second sub-block based on the first pre-decoding information of the second sub-block; and
writing repaired second pre-decoding information of the at least one target sub-block back into the ICache.
Regarding claim 16, Shang teaches:
16. The method of claim 15, wherein repairing the second pre-decoding information of the first sub-block based on the first pre-decoding information of the first sub-block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises:
updating the second pre-decoding information of the first sub-block to be the first pre-decoding information of the first sub-block.
Regarding claim 17, Shang teaches:
17. The method of claim 15, wherein determining the first pre-decoding information of the second sub-block based on the instruction information stored in the previous sub-block of the second sub-block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises at least one of:
taking second information as the first pre-decoding information of the second sub-block when the instruction information is configured to indicate that low-order bits of an instruction are stored in the previous sub-block; or
taking first information as the first pre-decoding information of the second sub-block when the instruction information is configured to indicate that high-order bits of the instruction or all bits of the instruction are stored in the previous sub-block.
Regarding claim 18, Shang teaches:
18. The method of claim 15, wherein repairing the second pre-decoding information of the second sub-block based on the first pre-decoding information of the second sub-block (this limitation follows from a contingent limitation and is not required under BRI of a method claim) comprises:
reading the second pre-decoding information of the second sub-block from the ICache;
updating the second pre-decoding information of the second sub-block to be the first pre-decoding information of the second sub-block when the second pre-decoding information of the second sub-block is different from the first pre-decoding information of the second sub-block; and
keeping the second pre-decoding information of the second sub-block unchanged when the second pre-decoding information of the second sub-block is the same as the first pre-decoding information of the second sub-block.
Regarding claim 19, Shang teaches:
19. The method of claim 12, further comprising:
acquiring the instruction block from a memory (col 10 lines 6-9: the sequence of data words/instruction block is retrieved/acquired from the main memory if there is a read miss);
determining respective second pre-decoding information of each sub-block of the plurality of sub-blocks (col 11 lines 5-23: the ILV determines a vector of indicators for each data word/sub-block received from the cache, see also col 9 lines 36-49 describing that each indicator bit in the vector of indicators (similar to the vector of indicators generated by the ILV) corresponds to each data word/sub-block in the sequence of data words); and
storing each sub-block of the plurality of sub-blocks and the respective second pre-decoding information of the sub-block into the ICache (col 9 lines 5-8 and col 10 lines 6-9: the sequence of data words/sub-blocks read from main memory are stored into the instruction cache 30; col 11 lines 21-23: the verified boundary information (i.e., the respective second pre-decoding information) is written to the instruction boundary memory 20).
Regarding claim 20, Shang teaches:
20. A computer-readable storage medium having stored thereon a computer program that, when executed by a processor, implements:
determining a first sub-block from a plurality of sub-blocks of an instruction block stored in an Instruction Cache (ICache) based on a fetch instruction (col 10 lines 1-19 discloses fetching/determining a sequence of data words/sub-blocks (including a first data word/sub-block) from a cache line/instruction block of instruction cache 30 based on a request (i.e., a fetch instruction) from the prefetcher; instruction cache 30 and boundary memory 20 are collectively an ICache);
determining first pre-decoding information of the first sub-block based on position information of the first sub-block in the instruction block, wherein the first pre-decoding information of the first sub-block is configured to indicate whether an instruction stored in the first sub-block is an instruction boundary (col 11 lines 5-23: the instruction length verifier (ILV) generates a vector of indicators, the indicator bit of the first instruction is first pre-decoding information of a first sub-block (which indicates whether that data word/sub-block is an instruction boundary) that is determined based on position information of the first sub-block in the instruction block since each indicator bit corresponds to a data word position/location, see col 9 lines 36-49; in other words, the position of the first data word/sub-block of the first instruction is used by the ILV to determine which indicator bit should be set in the vector of indicators); and
repairing second pre-decoding information of at least one target sub-block in the instruction block based on the first pre-decoding information of the first sub-block when second pre-decoding information of the first sub-block stored in the ICache is different from the first pre-decoding information of the first sub-block (col 11 lines 17-27: by writing the correct boundary information to the boundary memory, the corresponding indicators in the boundary memory (i.e., second pre-decoding information of at least one target sub-block) are repaired based on the first pre-decoding information of the first sub-block when the stored indicator for the first sub-block (i.e., second pre-decoding information of the first sub-block stored in the ICache) is different from the indicator for the first sub-block determined by the ILV, see also col 12 lines 34-39 describing comparing the vector of indicators supplied by the boundary memory to those determined by the ILV).
Allowable Subject Matter
Claims 1-11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claims, an Instruction Cache (ICache), a pre-decoding circuit, a pre-decoding check circuit, and a pre-decoding repair circuit, wherein the pre-decoding circuit is configured to: determine a first sub-block from a plurality of sub-blocks of an instruction block stored in the ICache based on a fetch instruction; and determine first pre-decoding information of the first sub-block based on position information of the first sub-block in the instruction block, wherein the first pre-decoding information of the first sub-block is configured to indicate whether an instruction stored in the first sub-block is an instruction boundary, the pre-decoding check circuit is configured to: acquire second pre-decoding information of the first sub-block from the ICache; determine a check result corresponding to the first sub-block based on the first pre-decoding information of the first sub-block and the second pre-decoding information of the first sub-block; and when the check result corresponding to the first sub-block is a first check result, transmit the first check result to the pre-decoding repair circuit, wherein the first check result is configured to indicate that the first pre-decoding information of the first sub-block is different from the second pre-decoding information of the first sub-block, and the pre-decoding repair circuit is configured to: repair second pre-decoding information of at least one target sub-block in the instruction block based on the first pre-decoding information of the first sub-block; and write the repaired second pre-decoding information of the at least one target sub-block back into the ICache., as recited in claim 1.
The closest prior art of record was found to be Shang. While Shang teaches an instruction length verifier (ILV) that determines the first data word of each instruction in a sequence of data words, checks boundary information from a boundary memory, and repairs/updates the boundary information if the verified boundary information is different from the stored boundary information, Shang does not teach a separate pre-decoding circuit, pre-decoding check circuit, and pre-decoding repair circuit performing the respective functions and the interactions between these circuits as described in claim 1. That is, Shang does not teach a pre-decoding circuit that determines a first sub-block and determines first pre-decoding information, a pre-decoding check circuit that acquires second pre-decoding information, determines a check result, and transmits the check result to a pre-decoding repair circuit, which repairs second pre-decoding information and writes the repaired second pre-decoding information back into the ICache. No other prior art was found to cure this deficiency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5758116 teaches circuitry that receives bytes of instruction code and provides a start mark upon finding a first instruction byte, an end mark upon finding a last instruction byte, and circuitry that determines the instruction length, see Abstract
US 5859994 teaches an instruction length calculator logic that can be controlled to disregard a SIB byte in the length calculation, see col 7 lines 35-48
US 20210089311 teaches an instruction boundary prediction unit that adds instruction prediction information to each instruction meta-field and an instruction boundary determination unit that determines instruction boundary information according to prediction information, see [0066], which allows the fetch unit to determine boundary information more efficiently, see [0074]
US 20220100516 teaches a predecode cache that indicates which sections of instruction data is an end boundary of a variable length instruction, an incomplete decode table that indicates which sections have invalid predecode bits, and an instruction length decoder that generates predecode bits for the sections that have invalid predecode bits, see Abstract.
US 20140281246 teaches determining if a predicted first byte of an instruction is correct and incrementing a saturating counter if so, otherwise decrementing the saturating counter, see [0035].
US 20070028050 teaches a predecoder that calculates the next fetch address and stores it in a field of the cache line, see [0024] and Fig. 3
US 20120089783 teaches reading a first copy of an instruction from a cache table and reading a second copy of the instruction from memory using a predictive length obtained from the cache table and then comparing the two copies, if they match then the predictive length is the correct length of the instruction and if they do not match then the prefix of the second instruction is used to determine the actual length and the instruction and length is stored into the cache table, see [0023] and [0033]
US 20090119485 teaches a predecoder that predecodes instructions from a cache with invalid predecode information, forms repaired predecode information, stores it in a predecode repair cache associated with instructions that span across two cache lines, see Abstract.
US 5450605 teaches comparing a boundary marker and an actual boundary marker for an instruction to determine whether they match and updating the boundary marker to the actual boundary marker when they do not match, see Abstract
US 5724422 teaches an instruction length verifier that verifies if instructions were separated correctly, if so the instructions are processed in parallel, otherwise the instructions are decoded serially, see Abstract
US 20100017580 teaches checking circuitry that checks for consistency between a first portion of a pre-decoded instruction in a first cache line and a contiguous second portion stored within a second cache line, if the two portions are not consistent then the pre-decoded instruction is regenerated, see Abstract
US 20030236964 teaches validating or invalidating speculative length decoding, see [0022]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KASIM ALLI whose telephone number is (571)270-1476. The examiner can normally be reached Monday - Friday 9am 5pm.
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/KASIM ALLI/Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183