DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 11/07/2024.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-41 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claim 21, in L7-9, Applicant claims, “to control a shedding of phases in the DCDC converter based upon a comparison between the generated current level and an inductor current of the DCDC converter”, is indefinite. Applicant fails to clearly point out what and how is “the generated current level (i.e., is it input, sensed if so from where or output/load related current?)” being generated.
Claims 22-41 are depending from claim 21, inheriting same deficiencies and thus rejected.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 12, 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zheng et al. (“Zheng”, CN 105763047).
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Following is EXCERPT NOTE(S) OF ZHENG, explaining above Fig. 1, 7 operations:
PMOS M1's source respectively connected with
1st input end of Proportional ratioed MOS tube current sampling circuit and
the voltage input end Vin.
PMOS M1's drain respectively providing current output and also connected to
current summation input end of circuit (wherein translinear circuit (TC) operation is being performed)
connecting with 2nd input end of Proportional ratioed MOS tube current sampling circuit.
The voltage-to-current and current summation circuit comprises:
two voltage-to-current circuit and
a current summation circuit.
Two voltage-to-current circuits are respectively the voltages VX1 and VX2 at the two ends of the inductor L is converted to current, then subtraction, subtracting the two paths of current after the current is charging the sampling capacitor and the sampling capacitor voltage of two end is the sampling signal.
Due to the influence of the non-ideal factors such as DC resistance DCR of the inductor L, the DC value of the sampling signal is offset, so it needs a sampling DC correction circuit to perform DC correction. in the correcting process, it is necessary for the Proportional ratioed MOS tube current sampling circuit to obtain a reference signal.
After subtracting the current flowing from the Vsense node is sampling integrating capacitor C charging. finally, sampling the DC correction and sampling integration circuit, the circuit module comprises a third operational amplifier Amp3, a first capacitor C1, a second capacitor C2, a third resistor R3 of the proportional integrator (dashed in FIG. 7), along with MOS(s) ‘N7-11’ and the fourth resistor R4 of the current subtraction circuit. In-phase input end of sampling voltage Vsense sampling integrating capacitor C of the third operational amplifier Amp3, the sampling voltage Vsen of opposite phase input end proportion MOS tube current sampling circuit, through a proportional integrator, a proportional integrator output end is connected with gate of N7. Additionally, MOS(s) N9-11 driven by same fixed voltage Vbias offset, therefore, N9-11 equal to three constant current source, and the current are equal.
When the proportion integrator input Vsense is equal to Vsen, the output of the proportional integrator is common-mode output of the operational amplifier, which value is about VCC/2, at this time, N7 and N8 have the same bias condition, so with the N8 current flowing through N7 are equal, and are equal to the constant current provided by the N9-11. N7 and N8 form a current mirror, so current flows through M8 equal to the flowing current of the M7 and also equal to the N9; constant current provided by N10 and N11, so the output current of the DC correction circuit the Vsense node is 0, the current flowing through the fourth resistor R4 is also 0, then without correction.
When the Vsense input proportional integrator is greater than Vsen, the output of the proportional integrator increases, so increasing the current flowing through N7, and flows through N9; N10 and N11 is constant, so the redundant current through a fourth resistor R4 to N10, and N8 of current flowing through is reduced, so is through M7 and M8’s current ass well being reduced. At this time, for the Vsense node, filling through M8 current is smaller by the current drawn of N11, so sampling integrating capacitor C will be sampling the DC correction and sampling integrating circuit discharges the voltage of node Vsense will be reduced until the Vsense equal to Vsen, thus realizing correction.
When the proportional integrator input Vsense is less than Vsen, the output of the proportional integrator is reduced, so the current flowing through N7 decreases, and flows through N9. N10 and N11 is constant, so the shortage of current provided by N8 through R4, thus increase the through current of N8, it flows through M7 and M8 current, also increases. At this time, for the Vsense node, filling through M8 of the current greater than the current drawn by N11 of, so sampling integrating capacitor C will be sampling the DC correction circuit charging the voltage of node Vsense will increase until the Vsense equal to Vsen, thus realizing correction.
Obtaining the ratio of MOS tube current sampling circuit of the sampling voltage Vsense through sampling integrating capacitor C on corrected voltage Vsen equal, thus it realizes the accurate sampling of the inductor L current and is a continuous waveform, and switching the circuit state will not generate burr, so precise control can be used for automatic boost inductor L multi-output DC-DC converter and over-current protection, non-continuous inductor L current mode (DCM) detection, etc. there is no mistake, it will not cause system instability.
Above annotated Fig. 1 & 7 and excerpt, from Zheng et al. (“Zheng”, CN 105763047)
Regarding independent claim 1, Zheng teaches (Fig. 1, 7; see above annotated citations) a device comprising:
an adaptive power limitation circuit (see above annotated APLC is also connected to DC-DC) configured to automatically determine active phases of a DCDC converter (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration) based upon power level (based on combined operation of ‘Vin, L, M1 & N1-2’, resulting precise sensed signal on Vx1-2, which can be calculated as power level output using ohm’s law) of the DCDC converter (DC-DC);
the adaptive power limitation circuit (see above annotated APLC is also connected to DC-DC) including:
a translinear circuit (above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC) configured to convert the power level (based on combined operation of ‘Vin, L, M1 & N1-2’, resulting precise sensed signal on Vx1-2, which can be calculated as power level output using ohm’s law) of the DCDC converter to a current level (taught TC is configured to perform: two voltage-to-current circuits are respectively the voltages Vx1 and Vx2 at the two ends of the inductor L is converted to current “two converted current level(s)”, then subtraction, subtracting the two paths of current after the current is charging the sampling capacitor and the sampling capacitor voltage of two end is the sampling signal Vsense. Therefore, the taught two converted current levels being a function of the sensed input Vx1 & output Vx2 voltage of the DCDC converter and a current scaling factor using subtraction technique. See, above annotated NOTE); and
a clamping circuit (see above annotated input signal conditioning circuit with clamping operation (ISCC), also includes a mirror circuit N9-11), operatively connected to the translinear circuit (TC), configured to clamp (using ISCC’s operation when Vsense & Vsen is compared for required DC correction of iL, wherein clamping can be interpreted when reduction of DC correction is performed; see above annotated NOTE) a maximum output current (i.e., under broadest reasonable interpretations (BRI), using DC corrected value of a maximum output current being maximum current on the inductor (max iL) that is received by right hand side multiphase configuration, which is then further adjusted using switching operation of the multiphase configuration, in each phase to provide respective output signal(s) Vo1-n, as required by the load(s)) of the adaptive power limitation circuit to a predetermined value (under BRI, predetermined value being required value of any one of Vo1-n, as required by the respective load).
Regarding claim 2, Zheng teaches the translinear circuit includes a plurality of switches configured to generate a reciprocal function (above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC).
Regarding claim 3, Zheng teaches the translinear circuit includes a cascode configured to reduce an early effect of the plurality of switches (above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC).
Regarding claim 4, Zheng teaches the translinear circuit includes an amplifier circuit configured to reduce a β effect of the plurality of switches (above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC).
Regarding claim 5, Zheng teaches the adaptive power limitation circuit includes a mirror circuit operatively connected to the clamping circuit (see above annotated input signal conditioning circuit with clamping operation (ISCC), also includes a mirror circuit N9-11. Also note that above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC).
Regarding claim 6, Zheng teaches an input signal conditioning circuit (ISCC), which is operatively connected to the translinear circuit (TC), configured to sense a voltage (Vsen) of the DCDC converter (DC-DC).
Regarding claim 12, Zheng teaches the input signal conditioning circuit (ISCC) is configured to measure an input voltage of the DCDC converter (sensed Vin is considered by proportional MOS tube current sampling circuit, which generated Vsen for ISCC).
Regarding claim 14, Zheng teaches the DCDC converter is a two-channel synchronous boost converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claim 15, Zheng teaches the DCDC converter is a two-channel synchronous buck converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claim 16, Zheng teaches the DCDC converter is a single channel synchronous boost converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claim 17, Zheng teaches the DCDC converter is a single channel synchronous buck converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claim 18, Zheng teaches the DCDC converter is a buck-boost controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claim 19, Zheng teaches the DCDC converter is a multiphase boost converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claim 20, Zheng teaches the DCDC converter is a multiphase buck converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9, 12, 15, 17, 20-24, 26-27, 30, 33, 36, 38, 41-42, 44, 46, 49, 51, 54 are rejected under 35 U.S.C. 103 as being unpatentable over Qiu et al. (“Qiu”, US Pat 8072200), in view of Carroll et al. (“Carroll”, US Pub 2009/0198460).
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Above Fig. 1 & 3 from Qiu et al. (“Qiu”, US Pat 8072200)
Regarding independent claim 1, Qiu teaches (Fig. 1, 3, 5; col. 2 L11-col. 10 L31) a device comprising:
an adaptive power limitation circuit (Fig. 1, 3, 5; adaptive power limitation circuit (APLC) being combined operation of ‘105’s detail in Fig. 3, 107 (or 307), 109’ of 101) configured to automatically determine active phases (under BRI, Qiu teaches active phases) of a DCDC converter (Fig. 1, 3, 5; the multi-phase buck DC-DC converter (DC-DC) being any one of a single-channel at node 103 or two or more-channel output end of L1-2) based upon power level of the DCDC converter (respective power phase leveled circuits);
the adaptive power limitation circuit (APLC) including:
a translinear circuit (Translinear Circuit (TC) being combined operation of 305, 308, 307’) configured to convert the power level (respective power phase leveled circuits) of the DCDC converter to a current level (I sen corr, using feedback loop in 101); and
a clamping circuit (Clamping circuit (clamp) being combined operation of ‘311, 109, 313, 315’), operatively connected to the translinear circuit (TC), configured to clamp a maximum output current (maximum I sen corr, using feedback loop in 101, as required by the load) of the adaptive power limitation circuit (APLC) to a predetermined value (predetermined value being value that is required by the load).
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Above Fig. 1-4 and related excerpt from Carroll et al. (“Carroll”, US Pub 2009/0198460)
Furthermore, Carroll teaches (Fig. 1-7; Para 40-132, specifically Para 65-68, 109) controlled operation is performed using shedding one or more phases of the DCDC converter.
[NOTE Carroll teaches: a switch-mode controller (Fig. 1-5; driver circuits ‘210-1, 210-2’ in 105); the adaptive power limitation circuit (Fig. 4; adaptive power limitation circuit (APLS) being combined operation of ‘115-1 thru n, 105’s other elements, except for taught driver and 140’), configured to control a shedding of phases (using operation of taught APLS; Para 109) in the DCDC converter (Fig. 1-5), using plural means of comparison (Fig. 3-4; combined operation of 115-1 thru n, which includes ‘310, 320 and 325’, 105’s other elements specifically 415 except for taught driver, along with 140’s plural comparing means, specifically 435, etc.) between adjusted/generated current level (i.e., 435’s output used in a feedback loop operation) and an inductor current (325’s another input that is connected between 320 and 305) of the DCDC converter); and an input/output signal conditioning circuit (i.e., elements in 105 & 140 that assists in sensing and adjusting Vin, Vout, In, Iout, Pin, Pout for efficient operation) operatively connected to the translinear circuit (TC 435) to sense an input (Vin) and output (Vout) voltage of the DCDC converter in order to generate an input current (i.e., input of 435) to the translinear circuit (TC 435’s input end).]
Thus, it would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu’s device to include controlled operation for performing shedding of one or more phases of the DCDC converter to select required active phase(s), using some kind of comparison between adjusted/generated current level, sensed input/output voltages and inductor current, as disclosed by Carroll, as doing so would have provided an improved and efficient light-load requirements to reduce losses within the system and its method, as taught by Carroll (Para 109 and abstract).
Regarding independent claim 21, Qiu teaches (Fig. 1, 3, 5; col. 2 L11-col. 10 L31) a system comprising:
a DCDC converter (Fig. 1, 3, 5; the multi-phase buck DC-DC converter (DC-DC) being any one of a single-channel at node 103 or two or more-channel output end of L1-2);
an adaptive power limitation circuit (Fig. 1, 3, 5; adaptive power limitation circuit (APLC) being combined operation of ‘105’s detail in Fig. 3, 107 (or 307), 109’ of 101),
operatively connected to the DCDC converter (DC-DC),
configured to automatically determine … the DCDC converter (DC-DC)
based upon power level of the DCDC converter (respective power phase leveled circuits); and
a switch-mode controller (although not shown, but anticipated drivers in 101),
operatively connected to the DCDC converter (DC-DC) and the adaptive power limitation circuit (APLC),
configured to control a … in the DCDC converter (Fig. 1; the multi-phase buck DC-DC converter being any one of a single-channel at node 103 or two or more-channel output end of L1-2)
based upon a comparison (i.e., combined operation of 301’s 303 and other elements in 101; wherein, 303 comparing +/- IS and amplifying the difference to control 305’s gate; and controller 101 receiving sensed feedback voltage from output node 103, anticipated to be used for some kind of comparing) between
the generated current level (I sen corr, using feedback loop in 101) and
an inductor current (-IS) of the DCDC converter (DC-DC);
the adaptive power limitation circuit (APLC)
including
a translinear circuit (Translinear Circuit (TC) being combined operation of 305, 308, 307’) and
a clamping circuit (Clamping circuit (clamp) being combined operation of ‘311, 109, 313, 315’)
operatively connected to the translinear circuit (TC).
However, Carroll teaches (Fig. 1-7; Para 40-132, specifically Para 65-68, 109) controlled operation is performed using shedding one or more phases of the DCDC converter.
[NOTE Carroll teaches: a switch-mode controller (Fig. 1-5; driver circuits ‘210-1, 210-2’ in 105); the adaptive power limitation circuit (Fig. 4; adaptive power limitation circuit (APLS) being combined operation of ‘115-1 thru n, 105’s other elements, except for taught driver and 140’), configured to control a shedding of phases (using operation of taught APLS; Para 109) in the DCDC converter (Fig. 1-5), using plural means of comparison (Fig. 3-4; combined operation of 115-1 thru n, which includes ‘310, 320 and 325’, 105’s other elements specifically 415 except for taught driver, along with 140’s plural comparing means, specifically 435, etc.) between adjusted/generated current level (i.e., 435’s output used in a feedback loop operation) and an inductor current (325’s another input that is connected between 320 and 305) of the DCDC converter); and an input/output signal conditioning circuit (i.e., elements in 105 & 140 that assists in sensing and adjusting Vin, Vout, In, Iout, Pin, Pout for efficient operation) operatively connected to the translinear circuit (TC 435) to sense an input (Vin) and output (Vout) voltage of the DCDC converter in order to generate an input current (i.e., input of 435) to the translinear circuit (TC 435’s input end).]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu’s system and its method to include controlled operation for performing shedding of one or more phases of the DCDC converter, using some kind of comparison between adjusted/generated current level, sensed input/output voltages and inductor current, as disclosed by Carroll, as doing so would have provided an improved and efficient light-load requirements to reduce losses within the system and its method, as taught by Carroll (Para 109 and abstract).
Regarding independent claim 42, Qiu teaches (Fig. 1, 3, 5; col. 2 L11-col. 10 L31) a method for controlling one or more phases of a DCDC converter (Fig. 1, 3, 5; the multi-phase buck DC-DC converter (DC-DC) being any one of a single-channel at node 103 or two or more-channel output end of L1-2), comprising:
(a) sensing a voltage (i.e., controller 101 receiving sensed feedback voltage from output node 103) of the DCDC converter (DC-DC);
(b) sensing (i.e., 303 comparing +/- IS and amplifying the difference to control 305’s gate) an inductor current (IL 1-n) of the DCDC converter (DC-DC);
(c) converting, using a reciprocal function (Translinear Circuit (TC) being combined operation of 305, 308, 307’),
the sensed voltage (i.e., controller 101 receiving sensed feedback voltage from output node 103) of the DCDC converter (DC-DC)
to generate a current level (I sen corr, using feedback loop in 101); and
(d) controlling a phase of the DCDC converter
based upon a comparison (i.e., combined operation of 301’s 303 and other elements in 101; wherein, 303 comparing +/- IS and amplifying the difference to control 305’s gate; and controller 101 receiving sensed feedback voltage from output node 103, anticipated to be used for some kind of comparing) of
the generated current level (I sen corr, using feedback loop in 101) and
the sensed inductor current (-IS).
However, Qiu fails to teach controlled operation is performed using shedding one or more phases of the DCDC converter (i.e., using some kind of adjusted/generated current level and an inductor current).
However, Carroll teaches (Fig. 1-7; Para 40-132, specifically Para 65-68, 109) controlled operation is performed using shedding one or more phases of the DCDC converter.
[NOTE Carroll teaches: a switch-mode controller (Fig. 1-5; driver circuits ‘210-1, 210-2’ in 105); the adaptive power limitation circuit (Fig. 4; adaptive power limitation circuit (APLS) being combined operation of ‘115-1 thru n, 105’s other elements, except for taught driver and 140’), configured to control a shedding of phases (using operation of taught APLS; Para 109) in the DCDC converter (Fig. 1-5), using plural means of comparison (Fig. 3-4; combined operation of 115-1 thru n, which includes ‘310, 320 and 325’, 105’s other elements specifically 415 except for taught driver, along with 140’s plural comparing means, specifically 435, etc.) between adjusted/generated current level (i.e., 435’s output used in a feedback loop operation) and an inductor current (325’s another input that is connected between 320 and 305) of the DCDC converter); and an input/output signal conditioning circuit (i.e., elements in 105 & 140 that assists in sensing and adjusting Vin, Vout, In, Iout, Pin, Pout for efficient operation) operatively connected to the translinear circuit (TC 435) to sense an input (Vin) and output (Vout) voltage of the DCDC converter in order to generate an input current (i.e., input of 435) to the translinear circuit (TC 435’s input end).]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu’s system and its method to include controlled operation for performing shedding of one or more phases of the DCDC converter, using some kind of comparison between adjusted/generated current level, sensed input/output voltages and inductor current, as disclosed by Carroll, as doing so would have provided an improved and efficient light-load requirements to reduce losses within the system and its method, as taught by Carroll (Para 109 and abstract).
Regarding claims 2, 22, Qiu teaches the translinear circuit includes a plurality of switches configured to generate a reciprocal function (taught each TC for respective phase includes plurality of switches in a mirror configuration, and a switch that driven by taught comparison’s output, in order to perform (i) a plurality of switches to generate a reciprocal function, (ii) a cascode to reduce an early effect of the plurality of switches and/or (iii) an amplifier circuit to reduce a β effect of the plurality of switches).
Regarding claims 3, 23, Qiu teaches the translinear circuit includes a cascode configured to reduce an early effect of the plurality of switches (taught each TC for respective phase includes plurality of switches in a mirror configuration, and a switch that driven by taught comparison’s output, in order to perform (i) a plurality of switches to generate a reciprocal function, (ii) a cascode to reduce an early effect of the plurality of switches and/or (iii) an amplifier circuit to reduce a β effect of the plurality of switches).
Regarding claims 4, 24, Qiu teaches the translinear circuit includes an amplifier circuit configured to reduce a β effect of the plurality of switches (taught each TC for respective phase includes plurality of switches in a mirror configuration, and a switch that driven by taught comparison’s output, in order to perform (i) a plurality of switches to generate a reciprocal function, (ii) a cascode to reduce an early effect of the plurality of switches and/or (iii) an amplifier circuit to reduce a β effect of the plurality of switches).
Regarding claims 5, 26, Qiu teaches the adaptive power limitation circuit (taught APLC) includes a mirror circuit operatively (taught each TC for respective phase includes plurality of switches in a mirror configuration, and a switch that driven by taught comparison’s output, in order to perform (i) a plurality of switches to generate a reciprocal function, (ii) a cascode to reduce an early effect of the plurality of switches and/or (iii) an amplifier circuit to reduce a β effect of the plurality of switches) connected to the clamping circuit (taught clamp, which also includes current-mirror).
Regarding claims 6, 27, Qiu teaches an input signal conditioning circuit (controller 101 receiving sensed feedback voltage from output node 103, anticipated to be used for some kind of comparing), which is operatively connected to the translinear circuit (taught TC), configured to sense a voltage (sensed feedback voltage from output node 103) of the DCDC converter.
Furthermore, Carroll teaches an input signal conditioning circuit (i.e., elements in 105 & 140 that assists in sensing and adjusting Vin, Vout, In, Iout, Pin, Pout for efficient operation), which is operatively connected to the translinear circuit (TC 435), configured to sense a voltage (sensed Vin, Vout, Pin, Iin) of the DCDC converter.
Thus, it would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu’s system and its method to include controlled operation for performing shedding of one or more phases of the DCDC converter, using some kind of comparison between adjusted/generated current level, sensed input/output voltages and inductor current, as disclosed by Carroll, as doing so would have provided an improved and efficient light-load requirements to reduce losses within the system and its method, as taught by Carroll (Para 109 and abstract).
Regarding claim 9, 30, 44, Qiu teaches the input signal conditioning circuit is configured to sense an output voltage of the DCDC converter (controller 101 receiving sensed feedback voltage from output node 103, anticipated to be used for some kind of comparing).
Furthermore, Carroll teaches an input signal conditioning circuit (i.e., elements in 105 & 140 that assists in sensing and adjusting Vin, Vout, In, Iout, Pin, Pout for efficient operation), which is operatively connected to the translinear circuit (TC 435), configured to sense a voltage (sensed Vin, Vout, Pin, Iin) of the DCDC converter.
Thus, it would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu’s system and its method to include controlled operation for performing shedding of one or more phases of the DCDC converter, using some kind of comparison between adjusted/generated current level, sensed input/output voltages and inductor current, as disclosed by Carroll, as doing so would have provided an improved and efficient light-load requirements to reduce losses within the system and its method, as taught by Carroll (Para 109 and abstract).
Regarding claim 12, 33, 46, Qiu fails to teach the input signal conditioning circuit is configured to measure an input voltage of the DCDC converter.
However, Carroll teaches the input signal conditioning circuit (i.e., elements in 105 & 140 that assists in sensing and adjusting Vin, Vout, In, Iout, Pin, Pout for efficient operation) is configured to measure an input voltage (Vin, Pin, Iin) of the DCDC converter.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu’s system and its method to include controlled operation for performing shedding of one or more phases of the DCDC converter, using some kind of comparison between adjusted/generated current level, sensed input/output voltages and inductor current, as disclosed by Carroll, as doing so would have provided an improved and efficient light-load requirements to reduce losses within the system and its method, as taught by Carroll (Para 109 and abstract).
Regarding claim 15, 36, 49, Qiu teaches the DCDC converter is a two-channel synchronous buck converter controller (Fig. 1, 3, 5; the multi-phase buck DC-DC converter (DC-DC) being any one of a single-channel at node 103 or two or more-channel output end of L1-2).
Regarding claim 17, 38, 51, Qiu teaches the DCDC converter is a single channel synchronous buck converter controller (Fig. 1, 3, 5; the multi-phase buck DC-DC converter (DC-DC) being any one of a single-channel at node 103 or two or more-channel output end of L1-2).
Regarding claim 20, 41, 54, Qiu teaches the DCDC converter is a multiphase buck converter controller (Fig. 1, 3, 5; the multi-phase buck DC-DC converter (DC-DC) being any one of a single-channel at node 103 or two or more-channel output end of L1-2).
Claims 35, 37, 39-40, 48, 50, 52-53 are rejected under 35 U.S.C. 103 as being unpatentable over Qiu (US Pat 8072200), in view of Carroll (US Pub 2009/0198460) and Zheng et al. (“Zheng”, US Pat 11235668).
Regarding claims 35, 48, Qiu & Carroll fail to teach the DCDC converter is a two-channel synchronous boost converter controller.
However, Zheng teaches use of the DCDC converter being a two-channel synchronous boost converter controller (Zheng teaches in col. 2 L20-30: Further, the power supplying module is implemented by photovoltaic energization, fuel cell energization and fuel generator energization, and single-channel or multi-channel parallel energization can be adopted…the first DC-DC circuit and the second DC-DC circuit may be a buck-type circuit, a synchronous buck-type circuit or a buck-boost-type circuit).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu and Zheng collectively taught system and its method to include the DC-DC converter being any one of a single-channel, two-channel or multi-phase buck-boost converter controller, as disclosed by Zheng, as doing so would have provided an efficient with a stable power supply for various requirements of the load(s), as taught by Zheng (abstract).
Regarding claims 37, 50, Qiu & Carroll fail to teach the DCDC converter is a single channel synchronous boost converter controller.
However, Zheng teaches use of the DCDC converter being the DCDC converter is a single channel synchronous boost converter controller (Zheng teaches in col. 2 L20-30: Further, the power supplying module is implemented by photovoltaic energization, fuel cell energization and fuel generator energization, and single-channel or multi-channel parallel energization can be adopted…the first DC-DC circuit and the second DC-DC circuit may be a buck-type circuit, a synchronous buck-type circuit or a buck-boost-type circuit).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu and Zheng collectively taught system and its method to include the DC-DC converter being any one of a single-channel, two-channel or multi-phase buck-boost converter controller, as disclosed by Zheng, as doing so would have provided an efficient with a stable power supply for various requirements of the load(s), as taught by Zheng (abstract).
Regarding claims 39, 52, Qiu & Carroll fail to teach the DCDC converter is a buck-boost controller.
However, Zheng teaches use of the DCDC converter is a buck-boost controller (Zheng teaches in col. 2 L20-30: Further, the power supplying module is implemented by photovoltaic energization, fuel cell energization and fuel generator energization, and single-channel or multi-channel parallel energization can be adopted…the first DC-DC circuit and the second DC-DC circuit may be a buck-type circuit, a synchronous buck-type circuit or a buck-boost-type circuit).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu and Zheng collectively taught system and its method to include the DC-DC converter being any one of a single-channel, two-channel or multi-phase buck-boost converter controller, as disclosed by Zheng, as doing so would have provided an efficient with a stable power supply for various requirements of the load(s), as taught by Zheng (abstract).
Regarding claims 40, 53, Qiu & Carroll fail to teach the DCDC converter is a multiphase boost converter controller.
However, Zheng teaches use of the DCDC converter is a multiphase boost converter controller (Zheng teaches in col. 2 L20-30: Further, the power supplying module is implemented by photovoltaic energization, fuel cell energization and fuel generator energization, and single-channel or multi-channel parallel energization can be adopted…the first DC-DC circuit and the second DC-DC circuit may be a buck-type circuit, a synchronous buck-type circuit or a buck-boost-type circuit).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Qiu and Zheng collectively taught system and its method to include the DC-DC converter being any one of a single-channel, two-channel or multi-phase buck-boost converter controller, as disclosed by Zheng, as doing so would have provided an efficient with a stable power supply for various requirements of the load(s), as taught by Zheng (abstract).
Allowable Subject Matter
Claims 7-8, 10-11, 13, 43, 45 and 47 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7 and 43, cited art(s) failed to teach, as follows,
“The current level generated by the adaptive power limitation circuit is a function of a maximum power of the DCDC converter, the sensed voltage of the DCDC converter, and a current scaling factor”, as claimed in claim 7; and similarly
“the generated current level is a function of a maximum power of the DCDC converter, the sensed voltage of the DCDC converter, and a current scaling factor”, as claimed in claim 43.
Claim 8 is depending from claims 7.
Regarding claims 10, 45, cited art(s) failed to teach, as follows,
“wherein the current level generated by the adaptive power limitation circuit is a function of a maximum power of the DCDC converter, the sensed output voltage of the DCDC converter, and a current scaling factor”, as claimed in claim 10; and similarly
“wherein the generated current level is a function of a maximum power of the DCDC converter, the sensed output voltage of the DCDC converter, and a current scaling factor”, as claimed in claim 45.
Regarding claim 11, cited art(s) failed to teach, as follows, “wherein the input signal conditioning circuit is configured to generate an input current to the translinear circuit; the input current being a function of a maximum current acceptable by the adaptive power limitation circuit, the sensed output voltage of the DCDC converter, and a maximum output voltage of the DCDC converter”.
Regarding claims 13 and 47, cited art(s) failed to teach, as follows,
“the current level generated by the adaptive power limitation circuit is a function of a maximum power of the DCDC converter, the sensed input voltage of the DCDC converter, and a current scaling factor”, as claimed in claim 13; and similarly
“wherein the generated current level is a function of a maximum power of the DCDC converter, the sensed input voltage of the DCDC converter, and a current scaling factor”, as claimed in claim 47.
Claims 28-29, 31-32, 34 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 28, cited art(s) failed to teach, “the current level generated by the adaptive power limitation circuit is a function of a maximum power of the DCDC converter, the sensed voltage of the DCDC converter, and a current scaling factor”.
Claims 29 is depending from claim 28.
Regarding claim 31, cited art(s) failed to teach, “wherein the current level generated by the adaptive power limitation circuit is a function of a maximum power of the DCDC converter, the sensed output voltage of the DCDC converter, and a current scaling factor”.
Regarding claim 32, cited art(s) failed to teach, “wherein the input signal conditioning circuit is configured to generate an input current to the translinear circuit; the input current being a function of a maximum current acceptable by the adaptive power limitation circuit, the sensed output voltage of the DCDC converter, and a maximum output voltage of the DCDC converter”.
Regarding claim 34, cited art(s) failed to teach, “the current level generated by the adaptive power limitation circuit is a function of a maximum power of the DCDC converter, the sensed input voltage of the DCDC converter, and a current scaling factor”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Another 102 (a)(1) and (a)(2) prior art: Luff (US Pat 2019/131877)
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Above Fig.(s) are from Luff
Regarding claims 1, 2-6, 9, 16-17, 21-24, 26-27, 30, 37-38, 42, 44, 50-51, Luff teaches (Fig. 1-19; Para 82-100) a device comprising:
an adaptive power limitation circuit (Fig. 2, 19; 210)
configured to automatically determine active phases of a DCDC converter (Fig. 2; single channel DC-DC buck-boost controller)
based upon power level of the DCDC converter (Fig. 2, 19; power level output Vout/Iout);
the adaptive power limitation circuit (Fig. 2, 19; 210) including:
a translinear circuit (1906 and 1804; Para 95. Note that taught translinear circuit (TC) includes (i) a plurality of switches to generate a reciprocal function, (ii) a cascode to reduce an early effect of the plurality of switches and/or (iii) an amplifier circuit in to reduce a β effect of the plurality of switches; and an input signal conditioning circuit (1902, 218) operatively connected to the translinear circuit (1906 and 1804) to sense an input and output voltage (Vout) of the DCDC converter in order to generate an input current (i.e., input end operation of 1806, being a function of a maximum current acceptable by the adaptive power limitation circuit (210), the sensed input using 218 and output voltage using 1902 of the DCDC converter, and a maximum output voltage Vout of the DCDC converter) to the translinear circuit (1906 and 1804)) configured to convert the power level of the DCDC converter (Fig. 2, 19; power level output Vout/Iout) to a current level (i.e., output of 1906 and 1804 being adjusted current level, since both uses current mode-controlled operation, which is then fed to Fig. 20 comparing meant for further adjustment); and
a clamping circuit (CM operation with 1902 and 1804; Para 28,82, 85, 90-93), operatively connected to the translinear circuit (1906 and 1804; Para 95), configured to clamp a maximum output current (Fig. 2, 19; power level output Vout/Iout) of the adaptive power limitation circuit (Fig. 2, 19; 210) to a predetermined value (Vtarget or Vref).
However, Luff fails to teach phase-shedding technique. However, such technique can be easily be adopted, as shown in above 103 Rejection, for brevity’s sake is not repeated here.
Another 102/103 Prior Art: Zheng (CN 105763047)
Regarding independent claim 21, Zheng teaches (Fig. 1, 7; see above annotated citations) a system comprising:
a DCDC converter (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration);
an adaptive power limitation circuit (see above annotated APLC), operatively connected to the DCDC converter (DC-DC), configured to automatically determine active phases of the DCDC converter (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration) based upon power level (based on combined operation of ‘Vin, L, M1 & N1-2’, resulting precise sensed signal on Vx1-2, which can be calculated as power level output using ohm’s law) of the DCDC converter (DC-DC); and
a switch-mode controller (not shown, but anticipated controller to control the switches in Fig. 1), operatively connected to the DCDC converter (DC-DC) and the adaptive power limitation circuit (see above annotated APLC), configured to control … the DCDC converter (DC-DC) based upon … the generated current level (i.e., current sampling circuit’s two inputs) and an inductor current of the DCDC converter (iL’s both end being sensed on Vx1-2);
the adaptive power limitation circuit including
a translinear circuit (above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC) and
a clamping circuit (see above annotated input signal conditioning circuit with clamping operation (ISCC), also includes a mirror circuit N9-11) operatively connected to the translinear circuit (TC).
[Additional NOTE: Zheng teaches that the clamp circuit is configured to clamp (using ISCC’s operation when Vsense & Vsen is compared for required DC correction of iL, wherein clamping can be interpreted when reduction of DC correction is performed; see above annotated NOTE) a maximum output current (i.e., under broadest reasonable interpretations (BRI), using DC corrected value of a maximum output current being maximum current on the inductor (max iL) that is received by right hand side multiphase configuration, which is then further adjusted using switching operation of the multiphase configuration, in each phase to provide respective output signal(s) Vo1-n, as required by the load(s)) of the adaptive power limitation circuit to a predetermined value (under BRI, predetermined value being required value of any one of Vo1-n, as required by the respective load).]
However, Zheng fails to teach a switch-mode controller, operatively connected to the DCDC converter and the adaptive power limitation circuit, configured to control a shedding of phases in the DCDC converter based upon a comparison between the generated current level and an inductor current of the DCDC converter.
Regarding independent claim 42, Zheng teaches (Fig. 1, 7; see above annotated citations) a method for controlling (not shown, but anticipated controller to control the switches in Fig. 1) one or more phases of a DCDC converter (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration), comprising:
(a) sensing a voltage (i.e., Vsen) of the DCDC converter (DC-DC);
(b) sensing an inductor current (current on L (iL) is sensed at both ends of L, as Vx1-2, which are received by proportional MOS tube current sampling circuit and above annotated TC) of the DCDC converter (DC-DC);
(c) converting (i.e., see above annotated Adaptive Power Limitation Circuit (APLC), which includes ISCC and TC), using a reciprocal function (i.e., above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC),
the sensed voltage (Vsen) of the DCDC converter (DC-DC) to generate a current level (taught TC is configured to perform: two voltage-to-current circuits are respectively the voltages Vx1 and Vx2 at the two ends of the inductor L is converted to current “two converted current level(s)”, then subtraction, subtracting the two paths of current after the current is charging the sampling capacitor and the sampling capacitor voltage of two end is the sampling signal Vsense. Therefore, the taught two converted current levels being a function of the sensed input Vx1 & output Vx2 voltage of the DCDC converter and a current scaling factor using subtraction technique. See, above annotated NOTE); and
(d) controlling a phase of the DCDC converter (DC-DC) based upon … the generated current level (i.e., current sampling circuit’s two inputs) and the sensed inductor current (iL’s both end being sensed on Vx1-2).
[Additional NOTE: Zheng teaches that the clamp circuit see above annotated input signal conditioning circuit with clamping operation (ISCC), also includes a mirror circuit N9-11) is configured to clamp (using ISCC’s operation when Vsense & Vsen is compared for required DC correction of iL, wherein clamping can be interpreted when reduction of DC correction is performed; see above annotated NOTE) a maximum output current (i.e., under broadest reasonable interpretations (BRI), using DC corrected value of a maximum output current being maximum current on the inductor (max iL) that is received by right hand side multiphase configuration, which is then further adjusted using switching operation of the multiphase configuration, in each phase to provide respective output signal(s) Vo1-n, as required by the load(s)) of the adaptive power limitation circuit to a predetermined value (under BRI, predetermined value being required value of any one of Vo1-n, as required by the respective load).]
However, Zheng fails to teach controlled operation is performed using shedding one or more phases of the DCDC converter, specifically using controlled step (d) shedding a phase of the DCDC converter based upon a comparison of the generated current level and the sensed inductor current.
Regarding claim 22, Zheng teaches the translinear circuit includes a plurality of switches configured to generate a reciprocal function (above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC).
Regarding claim 23, Zheng teaches the translinear circuit includes a cascode configured to reduce an early effect of the plurality of switches (above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC).
Regarding claim 24, Zheng teaches the translinear circuit includes an amplifier circuit configured to reduce a β effect of the plurality of switches (above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC).
Regarding claim 26, Zheng teaches the adaptive power limitation circuit includes a mirror circuit operatively connected to the clamping circuit (see above annotated input signal conditioning circuit with clamping operation (ISCC), also includes a mirror circuit N9-11. Also note that above annotated translinear circuit (TC) includes switches and other elements in such a way that operative to include and perform any one or all of the following limitations: (i) a plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) to generate a reciprocal function (when combined with Amp1-2 & R1-2), (ii) a cascode to reduce an early effect (when combined with Amp1-2 & R1-2) of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror) and/or (iii) an amplifier circuit (when combined with Amp1-2 & R1-2) to reduce a β effect of the plurality of switches (M2-5, N3-6; wherein M2-3, M4-5 and N5-6 forms current mirror); APLC also include an input signal conditioning circuit with clamping operation (ISCC) operatively connected to the taught TC to sense an input Vx1 and output Vx2 voltage of the DCDC converter in order to generate a signal Vsense for taught TC).
Regarding claim 27, Zheng teaches an input signal conditioning circuit (ISCC), which is operatively connected to the translinear circuit (TC), configured to sense a voltage (Vsen) of the DCDC converter (DC-DC).
Regarding claims 33, 46, Zheng teaches the input signal conditioning circuit (ISCC) is configured to measure an input voltage of the DCDC converter (sensed Vin is considered by proportional MOS tube current sampling circuit, which generated Vsen for ISCC).
Regarding claims 35, 48, Zheng teaches the DCDC converter is a two-channel synchronous boost converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claims 36, 49, Zheng teaches the DCDC converter is a two-channel synchronous buck converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claims 37, 50, Zheng teaches the DCDC converter is a single channel synchronous boost converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claims 38, 51, Zheng teaches the DCDC converter is a single channel synchronous buck converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claims 39, 52, Zheng teaches the DCDC converter is a buck-boost controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claims 40, 53, Zheng teaches the DCDC converter is a multiphase boost converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
Regarding claims 41, 54, Zheng teaches the DCDC converter is a multiphase buck converter controller (Fig. 1; DC-DC converter (DC-DC) being a single-channel phase(s) buck-boost converter controller when considering Vo1 only, two-channel phase(s) buck-boost converter controller when considering Vo1-2 only or multi-phase(s) buck-boost converter controller when considering Vo1-n. Note Fig. 1’s Mip, Min, L, Mon is same as Fig. 7’s M1, N1, L, N2, respectively; and Fig. 7’s right hand side multiphase configuration although not shown, but is considered same as Fig. 1’s right hand side multiphase configuration).
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
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