DETAILED ACTION
1. This action is in response to the election filed on 6/10/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
3. Applicant’s election without traverse of Group I (claims 1-14, 27-44, and 45-49) in the reply filed on 6/10/26 is acknowledged.
Claim Objections
4. Claim 1, 3-5, and 12 are objected to because of the following informalities:
Claim 1 recites “voltage on the first pin is below a certain threshold” should be replaced with “a voltage on the first pin is below a certain threshold”.
Claims 3 and 5 recites “a certain threshold” should be replaced with “the certain threshold”.
Claim 4 recites “the first pin to a pre-determined voltage level” should be replaced with “the first pin to the pre-determined voltage level”.
Claim 12 recites “at least two responder channels “should be replaced with “the at least two responder channels”; and “a pre-determined voltage level” should be replaced with “the pre-determined voltage level”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claim 47 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 47, the limitation recites “the first pin … and the second pin”. It is unclear to which device is the first and second pin (i.e. requestor or responder device)
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 45-49 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagasawa (US 20110169471).
Regarding claim 45: Nagasawa disclsoes a system (i.e. figures 2-8) comprising:
a requestor device (i.e. POL [2]) having a requestor second pin (i.e. PN10 [2]) and a requestor first pin (i.e. PN15 [2]);
a responder device (i.e. POL [1]) having a responder second pin (i.e. PN10 [1]) and a responder first pin (i.e. PN15 [1]);
said requestor second pin (i.e. PN10 [2]) being connected to said responder second pin (i.e. PN10 [1]);
said requestor first pin (i.e. PN15 [2]) being connected to said responder first pin (i.e. PN15 [1]);
said requestor first pin (i.e. PN15 [2]) being configured to buffer and first compensation voltage (i.e. from SHR) of a channel (i.e. channel of POL [2]) of said requestor device (i.e. POL [2]) with said responder device (i.e. POL [1]);
said requestor second pin (i.e. PN10 [2]) being configured to synchronize switching activity (i.e. by CLK signal) between said requestor device (i.e. POL [2]) and said responder device (i.e. POL [1]) (i.e. 54, 62-67, 86-87, 108-110).
Regarding claim 46: (i.e. figures 2-8) wherein said requestor device is a first integrated circuit package and said responder device is a second integrated circuit package (i.e. configuration of (i.e. POL [1]) (i.e. POL [2])).
Regarding claim 47: (i.e. figures 2-8) wherein the first pin (i.e. PN15 [1]) is a pin for sharing a compensation voltage (i.e. provided by the voltage of SHR) and the second pin (i.e. PN10 [1]) is a pin to synchronize other device operation with a clock signal (i.e. CLK signal) (i.e. 54, 62-67, 86-87, 108-110).
Regarding claim 48: (i.e. figures 2-8) wherein the requestor device (i.e. POL [2]) and the responder device (i.e. POL [2]) are included in a multiphase boost converter controller (i.e. controller of figure 2).
Regarding claim 49: (i.e. figures 2-8) wherein the requestor device and the responder device are included in a multiphase buck converter controller (i.e. ¶ 4).
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1-5, 7, 9-12, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nagasawa (US 20110169471) in view of Carroll et al. (US 20120091977).
Regarding claim 1: Nagasawa disclsoes a method (i.e. figures 2-8), comprising:
(a) pulling down, by a responder device (i.e. POL [1]), a first pin (i.e. PN15 [1]) to a pre-determined voltage level (i.e. voltage of SHR to the voltage level of CS1, output from D1 to pin PN15[1]) when a responder channel (i.e. output channel of POL [1]) of the responder device (i.e. POL [1]) is turned OFF (i.e. inactive state);
(b) detecting that a requestor device (i.e. POL [2]) coupled to the responder device (i.e. POL [1]) has frozen a synchronization signal (i.e. signal CLK is OFF) on a second pin (i.e. PN10 [2]) when voltage on the first pin (i.e. PN15 [1]) is below a certain threshold (i.e. threshold of CS); and
(c) terminating a pulling down, by the responder device (i.e. POL [1]), of the first pin (i.e. PN15 [1]) to the pre-determined voltage level (i.e. voltage of SHR to the voltage level of CS1, output from D1 to pin PN15[1]) after the responder device (i.e. POL [1]) detects no activity (i.e. during off period of CLK) on the second pin (i.e. PN10 [2] or PN9 [1]) (i.e. 54, 62-67, 86-87, 108-110),
but does not specifically disclose a responder device having at least two responder channels.
Carroll et al. disclose a power supply (i.e. figure 1) comprising a responder device having at least two responder channels (i.e. phase A and B).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagasawa’s invention with the power supply as disclose by Carroll et al. to have a compact and cost effective circuit for controlling multiple phases in a DC-DC power converter to deliver power in high-performance applications in which a load such as a processor consumes substantial power.
Regarding claim 2: Nagasawa disclsoes (i.e. figures 2-8) further comprising: (d) turning OFF, by the responder device (i.e. inactive), a responder channel when a requested load power is below a deactivation threshold (i.e. the load is light) (i.e. 54, 62-67, 86-87, 108-110).
Regarding claim 3: Nagasawa disclsoes (i.e. figures 2-8) further comprising: (d) turning OFF a synchronization signal (i.e. signal CLK during off period), by the requestor device (i.e. POL [2]), on the second pin (i.e. PN10 [2]) when voltage on the first pin (i.e. PN15 [1]) is below a certain threshold (i.e. threshold of CS) (i.e. 54, 62-67, 86-87, 108-110).
Regarding claim 4: Nagasawa disclsoes (i.e. figures 2-8) wherein said (a) pulling down, by the responder device (i.e. POL [1]), the first pin (i.e. PN15 [1]) to a pre-determined voltage level (i.e. voltage of SHR to the voltage level of CS1, output from D1 to pin PN15[1]) when the responder channel (i.e. output channel of POL [1]) of the responder device (i.e. POL [1]) is turned OFF (i.e. inactive) for a first predetermined period of time (i.e. during the inactive time period) (i.e. 54, 62-67, 86-87, 108-110).
Regarding claim 5: Nagasawa disclsoes (i.e. figures 2-8) wherein said (d) turning OFF the synchronization signal (i.e. signal CLK during off period), by the requestor device (i.e. POL [2]), on second the second pin (i.e. PN10 [2]) when voltage on the first pin (i.e. PN15 [1]) is below a certain threshold (i.e. threshold of CS) for a second predetermined period of time (i.e. during the time period when the signal CLK is off) (i.e. 54, 62-67, 86-87, 108-110).
Regarding claim 7: Nagasawa disclsoes (i.e. figures 2-8) wherein said (c) terminating the pulling down, by the responder device (i.e. POL [1]), of the first pin (i.e. PN15 [1]) to the pre-determined voltage level (i.e. voltage of SHR to the voltage level of CS1, output from D1 to pin PN15[1]) after the responder device detects no activity (i.e. during off period of CLK) on the second pin (i.e. PN10 [2] or PN9 [1]) for a first predetermined period of time (i.e. during the inactive time period) (i.e. 54, 62-67, 86-87, 108-110).
Regarding claim 9: Nagasawa disclsoes (i.e. figures 2-8) wherein the first pin (i.e. PN15 [1])is a pin for sharing a compensation voltage (i.e. voltage of SHR) and the second pin (i.e. PN10 [2] or PN9 [1]) is a pin to synchronize other device operation with a clock signal (i.e. signal CLK) (i.e. 54, 62-67, 86-87, 108-110).
Regarding claim 10: Nagasawa disclsoes (i.e. figures 2-8) wherein the responder device is included in a multiphase boost converter controller (i.e. controller of figure 2).
Regarding claim 11: Nagasawa disclsoes (i.e. figures 2-8) wherein the responder device is included in a multiphase buck converter controller (i.e. ¶ 4).
Regarding claim 12: Nagasawa disclsoes said (a) pulling down, by a responder device (i.e. POL [1]) having a responder channel (i.e. output channel of POL [1]), a first pin (i.e. PN15 [1]) to a pre-determined voltage level (i.e. voltage of SHR to the voltage level of CS1, output from D1 to pin PN15[1]) when the responder channel of the responder device (i.e. PN15 [1]) are turned OFF (i.e. inactive) (i.e. 54, 62-67, 86-87, 108-110),
but does not specifically disclose a responder device having at least two responder channels when all responder channels of the responder device are turned OFF.
Carroll et al. disclose a power supply (i.e. figure 1) comprising a responder device having at least two responder channels (i.e. phase A and B).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagasawa’s invention with the power supply as disclose by Carroll et al. in order to have all responder channels of the responder device are turned OFF, because it provide a compact and cost effective circuit for controlling multiple phases in a DC-DC power converter to deliver power in high-performance applications in which a load such as a processor consumes substantial power.
Regarding claim 15: Nagasawa disclsoes said (a) pulling down, by the responder device (i.e. POL [1]), the first pin (i.e. PN15 [1]) to a pre-determined voltage level (i.e. voltage of SHR to the voltage level of CS1, output from D1 to pin PN15[1]) when the responder channel of the responder device (i.e. POL [1]) are turned OFF (i.e. inactive) for a first predetermined period of time (i.e. during the inactive time period) (i.e. 54, 62-67, 86-87, 108-110),
but does not specifically disclose said all the responder channels of the responder device.
Carroll et al. disclose a power supply (i.e. figure 1) comprising a responder device having at least two responder channels (i.e. phase A and B).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Nagasawa’s invention with the power supply as disclose by Carroll et al. in order to have when all the responder channels of the responder device are turned OFF, because it provide a compact and cost effective circuit for controlling multiple phases in a DC-DC power converter to deliver power in high-performance applications in which a load such as a processor consumes substantial power.
Allowable Subject Matter
11. Claims 27-44 are allowed.
The following is an examiner’s statement of reasons for allowance: In regards to claim 27, the prior art fails to disclose (d) generating a synchronization signal, by the requestor device, on a second pin when a load power demand reaches a reactivation threshold; and (e) turning ON a responder channel, by the responder device, when the responder device detects the synchronization signal on the second pin.
12. Claims 6, 8, and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/Primary Examiner, Art Unit 2838
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