DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the low-side pre-driver includes a third high-side transistor and a fourth high-side transistor" in lines 10-11. The claim, as written, lacks clarity as it relates the low-side pre-driver to additional high-side transistors. For examination purposes, examiner has interpreted “the low-side pre-driver includes a third high-side transistor and a fourth high-side transistor” to read “the low-side pre-driver includes a first low-side transistor and a second low-side transistor”.
By virtue of their dependency on claim 1, claims 2-9 are also rejected.
Election/Restrictions
Applicant’s election without traverse of Group 1 (claims 1-9) in the reply filed on 09/17/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 & 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Niikura (US 2022/0200581 A1).
Regarding claim 1, as best understood based on the 35 U.S.C. 112(b) rejection made above, Niikura discloses, in figure 1, 2, & 6, a gate drive circuit configured to drive a half bridge in which a high-side transistor to be driven and a low-side transistor to be driven are connected in series between a power supply voltage and a ground potential (high-side transistor MH and low-side transistor ML between a voltage source and GND), the gate drive circuit comprising:
a high-side pre-driver configured to drive a gate of the high-side transistor to be driven (Para [0057], “high-side driver 402”); and
a low-side pre-driver configured to drive a gate of the low-side transistor to be driven (Para [0057], “low-side driver 404”),
wherein the high-side pre-driver includes a first high-side transistor and a second high-side transistor (MP1 and MP2 of high-side driver 402),
the low-side pre-driver includes a first low-side transistor and a second low-side transistor (MP1 and MP2 of low-side driver 404) and
a delay is provided in at least one of (see figure 2 showing delays between turn-on gate signals)
a time period between a first gate signal configured to turn on the first high-side transistor and a second gate signal configured to turn on the second high-side transistor (time period ϕ.sub.3 and ϕ.sub.4 between first turn-on signal V.sub.PG1 to transistor MP1 and the turn-on signal V.sub.PG2 to transistor MP2 of the high-side driver 402) and
a time period between a third gate signal configured to turn on the first low-side transistor and a fourth gate signal configured to turn on the second low-side transistor (Para [0059], “high-side driver 402 and the low-side driver 404 each have the same configuration as that of the resonant gate driver circuit 200 described above”…same time period between turn-on signals to respective transistors).
Regarding claim 2, Niikura discloses the gate drive circuit according to claim 1, and continues to disclose, in figures 1, 2, & 6, wherein the high-side pre-driver includes a high-side drive unit configured to generate the first gate signal and the second gate signal based on a high-side control input signal (drive unit 206 generates first and second gate signals based on the high-side control input signal H.sub.IN).
Regarding claim 5, Niikura discloses the gate drive circuit according to claim 1, and continues to disclose, in figures 1, 2, & 6, wherein the low-side pre-driver includes a low-side drive unit configured to generate the third gate signal and the fourth gate signal based on a low-side control input signal (drive unit 206 generates third and fourth gate signals based on the low-side control input signal L.sub.IN).
Allowable Subject Matter
Claims 3-4 & 6-9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sugie (US 12,556,082 B2) [Figure 2. Discloses An output node of a high-side driver circuit is coupled to the gate of a high-side transistor. The high-side driver circuit is structured to operate in a first mode in which the high-side driver circuit outputs a driving current with a first current amount during a first period from the transition of a high-side control signal HGCTL from the off level to the on level, and outputs the driving current with a second current amount that is smaller than the first current amount during a second period subsequent to the first period.]
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/TYLER J PERENY/ Examiner, Art Unit 2836
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