Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the arguments filed on 01/21/2026. Claims 1, 3-20 are pending. Claim 2 is cancelled
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4 and 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al. (US 20040240288 A1) in view of SHIMANO et al. (US 20120113731 A1) hereinafter Takahashi and SHIMANO.
Regarding claim 1, Takahashi teaches A register file operator, comprising: a memory cell array, the memory cell array comprising: plural subarrays configured to perform an operation between data stored in memory cells and input data, (see Fig 1, paragraph [0037], illustrates a memory system or register file operator having plurality of subarrays 100.sub.x used for operation of input data for memory cells)
the plural subarrays each comprising: two read ports configured to read data as received data; and a write port configured to write data as written data; and (see Fig 1, paragraph [0037], illustrates each subarray 100.sub.x have 2 ports read port and write port)
Takahashi teaches read and write operations in memory cells with operation circuit. However, Takahashi does not explicitly teach an operation circuit configured to output one or more of operation results of the memory cell array and pieces of the received data read through the two read ports
wherein the register file operator is configured to simultaneously, in one clock cycle, perform a read operation on different addresses of the memory cell array and a write operation on a random address of the memory cell array
On the other hand, SHIMANO which also relates to read and write operations in memory cells with operation circuit teaches an operation circuit configured to output one or more of operation results of the memory cell array and pieces of the received data read through the two read ports. (see Fig 6, paragraph [0281], illustrates a configuration of sub-array block with two read ports RPRTA and RPRTB and write ports WPRTA and WPRTB respectively for data read and writes)
wherein the register file operator is configured to simultaneously, in one clock cycle, perform a read operation on different addresses of the memory cell array and a write operation on a random address of the memory cell array (see Fig 24, 44 and 45, paragraph [0395] and [0560], illustrates data can concurrently be written and read to the different entries in same clock cycle. In other words, read operation at different addresses and write operation can be done simultaneously in same clock cycle)
Both Takahashi and SHIMANO relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, and see SHIMANO, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi with SHIMANO by incorporating read and write operations in memory cells with operation circuit, as taught by SHIMANO, to illustrate a configuration of sub-array block with two read ports RPRTA and RPRTB and write ports WPRTA and WPRTB respectively for data read and writes and where read operation at different addresses and write operation can be done simultaneously in same clock cycle. The combined system of Takahashi – SHIMANO allows operation performance close to hardware to be achieved by massive parallel operation as mentioned in paragraph [0011]. Therefore, the combination of Takahashi - SHIMANO improves high-performance operation processing. See SHIMANO, paragraph [0012].
Regarding claim 3, Takahashi in view of Lee teaches read and write operations in memory cells with operation circuit in claim 2. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 2, wherein the register file operator is further configured to: perform the read operation on a rising edge of a clock cycle; and perform the write operation on a falling edge of the clock cycle
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 2, wherein the register file operator is further configured to: perform the read operation on a rising edge of a clock cycle; and perform the write operation on a falling edge of the clock cycle. (see Fig 2, paragraph [0062] and [0065], illustrates both rising and falling edges of the clock signal CLK are used for concurrent read and write commands with data input DIN and address ADD in same in half clock cycle)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 3.
Regarding claim 4, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 3. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 3, wherein the register file operator is further configured to: read the pieces of received data from two different addresses of the memory cell array through the two read ports on the rising edge of the clock cycle, and write the written data in the memory cell array through the write port on the falling edge of the clock
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 3, wherein the register file operator is further configured to: read the pieces of received data from two different addresses of the memory cell array through the two read ports on the rising edge of the clock cycle, and write the written data in the memory cell array through the write port on the falling edge of the clock. (see Fig 2, paragraph [0062] and [0063], illustrates multiple addresses of read and write operations are executed concurrently in same cycle using rising and falling edges)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 4.
Regarding claim 8, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 1. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 1, wherein each of the subarrays comprises: a write word line, a first read word line, and a second read word line, which are word lines in a row direction; and a write bit line, a first read bit line, and a second read bit line, which are bit lines in a column direction
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 1, wherein each of the subarrays comprises: a write word line, a first read word line, and a second read word line, which are word lines in a row direction; and a write bit line, a first read bit line, and a second read bit line, which are bit lines in a column direction. (see Fig 5, paragraph [0071] and [0072], illustrates world lines XR1 and XW1 for read and write system while bit lines B1® B2® for read system and B1(W) B2(W) for write system)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 8.
Regarding claim 9, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 8. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 8, wherein the write word line is used for access for a write operation for the memory cells and is connected to the write bit line to gate a first switch configured to determine whether to write the written data in the memory cells
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 8, wherein the write word line is used for access for a write operation for the memory cells and is connected to the write bit line to gate a first switch configured to determine whether to write the written data in the memory cells. (see Fig 5, paragraph [0072], illustrates Y switches 103.sub.1 to 103.sub.4 are used for the write-system port and the write bus, and are controlled to be turned on and off by column selection signals YW supplied to their respective gate terminals)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 9.
Regarding claim 10, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 8. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 8, wherein the second read bit line is used for access for a read operation for the memory cells and is connected to the second read bit line to gate a second switch configured to determine whether to read the data stored in the memory cells
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 8, wherein the second read bit line is used for access for a read operation for the memory cells and is connected to the second read bit line to gate a second switch configured to determine whether to read the data stored in the memory cells. (see Fig 5, paragraph [0072], illustrates Y switches are controlled to be turned on and off by column selection signals YR1 to YR4 supplied to their respective gate terminals for the read-system port respectively)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 10.
Regarding claim 11, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 8. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 8, wherein the register file operator is further configured to determine a write target subarray in which written data is to be written among the subarrays by selecting the write word line of each of the subarrays
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 8, wherein the register file operator is further configured to determine a write target subarray in which written data is to be written among the subarrays by selecting the write word line of each of the subarrays. (see Fig 5, paragraph [0074], illustrates Y switches for subarray 103.sub.1 to 103.sub.4 for the write-system port are connected for the write-system port and the write bus and are controlled to be turned on and off by column selection signals YW supplied to their respective gate terminals)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 11.
Regarding claim 12, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 8. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 8, wherein the register file operator is further configured to determine a read target subarray by inputting a second logic value to other first read word lines of other subarrays excluding the read target subarray in which the data is to be read among the subarrays
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 8, wherein the register file operator is further configured to determine a read target subarray by inputting a second logic value to other first read word lines of other subarrays excluding the read target subarray in which the data is to be read among the subarrays. (see Fig 7, paragraph [0076], illustrates selected or targeted word lines are turned ON or in a logic value and unselected word lines are turned OFF or different logic value)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 12.
Regarding claim 13, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 8. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 8, wherein the register file operator is further configured to: access memory cells of a write target subarray in which written data is to be written among the subarrays by applying a first logic value to the write word line,
select a write target memory cell by applying the first logic value to a first write selection line corresponding to the write target memory cell in which the written data is to be written among the memory cells, and
write the written data in the write target memory cell by relaying the written data input through the write bit line to the first write selection line through a local write bit line connected to a first switch
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 8, wherein the register file operator is further configured to: access memory cells of a write target subarray in which written data is to be written among the subarrays by applying a first logic value to the write word line,
select a write target memory cell by applying the first logic value to a first write selection line corresponding to the write target memory cell in which the written data is to be written among the memory cells, and (see Fig 7, paragraph [0076], illustrates selected word line is turned on or activated for write system with first logic value high)
write the written data in the write target memory cell by relaying the written data input through the write bit line to the first write selection line through a local write bit line connected to a first switch. (see Fig 7, paragraph [0076], illustrates selected bit line is made high for the write bus is thru Y switch)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 13.
Regarding claim 14, Regarding claim 13, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 8. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 8, wherein the register file operator is further configured to: access memory cells of a read target subarray from which the received data is to be read among the subarrays by applying a first logic value to the second read word line,
select a read target memory cell by applying the first logic value to a first read select line corresponding to the read target memory cell in which the received data is to be read among memory cells of the read target subarray, and
read the received data stored in the read target memory cell through the second read bit line connected to a read bit line
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 8, wherein the register file operator is further configured to: access memory cells of a read target subarray from which the received data is to be read among the subarrays by applying a first logic value to the second read word line,
select a read target memory cell by applying the first logic value to a first read select line corresponding to the read target memory cell in which the received data is to be read among memory cells of the read target subarray, and (see Fig 7, paragraph [0076], illustrates selected word line is turned on or activated for read system with first logic value high)
read the received data stored in the read target memory cell through the second read bit line connected to a read bit line. (see Fig 7, paragraph [0076], illustrates selected bit line is made high for the read bus is thru Y switch)
The same motivation that was utilized for combining Takahashi and SHIMANO as set forth in claim 1 is equally applicable to claim 14.
Claim(s) 5-6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of SHIMANO and further in view of Lee et al. (US 20220244916 A1) hereinafter Lee.
Regarding claim 5, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 1. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 1, wherein the subarrays further comprise: the memory cells, the memory cells being configured to store the data and comprising static random access memory (SRAM) cells
a multiplier configured to perform a multiplication operation between the written data stored in the memory cells and the input data
On the other hand, Lee which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 1, wherein the subarrays further comprise: the memory cells, the memory cells being configured to store the data and comprising static random access memory (SRAM) cells; (see Fig 1, paragraph [0032], illustrates memory cell 112 includes SRAM 6T cells to store data)
a multiplier configured to perform a multiplication operation between the written data stored in the memory cells and the input data; (see Fig 1, paragraph [0036], illustrates multiplier circuit 114 implemented by NOR gates is used to perform multiplication operation of input data)
Takahashi in view of SHIMANO and further in view of Lee teaches read and write operations in memory cells with operation circuit above. However, Takahashi - SHIMANO - Lee combination does not explicitly teach a first switch configured to determine whether to write the written data stored in the memory cells; and a second switch configured to determine whether to read the received data stored in the memory cells
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches a first switch configured to determine whether to write the written data stored in the memory cells; and a second switch configured to determine whether to read the received data stored in the memory cells. (see Fig 5, paragraph [0072], illustrates Y switches (NMOS transistors) are used for read and write system ports to control read and write operations of memory cells)
Both Takahashi, SHIMANO and Lee relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, and see SHIMANO, abstract, and see Lee, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi – SHIMANO combination with Lee by incorporating read and write operations in memory cells with operation circuit, as taught by Lee, to illustrate memory cell 112 includes SRAM 6T cells to store data and multiplier circuit 114 implemented by NOR gates is used to perform multiplication operation of input data. The combined system of Takahashi – SHIMANO- Lee allows data to be analyzed in real time, enabling faster reporting and decision-making in business and machine learning applications as mentioned in paragraph [0002]. Therefore, the combination of Takahashi - SHIMANO - Lee improves the performance of compute-in-memory systems. See Lee, paragraph [0002].
Regarding claim 6, Takahashi in view of SHIMANO and further in view of Lee teaches read and write operations in memory cells with operation circuit in claim 1. However, Takahashi - SHIMANO - Lee combination does not explicitly teach The register file operator of claim 1, wherein the operation circuit comprises: an adder tree configured to sum the operation results of the memory cell array and read first received data among the pieces of received data
an accumulator configured to perform a shift operation and an accumulation operation on the summed results of the adder tree; and
a buffer configured to store second received data such that the first received data output through the accumulator among the pieces of received data is output simultaneously with the second received data of the memory cells relayed through a second read bit line
On the other hand, Lee which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 1, wherein the operation circuit comprises: an adder tree configured to sum the operation results of the memory cell array and read first received data among the pieces of received data; (see Fig 1, paragraph [0035], illustrates adder circuit 116 is used to add or sum output data of logic circuits 114)
an accumulator configured to perform a shift operation and an accumulation operation on the summed results of the adder tree; and (see Fig 8, paragraph [0045], illustrates accumulator 124 which includes a partial sum adder and shifter receives sum data from adder circuit)
a buffer configured to store second received data such that the first received data output through the accumulator among the pieces of received data is output simultaneously with the second received data of the memory cells relayed through a second read bit line. (see Fig 9, paragraph [0051] and [0055], illustrates output register 330 which works as buffer receives outputs from adder and accumulator circuits where first and second data are received and executed in adder and output register at the same time)
Both Takahashi, SHIMANO and Lee relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, and see SHIMANO, abstract, and see Lee, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi – SHIMANO combination with Lee by incorporating read and write operations in memory cells with operation circuit, as taught by Lee, to illustrate adder circuit 116 is used to add or sum output data of logic circuits 114 and accumulator 124 which includes a partial sum adder and shifter receives sum data from adder circuit and output register 330 which works as buffer receives outputs from adder and accumulator circuits where first and second data are received and executed in adder and output register at the same time. The combined system of Takahashi – SHIMANO- Lee allows data to be analyzed in real time, enabling faster reporting and decision-making in business and machine learning applications as mentioned in paragraph [0002]. Therefore, the combination of Takahashi - SHIMANO - Lee improves the performance of compute-in-memory systems. See Lee, paragraph [0002].
Regarding claim 15, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 1. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 1, wherein the register file operator is configured to perform a multiplication operation in a multiplier of each of the subarrays by applying the input data to a first read word line of the subarrays and applying a second logic value to all second read word line of the subarrays
On the other hand, Lee which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 1, wherein the register file operator is configured to perform a multiplication operation in a multiplier of each of the subarrays by applying the input data to a first read word line of the subarrays and applying a second logic value to all second read word line of the subarrays. (see Fig 1, paragraph [0037] and [0038], illustrates a multiplier circuit 114 is used to multiply 2 different logic value input to the memory array 110)
Both Takahashi, SHIMANO and Lee relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, and see SHIMANO, abstract, and see Lee, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi – SHIMANO combination with Lee by incorporating read and write operations in memory cells with operation circuit, as taught by Lee, to illustrate a multiplier circuit 114 is used to multiply 2 different logic value input to the memory array 110. The combined system of Takahashi – SHIMANO- Lee allows data to be analyzed in real time, enabling faster reporting and decision-making in business and machine learning applications as mentioned in paragraph [0002]. Therefore, the combination of Takahashi - SHIMANO - Lee improves the performance of compute-in-memory systems. See Lee, paragraph [0002].
Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of Lee and further in view of SHIMANO.
Regarding claim 19, Takahashi teaches A method, the method comprising: accessing memory cells of a read target subarray from which received data is to be read among subarrays comprised in a memory cell array of a register file operator; (see Fig 1, paragraph [0037], illustrates plurality of subarrays 100.sub.0 to 100.sub.n of memory cell array to be used to read data)
selecting a read target memory cell from which the received data is to be read from among memory cells of the read target subarray; (see Fig 1, paragraph [0037], illustrates a target subarray with a read address is selected for read data thru read bus)
reading the received data stored in the read target memory cell; (see Fig 1, paragraph [0041], illustrates read/write control circuit 120 controls the read data output from output terminal DOUT)
Takahashi teaches read and write operations in memory cells with operation circuit. However, Takahashi does not explicitly teach performing a multiplication operation between the received data and input data in each of the subarrays; and
summing results of the multiplication operation and performing and outputting a shift operation and an accumulation operation on the summed results.
On the other hand, Lee which also relates to read and write operations in memory cells with operation circuit teaches performing a multiplication operation between the received data and input data in each of the subarrays; and (see Fig 1, paragraph [0036], illustrates multiplier circuit 114 implemented by NOR gates is used to perform multiplication operation of input data)
summing results of the multiplication operation and performing and outputting a shift operation and an accumulation operation on the summed results. (see Fig 8, paragraph [0045], illustrates accumulator 124 which includes a partial sum adder and shifter receives sum data from adder circuit)
Both Takahashi and Lee relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, and see Lee, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi with Lee by incorporating read and write operations in memory cells with operation circuit, as taught by Lee, to enable multiplier circuit implemented by NOR gates is used to perform multiplication operation of input data and accumulator which includes a partial sum adder and shifter receives sum data from adder circuit. The combined system of Takahashi – Lee allows data to be analyzed in real time, enabling faster reporting and decision-making in business and machine learning applications as mentioned in paragraph [0002]. Therefore, the combination of Takahashi - Lee improves the performance of compute-in-memory systems. See Lee, paragraph [0002].
Takahashi in view of Lee teaches read and write operations in memory cells with operation circuit. However, Takahashi - Lee combination does not explicitly teach
wherein the register file operator is configured to simultaneously, in ore clock cycle, perform a read operation on different addresses of the memory cell array and a write operation on a random address of the memory cell array
On the other hand, SHIMANO which also relates to read and write operations in memory cells with operation circuit teaches wherein the register file operator is configured to simultaneously, in ore clock cycle, perform a read operation on different addresses of the memory cell array and a write operation on a random address of the memory cell array (see Fig 24, 44 and 45, paragraph [0395] and [0560], illustrates data can concurrently be written and read to the different entries in same clock cycle. In other words, read operation at different addresses and write operation can be done simultaneously in same clock cycle)
Both Takahashi, Lee and SHIMANO relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, see Lee, abstract, and see SHIMANO, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi - Lee combination with SHIMANO by incorporating read and write operations in memory cells with operation circuit, as taught by SHIMANO, to illustrate a configuration of sub-array block with two read ports RPRTA and RPRTB and write ports WPRTA and WPRTB respectively for data read and writes and where read operation at different addresses and write operation can be done simultaneously in same clock cycle. The combined system of Takahashi - Lee – SHIMANO allows operation performance close to hardware to be achieved by massive parallel operation as mentioned in paragraph [0011]. Therefore, the combination of Takahashi - Lee - SHIMANO improves high-performance operation processing. See SHIMANO, paragraph [0012].
Regarding claim 20, Takahashi in view of Lee and further in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 19. However, Takahashi - Lee - SHIMANO combination does not explicitly teach The method of claim 19, further comprising: accessing memory cells of a write target subarray in which written data is to be written among the subarrays
selecting a write target memory cell in which the written data is to be written from among the memory cells; and
writing the written data in the write target memory cell
On the other hand, Takahashi which also relates to read and write operations in memory cells with operation circuit teaches The method of claim 19, further comprising: accessing memory cells of a write target subarray in which written data is to be written among the subarrays; (see Fig 1, paragraph [0037], illustrates plurality of subarrays 100.sub.0 to 100.sub.n of memory cell array to be used to write data)
selecting a write target memory cell in which the written data is to be written from among the memory cells; and (see Fig 1, paragraph [0037], illustrates a target subarray with a write address is selected for write data thru write bus)
writing the written data in the write target memory cell. (see Fig 1, paragraph [0041], illustrates read/write control circuit 120 controls the write data input from data input terminal DIN)
The same motivation that was utilized for combining Takahashi - Lee combination and in as set forth in claim 19 is equally applicable to claim 20.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of SHIMANO and further in view of Lee and further in view of PATIL et al. (US 20210327495 A1) hereinafter PATIL.
Regarding claim 7, Takahashi in view of SHIMANO and further in view of Lee teaches read and write operations in memory cells with operation circuit in claim 6. However, Takahashi - SHIMANO - Lee combination does not explicitly teach The register file operator of claim 6, wherein the register file operator is further configured to simultaneously perform, in different subarrays, a first read operation on the first received data using the adder tree and a second read operation on the second received data using the second read bit line
On the other hand, PATIL which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 6, wherein the register file operator is further configured to simultaneously perform, in different subarrays, a first read operation on the first received data using the adder tree and a second read operation on the second received data using the second read bit line. (see Fig 1, paragraph [0027], illustrates two words can be read at the same time and circuit 100 allows two read operations to be operated independently at the same time)
Both Takahashi, SHIMANO, Lee and PATIL relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, see SHIMANO, abstract, see Lee, abstract, and see PATIL, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi - SHIMANO - Lee combination with PATIL by incorporating read and write operations in memory cells with operation circuit, as taught by PATIL, to enable two words which can be read at the same time and circuit 100 allows two read operations to be operated independently at the same time. The combined system of Takahashi - SHIMANO - Lee – PATIL allows performing a read operation of a first word and a second word in parallel in a static random access memory (SRAM) as mentioned in paragraph [0008]. Therefore, the combination of Takahashi - SHIMANO - Lee - PATIL improves the performance. See PATIL, paragraph [0008].
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of SHIMANO and further in view of PATIL et al. (US 20210327495 A1) hereinafter PATIL.
Regarding claim 16, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 1. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 1, wherein the register file operator comprises the subarrays arranged in a plurality of columns, and wherein the register file operator is configured to share a first read bit line, a second read bit line, and a write bit line in a same column of the plurality of columns and a first read word line, a second read word line, and a write word line among the plurality of columns
On the other hand, PATIL which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 1, wherein the register file operator comprises the subarrays arranged in a plurality of columns, and wherein the register file operator is configured to share a first read bit line, a second read bit line, and a write bit line in a same column of the plurality of columns and a first read word line, a second read word line, and a write word line among the plurality of columns. (see Fig 1, paragraph [0023] and [0025], illustrates multiple WLs both read and write system in the array are configured to share same BL of column)
Both Takahashi, SHIMANO and PATIL relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, see SHIMANO, abstract, and see PATIL, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi - SHIMANO combination with PATIL by incorporating read and write operations in memory cells with operation circuit, as taught by PATIL, to enable multiple WLs both read and write system in the array to be configured to share same BL of column. The combined system of Takahashi - SHIMANO – PATIL allows performing a read operation of a first word and a second word in parallel in a static random access memory (SRAM) as mentioned in paragraph [0008]. Therefore, the combination of Takahashi - SHIMANO - PATIL improves the performance. See PATIL, paragraph [0008].
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of SHIMANO and further in view of CHEN et al. (US 20190065151 A1) hereinafter Takahashi and CHEN.
Regarding claim 17, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 1. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 1, wherein the register file operator is configured to perform an operation of one of a multiply-accumulate (MAC) operation, a vector-matrix multiplication (VMM) operation, and a matrix-matrix multiplication (MMM) operation
On the other hand, CHEN which also relates to read and write operations in memory cells with operation circuit teaches The register file operator of claim 1, wherein the register file operator is configured to perform an operation of one of a multiply-accumulate (MAC) operation, a vector-matrix multiplication (VMM) operation, and a matrix-matrix multiplication (MMM) operation. (see Fig 1, paragraph [0024] and [0027], illustrates Multiply and Accumulate (MAC) units 104 and a memory 102 to store a weight matrix W, a column vector X, and a column vector Y used to compute multiplication)
Both Takahashi, SHIMANO and CHEN relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, see SHIMANO, abstract, and see CHEN, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi - SHIMANO combination with CHEN by incorporating read and write operations in memory cells with operation circuit, as taught by CHEN, to enable Multiply and Accumulate (MAC) units and a memory to store a weight matrix W, a column vector X, and a column vector Y used to compute multiplication. The combined system of Takahashi - SHIMANO – CHEN allows sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device as mentioned in paragraph [0019]. Therefore, the combination of Takahashi - SHIMANO - CHEN improves bit precision of the result. See CHEN, paragraph [0040].
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of SHIMANO and further in view of Lea et al. (US 20200150864 A1) hereinafter Takahashi and Lea.
Regarding claim 18, Takahashi in view of SHIMANO teaches read and write operations in memory cells with operation circuit in claim 1. However, Takahashi - SHIMANO combination does not explicitly teach The register file operator of claim 1, wherein the subarrays comprise one of four SRAM memory cells, eight SRAM memory cells, and thirty-two SRAM memory cells
On the other hand, Lea which also relates to read and write operations in memory cells with operation circuit teaches The The register file operator of claim 1, wherein the subarrays comprise one of four SRAM memory cells, eight SRAM memory cells, and thirty-two SRAM memory cells. (see Fig 1B, paragraph [0060] and [0061], illustrates subarrays may include SRAMs in various numbers of rows)
Both Takahashi, SHIMANO and Lea relate read and write operations in memory cells with operation circuit (see Takahashi, abstract, see SHIMANO, abstract, and see Lea, abstract, regarding command queue management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Takahashi - SHIMANO combination with Lea by incorporating read and write operations in memory cells with operation circuit, as taught by Lea, to enable subarrays to include SRAMs in various numbers of rows. The combined system of Takahashi - SHIMANO – Lea allows including random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others as mentioned in paragraph [0003] performance. Therefore, the combination of Takahashi - SHIMANO - Lea improves bit precision of the result. See Lea, paragraph [0006].
Response to Arguments
Applicant’s arguments filed on 01/21/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claim 1 amendment mapping by
primary reference Takahashi and secondary reference Lee in page 8-13 of the response: Takahashi is describing a memory cell with subarrays using only a read port and a write port while, external from the subarrays, a switching device handles cache hit/misses. Furthermore, in the cited portion of Takahashi, the cell core array is configured to perform read and/or write operations in half-cycles of the clock signal. In addition, during the write operation, data is written to the subarray and the cache memory simultaneously. Therefore, the cited portions of Takahashi further fail to teach or suggest "read the pieces of received data from two different addresses of the memory cell array through the two read ports on the rising edge of the clock cycle," and "write the written data in the memory cell array through the write port on the falling edge of the clock," as recited in claim 4 because Takahashi is not reading, by its subarrays, two pieces of data from two different addresses of the memory cell based on the rising edge of a clock cycle….
both Takahashi and Lee are not capable of being readily combined in a predicable manner to yield predictable results, nor are they capable of being a "simple substitution" for each other, and instead, the more complex the technologies are, the Office has stated that there is less of a predictability of success and therefore the outcomes of such combinations would not be predictable, leading to unexpected results, showing the combination to be nonobvious
In summary, applicant argued that primary reference Takahashi and secondary
reference Lee do not teach amended limitations subarray having two read ports and multiple addresses of read and write operations are executed concurrently in same clock cycle. The amendment necessitates adding another secondary reference SHIMANO in this regard. For further clarification examiner cites portion from SHIMANO. Also, for applicant’s understanding examiner would like to explain the teachings of SHIMANO and examiner’s interpretation in more detail here. See Fig 6, paragraph [0281], SHIMANO teaches a configuration of sub-array block with two read ports RPRTA and RPRTB and write ports WPRTA and WPRTB respectively for data read and writes. See Fig 24, 44 and 45, paragraph [0395] and [0560], SHIMANO teaches data can concurrently be written and read to the different entries in same clock cycle. In other words, read operation at different addresses and write operation can be done simultaneously in same clock cycle. The cited portions along with figures clearly teaches subarray block may have two read ports and write ports and also read operation at different addresses and write operation can be done simultaneously in same clock cycle. Thus, the rejection of amended independent claims 1 and 19 is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132