DETAILED ACTION
This application has been examined. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Making Final
Applicant's arguments filed 5/11/2026 have been fully considered but they are moot in view of the new grounds for rejection.
The claim amendments regarding -- ‘wherein updating the second ring buffer comprises transferring the first pointer from the first ring buffer to the second ring buffer and removing the first pointer from the first ring buffer’ -- clearly change the literal scope of the independent and dependent claims and/or the range of equivalents for such claims. The said amendments alter the scope of the claims but do not overcome the disclosure by the prior art as shown below.
The Examiner is presenting new grounds for rejection as necessitated by the claim amendments and is thus making this action FINAL.
Response to Arguments
Applicant's arguments filed 5/11/2026 have been fully considered but they are moot in view of the new grounds for rejection.
Singhal-Go disclosed (re. Claim 1) wherein updating the second ring buffer comprises transferring the first pointer from the first ring buffer to the second ring buffer (Go-Paragraph 121, The copy descriptor 210 may be the format of descriptors used by the Tx control circuit 56 for copy DMA transfers (from one memory region in the host 12 to another memory region in the host 12) using the copy FIFO 42. Thus, the copy descriptor 210 may be used in the descriptor rings 112A-112N that correspond to Tx DMA channels assigned to the copy FIFO 42.)
While Singhal-Go substantially disclosed the claimed invention Singhal-Go does not disclose (re. Claim 1) removing the first pointer from the first ring buffer
Oikawa Paragraph 69 disclosed wherein when the execution of a command is completed, pointers corresponding to the command, execution of which is completed, are deleted (invalidated) from the pointer buffer 41. However, the pointers may be deleted from the pointer buffer 41 when data transfer corresponding to the pointers is completed.
Oikawa disclosed (re. Claim 1) ‘removing the first pointer from the first ring buffer’ (Oikawa-Paragraph 69,Paragraph 70, when the execution of a command is completed, pointers corresponding to the command, execution of which is completed, are deleted (invalidated) from the pointer buffer 41. However, the pointers may be deleted from the pointer buffer 41 when data transfer corresponding to the pointers is completed.)
Singhal,Go and Oikawa are analogous art because they present concepts and practices regarding buffer management. Before the time of the effective filing date of the claimed invention it would have been obvious to combine Oikawa into Singhal-Go. The motivation for the said combination would have been to enable wherein a memory capacity for pointer buffer can be reduced, compared with a case where the storage device tries acquiring all of pointers corresponding to a command.(Oikawa-Paragraph 65)
Priority
The effective date of the claims described in this application is November 7, 2024.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,5-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singhal (USPGPUB 20250013386) further in view of Go (USPGPUB 20110314186) further in view of Oikawa (USPGPUB 2015/0254022)
Regarding Claim 1
Singhal Paragraph 14 disclosed wherein a computer node is able to remotely access a persistent memory of a memory server in the FAM using Remote Direct Memory Access (RDMA) over a network. In other examples, a FAM can include a volatile memory or a combination of persistent memory and volatile memory. An RDMA data transfer between a computer node and a memory server includes a transfer of data between the computer node and the persistent memory of the memory server over the network.
Singhal Paragraph 61 disclosed wherein FAM client 330 acquires a collection of buffers for memory servers that are part of a given memory address space. In some examples, the computer node 302 can use multiple memory address spaces, which may be for different use cases, for example. Each memory address space may include a different collection of memory servers. Depending on which memory address space is used, a different collection of buffers can be acquired by the FAM client 330. The collection of buffers is acquired from a pre-allocated buffer pool that includes buffers for all memory servers of a FAM (e.g., the FAM 106 in FIG. 1).
Singhal disclosed (re. Claim 1) a system, comprising: a remote direct memory access (RDMA) memory device (Singhal- Figure 1, Figure 3, Paragraph 59, PE 318 in the computer node 302, Paragraph 61,FAM client 330 ) comprising:
a plurality of memory regions, a first ring buffer comprising a first pointer indicating an address of a first memory region of the plurality of memory regions, (Singhal-Paragraph 65, memory addresses of the buffers 328-1 to 328-M are the addresses in a local memory at which the buffers 328-1 to 328-M are located. The buffer descriptor is a data structure, stored in a memory (e.g., the local memory 116-1 or 116-N of FIG. 1) that can be later accessed (e.g., by the FAM client 330 in response to a request to send queued computations to memory servers) to determine where the buffers 328-1 to 328-M are located in the local memory and what type of operation is to be applied) , and a second ring buffer; (Singhal-Figure 1, Figure 3,Paragraph 61,FAM client 330 acquires a collection of buffers for memory servers that are part of a given memory address space. In some examples, the computer node 302 can use multiple memory address spaces, which may be for different use cases, for example. Each memory address space may include a different collection of memory servers. Depending on which memory address space is used, a different collection of buffers can be acquired by the FAM client 330. ) and
an RDMA network interface controller (NIC) (Singhal-Paragraph 29, computer node 102-1 includes a NIC 117-1, and the computer node 102-N includes a NIC 117-N) that receives, from a first computing device, a write request for writing first data to one of the plurality of memory regions, (Singhal-Paragraph 31, PE can perform computations on data read from the FAM 106 or data to be written to the FAM 106.)
determines, based on the first pointer, the address of the first memory region, writes the first data to the first memory region based on the address of the first memory region, (Singhal-Paragraph 65, memory addresses of the buffers 328-1 to 328-M are the addresses in a local memory at which the buffers 328-1 to 328-M are located. The buffer descriptor is a data structure, stored in a memory (e.g., the local memory 116-1 or 116-N of FIG. 1) that can be later accessed (e.g., by the FAM client 330 in response to a request to send queued computations to memory servers) to determine where the buffers 328-1 to 328-M are located in the local memory and what type of operation is to be applied)
While Singhal substantially disclosed the claimed invention Singhal does not disclose (re. Claim 1) a first ring buffer comprising a first pointer indicating an address of a first memory region the first memory region being empty
While Singhal substantially disclosed the claimed invention Singhal does not disclose (re. Claim 1) updating the second ring buffer to comprise a second pointer indicating the address of the first memory region storing the first data.
Go Figure 5 Paragraph disclosed a set of buffer pointer rings 114A-114M and descriptor rings 112A-112N.
Go Figure 7 Paragraph 86 disclosed wherein as DMA data is received from a given interface, the data may be stored in the buffers allocated to that interface and the buffer pointers may be written to the descriptor for the channel on which the DMA data is received.
Go disclosed (re. Claim 1) a first ring buffer (Go-Figure 5 Paragraph 85,set of buffer pointer rings 114A-114M ) comprising a first pointer indicating an address of a first memory region the first memory region being empty (Go-Paragraph 94, Rx control circuit 58 may determine if a buffer is already in use to receive the DMA data (decision block 130). A buffer may be in use if it has previously been selected to store the DMA data and is not yet full.)
Go disclosed (re. Claim 1) updating the second ring buffer (Go-Figure 5 Paragraph 85, descriptor rings 112A-112N.)
to comprise a second pointer indicating the address of the first memory region storing the first data. (Go- Figure 7 Paragraph 86,as DMA data is received from a given interface, the data may be stored in the buffers allocated to that interface and the buffer pointers may be written to the descriptor for the channel on which the DMA data is received.)
Singhal and Go are analogous art because they present concepts and practices regarding buffer management. Before the time of the effective filing date of the claimed invention it would have been obvious to combine Go into Singhal. The motivation for the said combination would have been to enable allocating buffers of different sizes based on, e.g., the amount of memory available, the expected size of DMA transfers on a given interface.(Go-Paragraph 87)
Singhal-Go disclosed (re. Claim 1) wherein updating the second ring buffer comprises transferring the first pointer from the first ring buffer to the second ring buffer (Go-Paragraph 121, The copy descriptor 210 may be the format of descriptors used by the Tx control circuit 56 for copy DMA transfers (from one memory region in the host 12 to another memory region in the host 12) using the copy FIFO 42. Thus, the copy descriptor 210 may be used in the descriptor rings 112A-112N that correspond to Tx DMA channels assigned to the copy FIFO 42.)
While Singhal-Go substantially disclosed the claimed invention Singhal-Go does not disclose (re. Claim 1) removing the first pointer from the first ring buffer
Oikawa Paragraph 69 disclosed wherein when the execution of a command is completed, pointers corresponding to the command, execution of which is completed, are deleted (invalidated) from the pointer buffer 41. However, the pointers may be deleted from the pointer buffer 41 when data transfer corresponding to the pointers is completed.
Oikawa disclosed (re. Claim 1) ‘removing the first pointer from the first ring buffer’ (Oikawa-Paragraph 69,Paragraph 70, when the execution of a command is completed, pointers corresponding to the command, execution of which is completed, are deleted (invalidated) from the pointer buffer 41. However, the pointers may be deleted from the pointer buffer 41 when data transfer corresponding to the pointers is completed.)
Singhal,Go and Oikawa are analogous art because they present concepts and practices regarding buffer management. Before the time of the effective filing date of the claimed invention it would have been obvious to combine Oikawa into Singhal-Go. The motivation for the said combination would have been to enable wherein a memory capacity for pointer buffer can be reduced, compared with a case where the storage device tries acquiring all of pointers corresponding to a command.(Oikawa-Paragraph 65)
Regarding Claim 10
Claim 10 (re. method) recites substantially similar claim limitations as Claim 1. Claim 10 is rejected on the same basis as Claim 1.
Regarding Claim 16
Claim 16 (re. device) recites substantially similar claim limitations as Claim 1. Claim 16 is rejected on the same basis as Claim 1.
Regarding Claim 2,12,19
Singhal-Go-Oikawa disclosed (re. Claim 2,12,19) an overflow manager (Singhal-Paragraph 49, If the FAM client 130-1 detects that the buffer exceeds a specified fullness threshold (e.g., more than 75% full, more than 90% full, 100% full, or another threshold value), then the FAM client 130-1 automatically triggers the sending of the queued computations from the buffer to the memory server) that: determines a storage capacity of the plurality of memory regions satisfies a first storage criterion, and transfers the first data from the first memory region to a spill storage device; and the RDMA NIC causes the first ring buffer to comprise a third pointer indicating the address of the first memory region, the first memory region being empty.(Singhal-Paragraph 48, a FAM queue 134-1 into which offloaded computations from any of buffers 128-1 and 129-1 are queued, and the memory server 108-M includes a FAM queue 134-M into which offloaded computations from any of buffers 128-M and 129-M are queued.)
Regarding Claim 3
Singhal-Go-Oikawa disclosed (re. Claim 3) wherein: the overflow manager further: determines the storage capacity of the plurality of memory regions satisfies a second storage criterion,(Singhal-Paragraph 45, FAM client 130-1 detects a quantity of requests in the collection of requests that exceeds a specified quantity threshold, or that the amount of data to be processed for the collection of requests exceeds a specified size threshold, the FAM client 130-1 can automatically trigger the queuing of the computations of the collection of requests to offload to memory servers of the FAM 106,Paragraph 50, memory server can provide an indication of usage of the processor of the memory server to the FAM client 130-1. The indication of usage can be expressed as a percentage used (e.g., 10% used, 40% used, 90% used, or another percentage used value) ) determines, based on the first ring buffer, an address of a second memory region, the second memory region being empty, and transfers the first data from the spill storage device to the second memory region; and the RDMA NIC causes the second ring buffer to comprise a fourth pointer indicating the address of the second memory region storing the first data. (Singhal-Paragraph 48, a FAM queue 134-1 into which offloaded computations from any of buffers 128-1 and 129-1 are queued, and the memory server 108-M includes a FAM queue 134-M into which offloaded computations from any of buffers 128-M and 129-M are queued.)
Regarding Claim 5,13
Singhal-Go-Oikawa disclosed (re. Claim 5,13) wherein to determine, based on the first pointer, the address of the first memory region, the RDMA NIC further: accesses the first ring buffer to obtain the first pointer; and provides the first pointer to the first computing device. (Singhal-Paragraph 65, memory addresses of the buffers 328-1 to 328-M are the addresses in a local memory at which the buffers 328-1 to 328-M are located. The buffer descriptor is a data structure, stored in a memory (e.g., the local memory 116-1 or 116-N of FIG. 1) that can be later accessed (e.g., by the FAM client 330 in response to a request to send queued computations to memory servers) to determine where the buffers 328-1 to 328-M are located in the local memory and what type of operation is to be applied)
Regarding Claim 6,14
Singhal-Go-Oikawa disclosed (re. Claim 6,14,20) wherein to write the first data to the first memory region, the RDMA NIC further: receives, from the first computing device, a write instruction ( Singhal-Paragraph 31, Each PE is able to access data of the FAM 106. The access can include a read access to read data from the FAM 106 or a write access to write data to the FAM 106.) indicating the first data is to be written to the address of the first memory region; (Singhal-Paragraph 55, computer node 202 can store mapping information that maps offsets to memory servers. The operation elements in the requests 1-6 are added to different buffers 228-1 to 228-4 based on offsets of the operation elements) and responsive to receiving the write instruction, writes the first data to the first memory region.(Singhal-Paragraph 31, Each PE is able to access data of the FAM 106. The access can include a read access to read data from the FAM 106 or a write access to write data to the FAM 106.)
Regarding Claim 7,15
Singhal-Go-Oikawa disclosed (re. Claim 7,15) wherein the RDMA NIC further: receives, from a second computing device, a read request for reading the first data; ( Singhal-Paragraph 31, Each PE is able to access data of the FAM 106. The access can include a read access to read data from the FAM 106 or a write access to write data to the FAM 106.) determines, based on the second pointer, the address of the first memory region; (Singhal-Paragraph 55, computer node 202 can store mapping information that maps offsets to memory servers. The operation elements in the requests 1-6 are added to different buffers 228-1 to 228-4 based on offsets of the operation elements) reads the first data from the first memory region based on the address of the first memory region; and provides the first data to the second computing device.( Singhal-Paragraph 31, Each PE is able to access data of the FAM 106. The access can include a read access to read data from the FAM 106 or a write access to write data to the FAM 106.)
Regarding Claim 8
Singhal-Go-Oikawa disclosed (re. Claim 8) wherein the second ring buffer comprises a third pointer indicating an address of a second memory region storing second data, and to determine, based on the second pointer, the address of the first memory region, the RDMA NIC further: accesses the second ring buffer to obtain the second pointer and the third pointer; and provides the second pointer and the third pointer to the second computing device. (Go- Figure 7 Paragraph 86,as DMA data is received from a given interface, the data may be stored in the buffers allocated to that interface and the buffer pointers may be written to the descriptor for the channel on which the DMA data is received.)
Regarding Claim 9
Singhal-Go-Oikawa disclosed (re. Claim 9) wherein the second pointer comprises the first pointer (Go- Figure 7,Paragraph 86,as DMA data is received from a given interface, the data may be stored in the buffers allocated to that interface and the buffer pointers may be written to the descriptor for the channel on which the DMA data is received.)
Regarding Claim 17
Singhal-Go-Oikawa disclosed (re. Claim 17) wherein the first ring buffer comprises a third pointer indicating an address of a second memory region storing second data, and to receive the first pointer from the first ring buffer, the RDMA NIC further: receives the first and third pointer from the first ring buffer. (Go- Figure 7 Paragraph 86,as DMA data is received from a given interface, the data may be stored in the buffers allocated to that interface and the buffer pointers may be written to the descriptor for the channel on which the DMA data is received.)
Regarding Claim 18
Singhal-Go-Oikawa disclosed (re. Claim 18) wherein RDMA NIC further: provides the first pointer and the third pointer to the first computing device; and receives, from the first computing device, a read instruction indicating the first data is to be read from the first memory region. (Singhal-Paragraph 31, Each PE is able to access data of the FAM 106. The access can include a read access to read data from the FAM 106 or a write access to write data to the FAM 106.)
Regarding Claim 20
Singhal-Go-Oikawa disclosed (re. Claim 20) wherein the RDMA NIC further: receives, from a second computing device, a write request for writing second data to the memory device; (Singhal-Paragraph 31, Each PE is able to access data of the FAM 106. The access can include a read access to read data from the FAM 106 or a write access to write data to the FAM 106.) determines, based on the second pointer, the address of the first memory region; writes the second data to the first memory region based on the address of the first memory region; and updates the first ring buffer to comprise a third pointer indicating the address of the first memory region storing the second data. (Go- Figure 7 Paragraph 86,as DMA data is received from a given interface, the data may be stored in the buffers allocated to that interface and the buffer pointers may be written to the descriptor for the channel on which the DMA data is received.)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singhal (USPGPUB 20250013386) further in view of Go (USPGPUB 20110314186) further in view of Oikawa (USPGPUB 2015/0254022) further in view of Cai (US Patent 9397788)
Regarding Claim 4
Singhal-Go-Oikawa disclosed (re. Claim 4) wherein: the first data is associated with a first entity account; the RDMA memory device further comprises: a first ring pair comprising the first ring buffer and the second ring buffer, and a second ring pair comprising a third ring buffer and a fourth ring buffer, the fourth ring buffer comprising fourth pointer indicating an address of a second memory region storing second data associated with a second entity account; and the overflow manager further: prioritizes transferring the first data from the first memory region to the spill storage device over transferring the second data from the second memory region to the spill storage device.
While Singhal-Go-Oikawa substantially disclosed the claimed invention Singhal-Go-Oikawa does not disclose (re. Claim 4) the first data is associated with a first entity account; a second memory region storing second data associated with a second entity account
and the overflow manager further: prioritizes transferring the first data from the first memory region to the spill storage device over transferring the second data from the second memory region to the spill storage device.
Cai Column 7 Lines 35-40 disclosed wherein fast path communication program 200 determines which computing entities (e.g., applications, tenants, virtual machines, clients, etc.) executing within computing node 102 may engage in direct-memory data communications.
Cai Column 10 Lines 25-30 disclosed wherein data management program 300 determines information related to communicated data, such as a size of the data, whether the data is shared (e.g., multiple receiving entities), a priority assigned to the data.
Cai disclosed (re. Claim 4) the first data is associated with a first entity account; a second memory region storing second data associated with a second entity account (Cai Column 7 Lines 35-40, determines which computing entities (e.g., applications, tenants, virtual machines, clients, etc.)
and the overflow manager further: prioritizes transferring the first data from the first memory region to the spill storage device over transferring the second data from the second memory region to the spill storage device.(Cai-Column 10 Lines 25-30, data management program 300 determines a priority assigned to the data,Column 11 Lines 35-40, data management program 300 may utilize information associated with the data (step 302) to determine which buffer contains data of a lower priority. In case of an emergency (e.g., constrained shared memory), a memory buffer associated with a lower priority data and/or process may be purged and the memory buffer assigned to higher priority data.)
Singhal and Cai are analogous art because they present concepts and practices regarding buffer management. Before the time of the effective filing date of the claimed invention it would have been obvious to combine Cai into Singhal-Go. The motivation for the said combination would have been to enable analyzing which OSs and SDKs are associated with the computing entities and whether the OSs and SDKs include APIs and utilities needed to enable a fast path communication solution.(Cai-Column 7 Lines 45-50)
Conclusion
Examiner’s Note: In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GREG C BENGZON whose telephone number is (571)272-3944. The examiner can normally be reached on Monday - Friday 8 AM - 4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Follansbee can be reached on (571) 272-3964. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GREG C BENGZON/ Primary Examiner, Art Unit 2444
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