Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 - 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11, 13 - 26 of U.S. Patent No. 12171058. Although the claims at issue are not identical, they are not patentably distinct from each other because
Regarding claim 1, claim 11 of U.S. Patent No. 12171058 discloses all the limitations of claim 1 in current application except “a first wireless-frequency transceiver located between two of the layers of the multilayer PCB. It is obvious that a component embedded in a multilayer PCB is located between two layers of the multilayer PCB.
Claim 2 is rejected by claim 11 of U.S. Patent No. 12171058.
Claim 3 is rejected by claim 13 of U.S. Patent No. 12171058.
Claim 4 is rejected by claim 14 of U.S. Patent No. 12171058.
Claim 5 is rejected by claim 15 of U.S. Patent No. 12171058.
Claim 6 is rejected by claim 16 of U.S. Patent No. 12171058.
Claim 7 is rejected by claim 17 of U.S. Patent No. 12171058.
Claim 8 is rejected by claim 16 of U.S. Patent No. 12171058.
Claim 9 is rejected by claim 18 of U.S. Patent No. 12171058.
Claim 10 is rejected by claim 19 of U.S. Patent No. 12171058.
Claim 11 is rejected by claim 20 of U.S. Patent No. 12171058.
Claim 12 is rejected by claim 21 of U.S. Patent No. 12171058.
Claim 13 is rejected by claim 22 of U.S. Patent No. 12171058.
Claim 14 is rejected by claim 23 of U.S. Patent No. 12171058.
Claim 15 is rejected by claim 24 of U.S. Patent No. 12171058.
Claim 16 is rejected by claim 25 of U.S. Patent No. 12171058.
Claim 17 is rejected by claim 26 of U.S. Patent No. 12171058.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 5, 8 – 12, 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20200185299), in view of Choudhury (US 20110147920).
Regarding claim 1, Chang discloses a printed circuit board (PCB) module comprising a multilayer PCB, the multilayer PCB comprising:
a plurality of layers (the multiplayer substrate in Fig. 3A) comprising conductive layers (the metal lines 308) and non-conductive layers (the dielectric routing layer in the redistribution layer 306);
a first outer surface (top surface) and second outer surface (bottom surface) opposite from the first outer surface;
one or more electrical components (top metal layer) coupled to the first outer surface of the multilayer PCB;
one or more electrical contacts (solder bumps 320) coupled to the second outer surface of the multilayer PCB; and
a first embedded semiconductor die (RFIC chip 125 embedded in the molding compound 304) having an active side (top side) facing towards a location of the first outer surface (top surface); wherein
the first embedded semiconductor die comprises a first wireless radio-frequency transceiver (paragraph 69).
Chang does not explicitly disclose the first embedded semiconductor die located between two of the layers of the multilayer PCB.
Choudhury teaches the first embedded semiconductor die (RFIC chip 125, Fig. 1) located between two of the layers (insulating layers and metal layers on top and bottom side of the RFIC chip 125) of the multilayer PCB.
It would have been obvious to one having skill in the art at the effective filing date of the invention to increase number of routing layers in the circuit board in order to accommodate the increasing complexity of the intended circuitry.
Regarding claim 5, Chang discloses the claimed invention as set forth in claim 1. Chang further suggests the multilayer PCB further comprises a second embedded semiconductor die (the second die 402, Fig. 4E & 4F) having an active side facing towards the location of the first outer surface (top surface) or a location of the second outer surface of the multilayer PCB.
Regarding claim 8, Chang discloses the claimed invention as set forth in claim 5. Chang further suggests the second embedded semiconductor die comprises a second wireless radio-frequency transceiver (the chip is a transceiver; paragraph 69).
Regarding claim 9, Chang discloses the claimed invention as set forth in claim 8. Chang further suggests the second wireless radio-frequency transceiver comprises a magnetoinductive transceiver (the antenna controlled by the chip radiating electromagnetic field; paragraph 42).
Regarding claim 10, Chang discloses the claimed invention as set forth in claim 1. Chang further suggests the first embedded semiconductor die has a thickness less than 200 microns (the thickness of the chip is a little thicker than the thickness of layer 310. The thickness of layer 310 is less than 100 µm; paragraph 60).
Regarding claim 11, Chang discloses the claimed invention as set forth in claim 1. Chang further discloses the active side of the first embedded semiconductor die comprises a plurality of electrical pads (pads on top surface of the chip 302 connecting to metal lines 308) connected to respective electric traces in the multilayer PCB.
Regarding claim 12, Chang discloses the claimed invention as set forth in claim 11. Chang further discloses the active side of the first embedded semiconductor die is electrically connected via the plurality of electronic pads (pads on top surface of the chip 302 connecting to metal lines 308) and the respective electric traces to at least one of the one or more electrical components (top metal is antenna array connected to the internal circuitry controlled by the chip; paragraph 47).
Regarding claim 14, Chang discloses the claimed invention as set forth in claim 1. Chang further discloses the one or more electrical contacts comprise solder bump(s) (solder bumps 320, Fig. 3A).
Regarding claim 16, Chang discloses the claimed invention as set forth in claim 1. Chang further suggests the multilayer PCB comprises a unitarily formed multilayer PCB (the substrate in Fig. 3A appears to be a unitary substrate).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20200185299), in view of Choudhury (US 20110147920), in further view of Gouchi (US 20140264737).
Regarding claim 4, Chang discloses the claimed invention as set forth in claim 1.
Chang does not explicitly disclose the active side of the first embedded semiconductor die comprises an antenna coil.
Chang suggests antenna 412, fig. 4I, embedded in the adhesive layer 440.
Gouchi teaches the embedded internal component 3 is an antenna coil (paragraph 32).
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of the antenna in order to maximize the data transmission with other electronic devices.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20200185299), in view of Choudhury (US 20110147920), in further view of Kawano (US 8310837).
Regarding claim 13, Chang discloses the claimed invention as set forth in claim 11.
Chang does not explicitly disclose the one or more electrical components comprise a resistor, a capacitor, an inductor, or any combination of the foregoing.
Kawano suggests the capacitors and coils 251 mounted on the surface of the substrate (Fig. 2; column 7, line 58 - 59).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include capacitor and/or inductor on the surface of the circuit board in order to form a functional circuitry.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20200185299), in view of Choudhury (US 20110147920), in further view of Augustin (US 20200144723).
Regarding claim 15, Chang discloses the claimed invention as set forth in claim 1.
Chang does not explicitly disclose the wireless radio-frequency transceiver comprises a Bluetooth-compliant transceiver.
Augustin suggests Bluetooth being a part of a system working with the patch antenna having the embedded chip (paragraph 58).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include a Bluetooth-compliant feature in the transceiver in order to connect the transceiver to common external wireless electronic devices.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20200185299), in view of Vang (US 20180098162).
Regarding claim 17, Chang discloses the claimed invention as set forth in claim 1.
Chang does not explicitly disclose a head-wearable hearing device configured for use in, or at, an ear of a user, the head-wearable hearing device comprising the printed circuit board (PCB) module of claim 1.
Vang teaches the hearing assistance device having embedded chip in the substrate (Fig. 1A).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use the circuit board with embedded chip in the hearing aid device in order to fit all required component in the limited space of the hearing aid device.
Allowable Subject Matter
Claims 2, 3, 6, 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 2, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the multilayer PCB comprises a keep-out volume between the first outer surface and the active side of the first embedded semiconductor die, the keep-out volume being defined by a keep-out area of the active side of the first embedded semiconductor die and a keep-out height, the keep-out volume being free from electrically conductive materials. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 6, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 & 5, a combination of limitations that the first embedded semiconductor die and the second embedded semiconductor die are separated by at least one of the layers of the multilayer PCB. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chiu (US 20180025986) discloses an embedded chip in the substrate (Fig. 10).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
