DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 21-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tabaru (pub #US 20140149719 A1) in view of Casaletto (pub #US 20150286678 A1).
Regarding claim 21, Tabaru discloses a method (method of operating the processing system in figure 3), comprising: scheduling, by a first scheduler circuit (one of the thread schedulers 210), a first work item for consumption by a first workgroup processing element (arithmetic cores 220 connected to the thread scheduler 210) associated with the first scheduler circuit to produce a set of new work items (paragraph 53, result of reduction operations, which are cumulatively added or multiplied via loops, paragraph 4; details of the repeated reduction operations in figure 6, paragraph 70);
Tabaru discloses thread controller waiting for room in the execution units before dispatching threads (paragraph 42) but does not disclose explicitly redistributing by the first schedule circuit to another scheduler circuit. However, Casaletto discloses distributing, by the first scheduler circuit, at least one new work item of the set of new work items to a second scheduler circuit that is different from the first scheduler circuit (dynamically dispatching work queries between of many coordinator nodes, by using a global manager to communicate with the coordinator nodes based on resources availability, paragraph 21, example system shown in figure 1, details shown in subsequent figures). Furthermore, teachings of Tabaru and Casaletto are from the same field of parallel computing.
Therefore, it would have been obvious before the effective filing date of the invention for a person of ordinary skill in the art to combine teachings of Tabaru with Casaletto by using a global resource manager to coordinate between each thread controller to dynamically assign workload for the benefit of maximizing efficiency of the processor system (paragraph 23, Casaletto)
Regarding claim 22, the above combination discloses the method of claim 21, wherein the first scheduler circuit and the second scheduler circuit are included in one or more accelerated or parallel processors (parallel processing of threads, fundamental principal of the processor system, discussed throughout reference, Tabaru).
Regarding claim 23, the above combination discloses the method of claim 21, wherein the first scheduler circuit and the second scheduler circuit are included in one or more chiplets (semiconductor chips, paragraph 41, Tabaru).
Regarding claim 24, the above combination discloses the method of claim 23, wherein the chiplets are stacked die chiplets (plurality of chips on a substrate, paragraph 41, the multiple layers also shown in figure 3, Tabaru).
Regarding claim 25, the above combination discloses the method of claim 23, wherein each chiplet includes a plurality of scheduling domains (schedulers 210, paragraph 45, Tabaru).
Regarding claim 26, the above combination discloses the method of claim 21, wherein: the first scheduler circuit is part of a first scheduling domain of a scheduling hierarchy (hierarchy showing in figure 3, from upper level controller to thread controller 100, to execution units 200, down to the thread schedulers 210, paragraph 42, 43), the first scheduling domain including a set of workgroup processing elements that includes the first workgroup processing element (shown in figure 3, each scheduler 210 is associated with eight cores, and there are multiple layers of the same design); and the second scheduler circuit is part of a second scheduling domain of the scheduling hierarchy (any other scheduler 210 and associated cores shown in figure 3, Tabaru).
Regarding claim 27, the above combination discloses the method of claim 26, wherein: distributing the at least one new work item is responsive to the first scheduler circuit determining that the set of new work items includes one or more work items that would overload the first scheduling domain if consumed by at least one workgroup processing element of the first scheduling domain (whether a coordinator has enough resources to handle the query, paragraph 21, Casaletto).
Regarding claim 28, the above combination discloses the method of claim 27, wherein determining that the set of new work items includes one or more work items that would overload the first scheduling domain comprises identifying one or more work items having an amplification factor greater than a predetermined threshold (whether a coordinator has enough resources to handle the query, paragraph 21, Casaletto).
Regarding claim 29, the above combination discloses the method of claim 27, wherein determining that the set of new work items includes one or more work items that would overload the first scheduling domain comprises determining a total number of new work items in the set of new work items exceeds a predetermined threshold (whether a coordinator has enough resources to handle the query, paragraph 21, Casaletto).
Regarding claim 30, the above combination discloses the method of claim 26, further comprising: receiving the first work item at the first scheduler circuit responsive to an indication from the first scheduler circuit that one or more workgroup processing elements of the first scheduling domain are idle (when execution unit 200 has completed a thread, or when there is room on the execution unit 200, Tabaru)
Regarding claim 31, the above combination discloses the method of claim 26, wherein the first scheduling domain is associated with a first chiplet and the second scheduling domain is associated with a second chiplet (a plurality of semiconductor chips, paragraph 41, Tabaru).
Regarding claim 32-40, examiner notes these claims similar to claims 21-27, the same grounds of rejection are applied.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM.
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/SCOTT C SUN/Primary Examiner, Art Unit 2181