Prosecution Insights
Last updated: August 17, 2026
Application No. 18/941,175

CACHE ACCESS MANAGEMENT FOR RESILIENCY AND REDUNDANCY

Final Rejection §103
Filed
Nov 08, 2024
Examiner
FAAL, BABOUCARR
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
1y 0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
433 granted / 538 resolved
+25.5% vs TC avg
Moderate +14% lift
Without
With
+14.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
25 currently pending
Career history
572
Total Applications
across all art units

Statute-Specific Performance

§101
6.9%
-33.1% vs TC avg
§103
50.3%
+10.3% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Krasner et al. 20210096997 herein Krasner and Suryanarayana 20230034837 herein Suryanarayana in view of Patel et al. 20100274890 herein Patel. Per claim 1, Krasner discloses: establishing, by a host system that hosts virtual machines, access to a network-accessible cache device, wherein the network-accessible cache device is provided by a remote system across a network between the host system and the remote system, (fig. 1A&B, ¶0024; a storage array 100 maintains data for a host application 101 running on a host computer 102. In one embodiment, pages of associated metadata are maintained in a persistent (non-volatile) metadata static storage (e.g., static storage 203 of FIG. 1B). The host computer 102 may be a server with volatile memory 108, persistent storage 110, one or more tangible processors 112, and an OS (operating system) 114. The host computer 102 can support virtual hosts running on virtual machines or containers, and although an external host computer is illustrated, internal hosts may be instantiated within the storage array 100.) and wherein the establishing the access provides access to the network-accessible cache device to virtual input/output (I/O) servers in the host system; (fig. 1A&B, ¶0024; The host computer 102 may be a server with volatile memory 108, persistent storage 110, one or more tangible processors 112, and an OS (operating system) 114. The host computer 102 can support virtual hosts running on virtual machines or containers, and although an external host computer is illustrated, internal hosts may be instantiated within the storage array 100) and provides failover recovery to recover from a failed virtual I/O server of the virtual I/O servers (¶0024; Pairs of the computing nodes, e.g. (116.sub.1, 116.sub.2) and (116.sub.3, 116.sub.4), may be organized as storage engines 118.sub.1, 118.sub.2, respectively, for purposes of failover.). Krasner discloses host, virtual machines and network accessible caches wherein the cost and the storage can be implemented does not specifically disclose: virtualizing the network-accessible cache device into cache partitions in the host system, the cache partitions being of a cache pool of in the host system, wherein each cache partition of the cache partitions in the host system is assigned to cache data accessed by a respective virtual machine of the virtual machines hosted by the host system, and each of the virtual I/O servers in the host system has access to the cache partitions in the host system; and managing accesses to the cache partitions in the host system by the virtual I/O servers in the host system in handing access requests by the virtual machines hosted by the host system to access the cache partitions in the host system, wherein the managing load balances virtual machine access requests to access an assigned cache partition of the cache partitions in the host system across multiple virtual I/O servers of the virtual I/O servers in the host system. However, Suryanarayana discloses: virtualizing the network-accessible cache device into cache partitions in the host system, the cache partitions being of a cache pool of in the host system, wherein each cache partition of the cache partitions in the host system is assigned to cache data accessed by a respective virtual machine of the virtual machines hosted by the host system, and each of the virtual I/O servers in the host system has access to the cache partitions in the host system; (fig. 4, claim 1; the host processor comprising a plurality of processing cores for running virtual machines (VMs) and/or containers, and a cache memory which is shared by the plurality of processing cores; ... the host processor executes a first boot service to create page-sized cache namespaces within the cache memory and initialize the page-sized cache namespaces within a cache page namespace table; and wherein during OS runtime, the host processor executes the ACPI runtime service to dynamically partition the cache memory based on VM/container application workload and map dynamically created cache partitions to the VMs/containers by assigning a number of the page-sized cache namespaces included within the cache page namespace table to each VM/container) and managing accesses to the cache partitions in the host system by the virtual I/O servers in the host system in handing access requests by the virtual machines hosted by the host system to access the cache partitions in the host system, (fig. 4, claim 1; the host processor executes the ACPI runtime service to dynamically partition the cache memory based on VM/container application workload and map dynamically created cache partitions to the VMs/containers by assigning a number of the page-sized cache namespaces included within the cache page namespace table to each VM/container). It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Krasner and Suryanarayana’s virtualized multi processor cache sharing to effectively isolate applications running on the virtual machines. Suryanarayana improves security and performance of a shared cache (¶0014; he techniques described herein may be used to improve the security and performance of a shared last level cache (LLC) contained within a multi-core host processor included within a virtualized and/or containerized IHS. In the disclosed embodiments). The combined teachings of Krasner and Suryanarayana does not specifically disclose: wherein the managing load balances virtual machine access requests to access an assigned cache partition of the cache partitions across multiple virtual I/O servers of the virtual I/O servers. However, Patel in an analogous art discloses: wherein the managing load balances virtual machine access requests to access an assigned cache partition of the cache partitions in the host system across multiple virtual I/O servers of the virtual I/O servers in the host system (fig. 1B, ¶0031; While memory 152 can be segmented across virtual machines cache is often shared, i.e., each virtual machine may be have a more-or-less dedicated partition of memory 152 (mapping to the virtual memory 132), the cache 155 is shared by all applications running on the physical machine 120. Thus, if a high degree of cache contention is observed, the load balancer 110 may reduce the number of requests assigned to the virtual machines 130 until the cache contention is observed to decline). It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Krasner, Suryanarayana and Patel’s feedback agent for load balancing to compensate for traffic across the network. Patel improves the throughput of the virtual environment (¶0036; the feedback agent 141 running as part of the hypervisor 140 provides the load balancer 110 with a direct view of the system hardware 150 to allow better virtual environment management. For example, the feedback agent 141 can provide available network bandwidth of the physical machine 120 for related applications to avoid, e.g., oversubscription of the NIC). Per claim 2, Patel discloses: determining to transition handling of at least some access requests by one virtual machine of the virtual machines hosted by the host system to a cache partition assigned to the one virtual machine from one virtual I/O server of the virtual I/O servers in the host system to another virtual 11O server of the virtual I/O servers in the host system, the another virtual I/O server also handling access requests by another virtual machine of the virtual machines hosted by the host system to a cache partition assigned to the another virtual machine; and transitioning the handling of the at least some access requests to the another virtual I/O server (¶0030; the feedback agent 141 may provide the load balancer with status and load data for each virtual machine managed by the hypervisor 140. The load balancer 110 then forwards each new request to one of the web servers running on a target virtual machine, based in part on the feedback information provided by the feedback agent 141. The server on the target virtual machine 130 can generate a response to the request and send the response through the system hardware 150 via the network 102 to the client 103; the examiner notes that the transition the handling of the request as load balancing based on the status of the load). Per claim 3, Patel discloses: wherein the determining to transition includes recognizing a failure of the one virtual I/O server, and wherein the transitioning is performed automatically based on the determining (¶0026; The load balancer 110 is configured to distribute tasks among multiple virtual machines 130, according to availability information of different resources on each individual virtual machine. Examples of availability information includes central processing unit (CPU) loads, memory/cache usage, cache performance, network interface controller (NIC) usage, storage unit usage, or performance metrics related other hardware, as well as combinations of usage information. Also, as noted above, when one of the virtual machines 130 is being migrated from one physical host to another, the load balancer may drop any traffic addressed to a port on that host; the examiner notes that while Patel does not explicitly teach failure, the availability of the server is monitored. Further Patel discloses migrating of the VM’s. Krasner discloses failover and the combine teaching would suggest a failure of a server and migrating the VM and requests.). Per claim 4, Patel discloses: wherein the determining to transition includes recognizing that a workload of the one virtual I/O server exceeds a threshold, and wherein the transitioning is performed automatically based on the determining (¶0026; The load balancer 110 is configured to distribute tasks among multiple virtual machines 130, according to availability information of different resources on each individual virtual machine. Examples of availability information includes central processing unit (CPU) loads, memory/cache usage, cache performance, network interface controller (NIC) usage, storage unit usage, or performance metrics related other hardware, as well as combinations of usage information. Also, as noted above, when one of the virtual machines 130 is being migrated from one physical host to another, the load balancer may drop any traffic addressed to a port on that host; ¶0049). Per claim 5, Patel discloses: wherein the recognizing is based on information provided from at least one selected from the group consisting of the one virtual machine and the one virtual I/O server (¶0033; the feedback agent may report on the availability of a given virtual machine 130, taking into account both the availability of the physical machine 120 and the availability of the given virtual machine 130. That is, the feedback agent 141 running on the hypervisor 140 may provide the load balancer 110 with information regarding each virtual machine executing over hypervisor 140. However, because the hypervisor 140 can monitor actual loads on system hardware 150 as well as loads on the virtual devices, (e.g., virtual CPU 133), the hypervisor can provide the load 110 balancer with more useful information about the status and loads being experienced on the virtual machines 130. In turn, this allows the load balancer 110 to make better balancing decisions when distributing work requests to a cluster of virtualized systems (i.e., to the virtual machines 130).). Per claim 6, Patel discloses: wherein the virtual I/O servers in the host system exchange heartbeat information, and wherein the determining to transition is made by at least one virtual I/O server of the virtual I/O servers in the host system based on the exchanged heartbeat information (¶0037; load and status information regarding the performance of individual virtual machines 130 may be monitored. The performance metrics of each virtual machine 130 may be obtained from the hypervisor 140. For example, the feedback agent 141 may invoke API calls provided by the hypervisor 140 to obtain load and status information (CPU loads, memory usage, I/O operations, network congestion, etc.) related to the virtual hardware devices exposed to each virtual machine 130). Per claim 7, Patel discloses: w herein the provided network-accessible cache device includes dynamic random access memory of the remote system (¶0024; Each computing node 116 includes at least one tangible multi-core processor 122 and a local cache 124. The local cache 124 may include, for example and without limitation, volatile memory components such as RAM (random access memory)). Per claim 8, Patel discloses: wherein the provided network-accessible cache device is presented to the host system via a cache-coherent network interconnect protocol (¶0037; the feedback agent 141 may invoke API calls provided by the hypervisor 140 to obtain load and status information (CPU loads, memory usage, I/O operations, network congestion, etc.) related to the virtual hardware devices exposed to each virtual machine 130; the examiner notes that an API is a type of cache coherent network interconnect protocol). Claims 9-14 are the system claims corresponding to the method claims 1-8 and are rejected under the same reasons set forth in connection with the rejection of claims 1-8. The rejection is silent to the computer readable storage media. However, Kransner in ¶0047 discloses: The above-described systems and methods can be implemented in digital electronic circuitry, in computer hardware, firmware, and/or software. The implementation can be as a computer program product. The implementation can, for example, be in a machine-readable storage device, for execution by, or to control the operation of, data processing apparatus. Claims 15-20 are the computer program product claims corresponding to the method claims 1-8 and are rejected under the same reasons set forth in connection with the rejection of claims 1-8. Response to Arguments Applicant’s arguments, see pg. 10, filed 3/10/26, with respect to the rejection(s) of claim(s) 1, 9 and 15 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Suryanarayana. Remark Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim VO can be reached at 5712723642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BABOUCARR . FAAL Primary Examiner Art Unit 2138 /BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Read full office action

Prosecution Timeline

Nov 08, 2024
Application Filed
Dec 10, 2025
Non-Final Rejection mailed — §103
Mar 10, 2026
Response Filed
Jun 23, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
95%
With Interview (+14.5%)
2y 10m (~1y 0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allowance rate.

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