Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over to Podsiadlo et al., (US 10,210,130) and Granfer-Jones et al., (US 9,602,146).
It has been noted that, a claimed invention is unpatentable if the differences between it and the prior art are "such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art." 35 U.S.C. § 103(a) (2000); KSRInt'lr. Teleflex Inc., 127 S.Ct. 1727, 1734 (2007); Graham v.John Deere Co., 383 U.S. 1, 13-14 (1966).
In Graham, the Court held that that the obviousness analysis is bottomed on several basic factual inquiries: "[(1)] the scope and content of the prior art are to be determined; [(2)] differences between the prior art and the claims at issue are to be ascertained; and [(3)] the level of ordinary skill in the pertinent art resolved." 383 U.S. at 17. See also KSR, 127 S.Ct. at 1734. "The combination of familiar elements according to known methods is likely to be obvious when it does no more; than yield predictable results." KSR, at 1739.
"When a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or in a different one. If a person of ordinary skill in the art can implement a predictable variation, § 103 likely bars its patentability." Id. at 1740.
"For the same reason, if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill." Id.
"Under the correct analysis, any need or problem known in the field of endeavor at the time of invention and addressed by the patent can provide a reason for combining the elements in the manner claimed." Id. 11742.
As per claim 1, Podsiadlo teaches a system (col. 1, lines 22-47) comprising: a serial bus (MIPI, col. 2, lines 28-31); a first module (IC, 202, Figs. 2-5) coupled to the serial bus, the first module being disposed on a first semiconductor die (col. 2, lines 18-27), including a first switch (col. 5 ,lines 23-26), and being configured to write to a first user identifier (USID, col. 2, lines 32-34, col. 10, lines 37-col. 11, lines 1-40, Fig. 5, Tables 2 and Table 3, Figs.6a,6b); and a second module (IC, 206, Fig. 2-5) coupled to the serial bus (MIPI, col. 2, lines 28-31), the second module being disposed on a second semiconductor die (col. 2, lines 18-27), including a second switch (col. 5 ,lines 23-26), and being configured to write to a second USID (USID, col. 2, lines 32-34, col. 10, lines 37-col. 11, lines 1-40, Fig. 5, Tables 2 and Table 3, Figs.6a,6b).
Podsiadlo discloses a multi-IC module layout of multiple radio frequency (RF) circuit elements, including integrated circuits (ICs) each configured with a unique address (USID), within a circuit module, while sending and receiving data on a Mobile Industry Processor Interface (MIPI) serial bus. MIPI RFFE serial bus is described as a serial, two-wire, master/slave interface originally designed for controlling a variety of RF front end devices, such as amplifiers, antenna switches, filters, etc. Therein, Podisiadlo would obviously include individual switches connected to each IC.
Nonetheless, Granger-Jones teaches a wireless device comprising a front-end module including a switch (34 or 36) and another front-end module including another separate switch (84). Further, each module is coupled to a respective antenna port (30 or 82, Fig. 4) outside of the front-end module whereas the connected switching circuitry chooses a high, mid, and low band filter modes. (See conventional RF front end circuitry of Fig. 4, Grander-Jones, col. 3, lines 52—col. 4, lines 1-9, col. 5, lines 9-64)
It would have been obvious at the time of the invention to one of ordinary skill before the effective filing date to incorporate the conventional RF front end circuitry design that is configured to support one or more carrier aggregation configurations as taught by Grander-Jones into Podisiadlo’s multi-IC module layout of multiple radio frequency (RF) circuit elements configured to operate on a MIPI bus. Doing so would improve mobile telecommunication performance demands by supporting one or more carrier aggregation configurations (data exchange/data rates). (Grander-Jones, col. 12, lines 14-22)
As per claims 12 and 17, Polisiadlo-Grander-Jones in combination teaches a packaged module and Granger-Jones teaches a wireless device. See the rejection for claim 1.
As per claim 2, 13, and 18, Polisiadlo-Grander-Jones teaches wherein the second module further comprises a third switch and wherein the second module is further configured to write to the first USID and the second USID. Grander-Jones’s Fig. 4 shows a similar circuitry design of Applicant’s Fig. 2 (See Applicant’s drawing for Fig.2) Specifically, 38 (LB/MB/HB) + switching circuitry, 34 ++ 40(LB/MB/HB) + switching circuity 36 coupled to antenna, 30.
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Podsiadlo discloses a multi-IC module layout of multiple radio frequency (RF) circuit elements, including integrated circuits (ICs) each configured with a unique address (USID). Note Fig. 4, in one design a third IC 402 (col. 8, lines 22-29) or Note Fig. 6 whereas ICs configured with a unique address (USID) – col. 14, lines 30-47. Therein, it would have been obvious to one ordinary skill before the effective filing date the combination including Granger-Jones teachings wherein the antenna ports include a low-band antenna port, a mid-band antenna port, or a high-band antenna port (col. 3, line 37-col. 4, lines 1-9, col. 10, lines 36-47)
As per claim 3, Polisiadlo-Grander-Jones teaches wherein the first module is further configured to readback (some implementations of the MIPI RFFE serial bus, only two command types are supported: Register Read (for reading status information from a slave device) and Register Write (for providing control information to a slave device, Polisiadlo, col, 5, lines 53-55) the first (“..an internal device address (i.e. a USID) of “0001”…”1000”..specifies a “Register Write”USID, Polisiadlo, USID, col. 2, lines 32-34, col. 10, lines 37-col. 11, lines 1-40, Fig. 5, Tables 2 and Table 3, Figs.6a,6b)
As per claim 4, Polisiadlo-Grander-Jones teaches wherein the second module is further configured to readback the second USID. (“..an internal device address (i.e. a USID) of “0001”…”1000”..specifies a “Register Write”USID, Polisiadlo, USID, col. 2, lines 32-34, col. 10, lines 37-col. 11, lines 1-40, Fig. 5, Tables 2 and Table 3, Figs.6a,6b)
As per claim 5 and 14, Polisiadlo-Grander-Jones teaches wherein the second module comprises a diplexer (32, Fig. 4) coupled to the second switch and the third switch. (Grander-Jones, “…Further, the diplexer 32 is configured to route only mid-band signals (rather than both mid-band and high-band signals) between the antenna 30 and the mid-band switching circuitry 36, while attenuating other signals,” col.3, lines 59-62)
As per claim 6, Polisiadlo-Grander-Jones teaches further comprising a first antenna (30, antenna, Fig. 4) coupled to the diplexer. (Grander-Jones, “…Further, the diplexer 32 is configured to route only mid-band signals (rather than both mid-band and high-band signals) between the antenna 30 and the mid-band switching circuitry 36, while attenuating other signals,” col.3, lines 59-62)
As per claim 7, Polisiadlo-Grander-Jones teaches further comprising a second antenna coupled to the first switch. (Note Fig. 4 of Grander-Jones)
As per claim 8, Polisiadlo-Grander-Jones teaches wherein the first switch is a high-band switch, the second switch is a medium-band switch, and the third switch is a low-band switch. Granger-Jones teachings wherein the antenna ports include a low-band antenna port, a mid-band antenna port, or a high-band antenna port (col. 3, line 37-col. 4, lines 1-9, col. 10, lines 36-47) Therein, based on Fig. 4, any combination could be implemented and not depart from the inventive concept.
As per claim 9, 15, and 19, Polisiadlo-Grander-Jones teaches further comprising a third module coupled to the serial bus, the third module (402, Polisiadlo) being disposed on a third semiconductor die, including a third switch (Grander-Jones – Fig. 4 above shows individual switch), and being configured to write to the first USID. Note Polisiadlo, Fig. 4, in one design a third IC 402 (col. 8, lines 22-29) or Note Fig. 6 whereas ICs configured with a unique address (USID) – col. 14, lines 30-47. Therein, it would have been obvious to one ordinary skill before the effective filing date the combination including Granger-Jones with Polisiadlo teachings wherein a third modules including a third switch being configured to write to the first USID. (Polisiadlo, col. 3, line 37-col. 4, lines 1-9, col. 10, lines 36-47)
As per claim 10, 16, and 20, Polisiadlo-Grander-Jones teaches wherein the first module is configured to readback the first USID, the second module is configured to readback the second USID, and the third module is not configured to readback any USIDs. Polisiadlo teaches “fictionalize or “spoof” such data so that a response valid in form is provided to the master deivce,” col. 10, lines 24-36. Both Polisiadlo-Grander-Jones discloses at least 3 or more modules wherein Polisaidlo discloses that some commands could be a non-broadcast command. (col. 12, lines 13-16)
As per claim 11, Polisiadlo-Grander-Jones teaches wherein each of the first switch, the second switch, and the third switch is coupled to a separate antenna. (Note Grander-Jones, “For example, a dual feed antenna may be used, or separate antennas for low-band signals and mid/high-band signals may be used without departing from the principles of the present disclosure,” col. Col. 10, lines 36-47)
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c). 3. ZHANG ET AL., (US 10,727,893) teaches reconfigurable front-end module for carrier aggregation. (Abstract); YU ET AL., (US 12,317,333) and CHEN (US 2024/0106491) both teach a method for controlling transmission of an electronic device having at least two transmission modules. (Abstract)
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/Primary Examiner, Art Unit 2184
March 13, 2026
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