DETAILED ACTION
The instant action is in response to application 8 November 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 14 August 2024.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
As to claim 5, applicant claims a triode. However, the drawings appear to refer to the triodes as bipolar junction transistors. Though the control mesh between the cathode and anode acts similarly to a gate of a bjt, the Vacuum tube as well as filaments means that they behave slightly differently, and also triodes may generate a fair amount of heat. Also, the circuit diagrams appear to show BJTs rather than triodes, and any claimed subject matter must be shown in the drawings. Rephrased simply, it is not readily apparent if applicant meant to claim a BJT or a triode, and for the purposes of examination it will be assumed applicant claimed a BJT.
Claims 6 depend directly or indirectly from a rejected claim and are, therefore, also rejected under 35 USC 112(b) , or 35 U.S.C. 112 (pre-AIA ) second paragraph for the reasons set above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Hari (US 20150381039)
Hari discloses a boost circuit, comprising a controller, an inductor, a switch transistor, a voltage sampling circuit and a current sampling circuit, wherein the controller is electrically connected to a first terminal (gate) of the switch transistor, a first terminal (node R1/R2) of the voltage sampling circuit and a first terminal (R3/C1) of the current sampling circuit, the inductor is electrically connected to a power supply and a second terminal (source) of the switch transistor and is configured to be electrically connected to an external load, a third terminal (drain) of the switch transistor is electrically connected to a second terminal (RCS) of the current sampling circuit, and a second terminal of the voltage sampling circuit is electrically connected to the inductor.
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As to claim 2, Hari discloses wherein the current sampling circuit comprises a first resistor (RCS) and a second resistor (R3), one terminal of the first resistor is electrically connected to the third terminal of the switch transistor and one terminal of the second resistor, the other terminal of the first resistor is grounded, and the other terminal (input to 51) of the second resistor is electrically connected to a current detection terminal of the controller.
Claim(s) 1, 10 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Moretti (US 20230283168)
As to claim 1, Moretti (see image below) discloses A boost circuit, comprising a controller, an inductor, a switch transistor, a voltage sampling circuit and a current sampling circuit, wherein the controller is electrically connected to a first terminal (gate) of the switch transistor, a first terminal (node R1/R2) of the voltage sampling circuit and a first terminal (CSV) of the current sampling circuit, the inductor is electrically connected to a power supply and a second terminal (source) of the switch transistor and is configured to be electrically connected to an external load (PVDD), a third terminal (drain) of the switch transistor is electrically connected to a second terminal of the current sampling circuit (input), and a second terminal of the voltage sampling circuit is electrically connected to the inductor (connected through the synchronous rectifier).
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As to As to claim 10, Moretti teaches a lighting device, comprising the boost circuit according to Claim 1 (Fig. 11, display panel).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hari (US 20150381039) in view of Tallam (US 20200041559).
As to claim 3, Hari discloses wherein the voltage sampling circuit comprises a third resistor, a fourth resistor
Tallam teaches wherein the voltage sampling circuit comprises a third resistor (R2), a fourth resistor (R3), a fifth resistor (R4) and a snubber circuit (R5, C4), one terminal of the third resistor is electrically connected to one terminal of the snubber circuit, the other terminal of the third resistor is electrically connected to one terminal of the fourth resistor, the other terminal of the fourth resistor is electrically connected to one terminal of the fifth resistor, the other terminal of the snubber circuit and a feedback voltage input terminal of the controller (200), and the other terminal of the fifth resistor is grounded (Note that all resistors and snubbers are shown, and though broadly interpreted they are electrically connected since an electron could theoretically flow between one point to another via circuitry. Even a narrower interpretation however, would generally be regarded as obvious per MPEP 2144.04 VI C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use the voltage divider as disclosed in Tallam to reduce high frequency noise.
As to claim 4, Hari in view of Tallam teaches wherein the snubber circuit comprises a sixth resistor and a first capacitor, the sixth resistor is electrically connected to one terminal of the third resistor and one terminal of the first capacitor, and the other terminal of the first capacitor is electrically connected to the other terminal of the fourth resistor (this would be taught by the combination, with the RC snubber being connected to the divider).
Claims 5-6 (as best understood) are rejected under 35 U.S.C. 103 as being unpatentable over Hari (US 20150381039) in view of Marcinkiewicz (US 20170302214).
As to claim 5, Hari does not disclose further comprising a first triode, a second triode and a seventh resistor, wherein a first terminal of the first triode is electrically connected to the power supply, a second terminal of the first triode is electrically connected to the seventh resistor and a first terminal of the second triode, a third terminal of the first triode is electrically connected to a second terminal of the second triode and the first terminal of the switch transistor, a third terminal of the second triode is grounded, and the other terminal of the seventh resistor is electrically connected to an output terminal of the controller.
Marcinkiewicz (Fig. 5A) teaches further comprising a first triode (510), a second triode (512) and a seventh resistor, wherein a first terminal of the first triode (collector) is electrically connected to the power supply (15V), a second terminal (emitter) of the first triode is electrically connected to the seventh resistor (R160) and a first terminal (collector) of the second triode, a third terminal (base) of the first triode is electrically connected to a second terminal (base) of the second triode and the first terminal of the switch transistor, a third terminal (emitter) of the second triode is grounded, and the other terminal of the seventh resistor is electrically connected to an output terminal of the controller (connects to gate of FET).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use the driver as disclosed in Marcinkiewicz to have more control over the gate signal.
As to claim 6, Hari in view of Marcinkiewicz teaches further comprising an eighth transistor (520) and a ninth resistor (165), wherein one terminal of the eighth resistor is electrically connected to the first terminal (collector/ground) of the switch transistor, the other terminal of the eighth transistor is electrically connected to the third terminal of the first triode (connected via R160), and the ninth resistor is electrically connected to the first terminal and the third terminal of the switch transistor (it is between gate and drain).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hari (US 20150381039) in view of Liu (US 20170353121).
Hari teaches further comprising a rectifier (D2, HD2) and filter circuit (C0) and a first diode (D1), wherein one terminal of the rectifier and filter circuit is electrically connected to the inductor, the other terminal of the rectifier and filter circuit is configured to be electrically connected to the external load
Hari , a positive pole of the first diode is electrically connected to the power supply, and a negative pole of the first diode is electrically connected to the rectifier and filter circuit.
Liu teaches a positive pole of the first diode is electrically connected to the power supply, and a negative pole of the first diode is electrically connected to the rectifier and filter circuit (item 7, ¶21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use a bypass as disclosed in Liu to reduce switch stress.
Allowable Subject Matter
Claims 8-9 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 8, the prior art fails to disclose: “wherein the rectifier and filter circuit comprises a second diode, a second capacitor, a common-mode choke, a third capacitor and a tenth resistor, a positive pole of the second diode is electrically connected to the inductor, a negative pole of the second diode is electrically connected to a first terminal of the common-mode choke and the negative pole of the first diode, one terminal of the second capacitor is electrically connected to a negative pole of the second diode, the other terminal of the second capacitor is grounded, a second terminal of the common-mode choke is electrically connected to one terminal of the tenth resistor, a third terminal and a fourth terminal of the common-mode choke are electrically connected to the external load, the other terminal of the tenth resistor is grounded, and the third capacitor is eclectically connected to the third terminal and the fourth terminal of the common-mode choke.” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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