DETAILED ACTION
This Office action is in response to an application filed on 8 October 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were filed on 8 October 2024. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 5-6, 8-14, 16-22, and 24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoshida et al. (US 2019/0317543 A1; hereinafter “Yoshida”).
In re claim 1, Yoshida discloses a circuit (Figs. 1, 3), comprising: a reference voltage source (10); an output (VGB, 1) coupled to the reference voltage source, the output for providing a reference voltage; a temperature sensing diode (Page 3, ¶ [0034]: diode-connected npn transistor Q8 connected between a common connection point of the resistors R5, R6 and the ground GND, and an npn transistor Q9 diode-connected to a collector of the transistor Q7) circuit (20); a first amplifier (30) having a first input coupled in a path to the reference voltage source (10) and a second input coupled in a path to a terminal of the temperature sensing diode (30 to Q9, shown in Fig. 3) circuit; a first transistor (Q12) including a control terminal coupled to an output of the first amplifier and a first current (i1) terminal to provide a correction current ([0035] i1 x (R22 +R23)) for adjusting the reference voltage in response to the temperature sensing diode circuit (Q5-9) indicating that a first temperature is being exceeded (see Abstract: a high temperature correction circuit (30) configured to increase a reference voltage generating circuit main body); a second amplifier (30) including a first input coupled in a path to the reference voltage source (10) and a second input coupled in a path to the terminal of the temperature sensing diode circuit (40 to Q8, shown in Fig. 3); a second transistor (Q15) including a control terminal coupled to an output of the second amplifier and a first current terminal for providing a correction current ([0035] i2 x R23) for adjusting the reference voltage in response to the temperature sensing diode circuit indicating that the temperature is below a second temperature (see Abstract: a low temperature correction circuit (40) configured to increase a reference voltage generated by the reference voltage generating circuit main body).
In re claim 2, Yoshida discloses a circuit (claim 1 rejection), wherein a second current terminal of the first amplifier (30) is coupled to the first input of the first amplifier (shown in Fig. 3).
In re claim 4, Yoshida discloses a circuit (see rejections above), wherein the first current terminal of the first transistor provides no correction current for adjusting the reference voltage when the temperature sensing diode circuit indicates that the first temperature is not being exceeded (Pg. 4, [0041]: the high temperature correction circuit 30, the collector current of the transistor Q11 is larger than that of the transistor Q12 by V4>V3, most of the collector current of the transistor Q10 flows to the transistor Q11, and the collector current i1 of the transistor Q12 is almost zero).
In re claim 5, Yoshida discloses a circuit (see rejections above), wherein the first amplifier controls the amount of correction current produced by the first current terminal of the first transistor such that a change the amount of the correction current has a positive correlation with a change in temperature when the first temperature is being exceeded (shown in Figs. 2 a-b).
In re claim 6, Yoshida discloses a circuit (see rejections above), wherein a second current terminal of the second transistor is coupled to the second input of the second transistor (see Fig. 3).
In re claim 8, Yoshida discloses a circuit (see rejections above), wherein the first current terminal of the second transistor (Q15 in Fig. 3) provides no correction current for adjusting the reference voltage in response to the temperature sensing diode circuit indicating that the temperature is not below the second temperature ([0039]: In the low temperature correction circuit 40, a collector current of the transistor Q14 is larger than that of the transistor Q15 by V1>V4, most of a collector current of the transistor Q13 flows through the transistor Q14, and the collector current i2 of the transistor Q15 is almost zero).
In re claim 9, Yoshida discloses a circuit (see rejections above), wherein the second amplifier controls the amount of correction current produced by the first current terminal of the second transistor such that a change in the amount of correction current has a positive correlation with a negative change in temperature when the temperature is below the second temperature (see Figs. 2 a-c).
In re claim 10, Yoshida discloses a circuit (see rejections above and Figs. 1 and 3), wherein the output (1) is provided by a node in an output current path, wherein the correction current provided by the first current terminal of the first amplifier and the correction current provided by the first current terminal of the second amplifier are provided across a resistive circuit (shown in 10 of Fig. 3) of the output current path to adjust the reference voltage.
In re claim 11, Yoshida discloses a circuit (see rejections above and Figs. 1 and 3) comprising a resistive path, from the reference voltage source to a power supply rail, wherein the first input of the first amplifier is coupled to a first node of the resistive path and the first input of the second amplifier is coupled to a second node of the resistive path, wherein a resistive circuit is located in the resistive path between the first node and the second node.
In re claim 12, Yoshida discloses a circuit (see rejections above and Fig. 3), wherein the terminal of the temperature sensing diode circuit is coupled to the reference voltage source through a biasing current path (R5-7).
In re claim 13, Yoshida discloses a circuit (see rejections above and Fig. 3), wherein the second input of the second amplifier is coupled to a node of the biasing current path through at least one resistive circuit.
In re claim 14, Yoshida discloses a circuit (see rejections above), wherein the reference voltage source is characterized as a bandgap voltage source and the reference voltage is characterized as a bandgap reference voltage (10 in Fig. 3).
In re claim 16, Yoshida discloses a circuit (see rejections above and see Fig. 3), wherein the output is coupled to the reference voltage source through at least one resistive (R1, R21) circuit.
In re claim 17, Yoshida discloses a circuit (see rejections above and see Fig. 3), temperature sensing diode circuit includes a bipolar transistor (Q9) with its base connected to its collector.
In re claim 18, Yoshida discloses a circuit (see rejections above and see Fig. 3), wherein the first current terminal of the first transistor and the first current terminal of the second transistor are connected together (N1-2).
In re claim 19, Yoshida discloses a circuit (see rejections above and see Fig. 3), wherein at least one resistive circuit (R22) is located in path between the first current terminal of the first transistor and the first current terminal of the second transistor.
In re claim 20, Yoshida discloses a circuit (see rejections above and see Fig. 3), wherein the output is connected to a node of a current path from the reference voltage source to a power supply rail (VCC) wherein the correction current from the first current terminal of the first transistor and the correction current from the first current terminal from the second transistor are each provided through a resistive circuit (R1, R21-23) located in the current path between the power supply rail and the node of the path.
In re claim 21, Yoshida discloses a circuit (see rejections above and Figs. 1,3), comprising: a reference voltage source (10); an output path from the reference voltage source to a power supply rail (VCC); an output (1) connected to a node of the output path for providing a reference voltage; a temperature sensing diode circuit (Q5-9); a first amplifier (30) having a first input coupled in a path to the reference voltage source (shown in Fig. 3) and a second input coupled in a path to a terminal of the temperature sensing diode circuit; a first transistor (Q12) including a control terminal coupled to an output of the first amplifier and a first current terminal to provide a correction current (i1) for adjusting the reference voltage in response to the temperature sensing diode circuit indicating that a first temperature is being exceeded; a second amplifier (30) including a first input coupled in a path to the reference voltage source and a second input coupled in a path to the terminal of the temperature sensing diode circuit; a second transistor (Q15) including a control terminal coupled to an output of the second amplifier and a first current terminal for providing a correction current (i2) for adjusting the reference voltage in response to the temperature sensing diode circuit indicating that the temperature is below a second temperature; wherein a second current terminal of the first amplifier is coupled to the first input of the first amplifier; wherein a second current terminal of the second transistor is coupled to the second input of the second transistor (shown in Fig. 3).
In re claim 22, Yoshida discloses a circuit (see rejections above and see Fig. 3), wherein: the output path includes a resistive circuit (R1, R21-23) coupled in the path between the node and the power supply rail, wherein the correction current (i1) from the first current terminal of the first transistor for adjusting the reference voltage in response to the temperature sensing diode circuit indicating that the first temperature is being exceeded flows through the resistive circuit to adjust the reference voltage; the correction current (i2) from the first current terminal of the second transistor for adjusting the reference voltage in response to the temperature sensing diode circuit indicating that the temperature is below the second temperature flows through the resistive circuit to adjust the reference voltage (shown in Figs. 2a-c).
In re claim 24, , Yoshida discloses a circuit (see rejections above and see Figs. 2a-3), wherein: the first current terminal of the first transistor provides no correction current for adjusting the reference voltage when the temperature sensing diode circuit indicates that the first temperature is not being exceeded (Pg. 4, [0041]: the high temperature correction circuit 30, the collector current of the transistor Q11 is larger than that of the transistor Q12 by V4>V3, most of the collector current of the transistor Q10 flows to the transistor Q11, and the collector current i1 of the transistor Q12 is almost zero); the first current terminal of the second transistor provides no correction current for adjusting the reference voltage in response to the temperature sensing diode circuit indicating that the temperature is not below the second temperature ([0039]: In the low temperature correction circuit 40, a collector current of the transistor Q14 is larger than that of the transistor Q15 by V1>V4, most of a collector current of the transistor Q13 flows through the transistor Q14, and the collector current i2 of the transistor Q15 is almost zero).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 7, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 2019/0317543 A1; hereinafter “Yoshida”) in view of Mori (US 2013/0285732 A1; hereinafter “Mori”).
In re claim 3, Yoshida discloses a circuit (see above rejections), wherein when the temperature sensing diode circuit indicates that the first temperature is being exceeded, the first amplifier drives its output.
Yoshida does not disclose the first amplifier drives its output at a voltage to control the conductivity of the first transistor such that the voltage of the first input of the first amplifier matches the voltage of the second input of the first amplifier.
Whereas, Mori discloses a similar circuit (Fig. 1), wherein an amplifier (22 and 19) drives its output at a voltage to control the conductivity of a transistor (18) such that the voltage of an input of the amplifier matches the voltage of the second input of the amplifier (shown in Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the circuit of Yoshida such that “the first amplifier drives its output at a voltage to control the conductivity of the first transistor such that the voltage of the first input of the first amplifier matches the voltage of the second input of the first amplifier” as shown by Mori. The selection of “the first amplifier drives its output at a voltage to control the conductivity of the first transistor such that the voltage of the first input of the first amplifier matches the voltage of the second input of the first amplifier” would be a routine matter to the person of ordinary skill to have better control and response, as taught by Mori, cited above.
In re claim 7, Yoshida discloses a circuit (see above rejections), wherein when the temperature sensing diode circuit indicates that the second temperature is being exceeded, the second amplifier drives its output.
Yoshida does not disclose the second amplifier drives its output at a voltage to control the conductivity of the second transistor such that the voltage of the second input of the second amplifier matches the voltage of the first input of the second amplifier.
Whereas, Mori discloses a similar circuit (Fig. 1), wherein an amplifier (22 and 19) drives its output at a voltage to control the conductivity of a transistor (18) such that the voltage of an input of the amplifier matches the voltage of the second input of the amplifier (shown in Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the circuit of Yoshida such that “the amplifier drives its output at a voltage to control the conductivity of the transistor such that the voltage of the first input of the amplifier matches the voltage of the second input of the amplifier” as shown by Mori. The selection of “the amplifier drives its output at a voltage to control the conductivity of the transistor such that the voltage of the first input of the amplifier matches the voltage of the second input of the amplifier” would be a routine matter to the person of ordinary skill to have better control and response, as taught by Mori, cited above.
In re claim 23, Yoshida discloses a circuit (see above rejections and Figs. 1-3), wherein: when the temperature sensing diode circuit (Q5-9) indicates that a first temperature is being exceeded, the first amplifier drives its output at a voltage to control the first transistor such that the voltage of the first input of the first amplifier matches the voltage of the second input of the first amplifier; when the temperature sensing diode circuit indicates that the temperature is below a second temperature, the second amplifier drives its output at a voltage to control the second transistor such that the voltage of the second input of the second amplifier matches the voltage of the first input of the second amplifier.
Yoshida does not disclose an amplifier drives its output at a voltage to control the conductivity of the transistor.
Whereas, Mori discloses a similar circuit (Fig. 1), wherein an amplifier (22 and 19) drives its output at a voltage to control the conductivity of a transistor (18) such that the voltage of an input of the amplifier matches the voltage of the second input of the amplifier (shown in Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the circuit of Yoshida such that “an amplifier drives its output at a voltage to control the conductivity of the transistor” as shown by Mori. The selection of “an amplifier drives its output at a voltage to control the conductivity of the transistor” would be a routine matter to the person of ordinary skill to have better control and response, as taught by Mori, cited above.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 2019/0317543 A1; hereinafter “Yoshida”).
In re claim 15, Yoshida discloses a circuit (see above rejections), wherein the reference voltage source is characterized as a voltage source and the reference voltage is characterized as a reference voltage.
Yoshida does not disclose the reference voltage source is characterized as a Zener voltage source and the reference voltage is characterized as a Zener reference voltage.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the circuit of Yoshida such that “the reference voltage source is characterized as a Zener voltage source and the reference voltage is characterized as a Zener reference voltage.” The selection of “a Zener voltage source” is a well-known design alternative would be a routine matter to the person of ordinary skill to simplify the system of Yoshida.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Zhou et al. CN 112162585 B A Reference Voltage Generating Circuit
Sakaguchi et al. US 20180284821 A1 VOLTAGE REGULATOR
Zhang US 9261415 B1 System And Method For Temperature Sensing
Cave US 9671800 B2 Bandgap Circuit With Temperature Correction
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas A Chapa Mills whose telephone number is (571)272-3683. The examiner can normally be reached Mon-Fri 9am-6pm.
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/NICOLAS ALDEN CHAPA MILLS/ Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838